1 /* Performance event support for sparc64.
3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
5 * This code is based almost entirely upon the x86 perf event
8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
9 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
10 * Copyright (C) 2009 Jaswinder Singh Rajput
11 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
15 #include <linux/perf_event.h>
16 #include <linux/kprobes.h>
17 #include <linux/ftrace.h>
18 #include <linux/kernel.h>
19 #include <linux/kdebug.h>
20 #include <linux/mutex.h>
22 #include <asm/stacktrace.h>
23 #include <asm/cpudata.h>
24 #include <asm/uaccess.h>
25 #include <linux/atomic.h>
32 /* Sparc64 chips have two performance counters, 32-bits each, with
33 * overflow interrupts generated on transition from 0xffffffff to 0.
34 * The counters are accessed in one go using a 64-bit register.
36 * Both counters are controlled using a single control register. The
37 * only way to stop all sampling is to clear all of the context (user,
38 * supervisor, hypervisor) sampling enable bits. But these bits apply
39 * to both counters, thus the two counters can't be enabled/disabled
42 * The control register has two event fields, one for each of the two
43 * counters. It's thus nearly impossible to have one counter going
44 * while keeping the other one stopped. Therefore it is possible to
45 * get overflow interrupts for counters not currently "in use" and
46 * that condition must be checked in the overflow interrupt handler.
48 * So we use a hack, in that we program inactive counters with the
49 * "sw_count0" and "sw_count1" events. These count how many times
50 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an
51 * unusual way to encode a NOP and therefore will not trigger in
55 #define MAX_HWEVENTS 2
56 #define MAX_PERIOD ((1UL << 32) - 1)
58 #define PIC_UPPER_INDEX 0
59 #define PIC_LOWER_INDEX 1
60 #define PIC_NO_INDEX -1
62 struct cpu_hw_events {
63 /* Number of events currently scheduled onto this cpu.
64 * This tells how many entries in the arrays below
69 /* Number of new events added since the last hw_perf_disable().
70 * This works because the perf event layer always adds new
71 * events inside of a perf_{disable,enable}() sequence.
75 /* Array of events current scheduled on this cpu. */
76 struct perf_event *event[MAX_HWEVENTS];
78 /* Array of encoded longs, specifying the %pcr register
79 * encoding and the mask of PIC counters this even can
80 * be scheduled on. See perf_event_encode() et al.
82 unsigned long events[MAX_HWEVENTS];
84 /* The current counter index assigned to an event. When the
85 * event hasn't been programmed into the cpu yet, this will
86 * hold PIC_NO_INDEX. The event->hw.idx value tells us where
87 * we ought to schedule the event.
89 int current_idx[MAX_HWEVENTS];
91 /* Software copy of %pcr register on this cpu. */
94 /* Enabled/disable state. */
97 unsigned int group_flag;
99 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
101 /* An event map describes the characteristics of a performance
102 * counter event. In particular it gives the encoding as well as
103 * a mask telling which counters the event can be measured on.
105 struct perf_event_map {
108 #define PIC_NONE 0x00
109 #define PIC_UPPER 0x01
110 #define PIC_LOWER 0x02
113 /* Encode a perf_event_map entry into a long. */
114 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
116 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
119 static u8 perf_event_get_msk(unsigned long val)
124 static u64 perf_event_get_enc(unsigned long val)
129 #define C(x) PERF_COUNT_HW_CACHE_##x
131 #define CACHE_OP_UNSUPPORTED 0xfffe
132 #define CACHE_OP_NONSENSE 0xffff
134 typedef struct perf_event_map cache_map_t
135 [PERF_COUNT_HW_CACHE_MAX]
136 [PERF_COUNT_HW_CACHE_OP_MAX]
137 [PERF_COUNT_HW_CACHE_RESULT_MAX];
140 const struct perf_event_map *(*event_map)(int);
141 const cache_map_t *cache_map;
152 static const struct perf_event_map ultra3_perfmon_event_map[] = {
153 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
154 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
155 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
156 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
159 static const struct perf_event_map *ultra3_event_map(int event_id)
161 return &ultra3_perfmon_event_map[event_id];
164 static const cache_map_t ultra3_cache_map = {
167 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
168 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
171 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
172 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
175 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
176 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
181 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
182 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
185 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
186 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
188 [ C(OP_PREFETCH) ] = {
189 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
190 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
195 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
196 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
199 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
200 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
203 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
204 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
209 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
210 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
213 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
214 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
216 [ C(OP_PREFETCH) ] = {
217 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
218 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
223 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
224 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
227 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
228 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
230 [ C(OP_PREFETCH) ] = {
231 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
232 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
237 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
238 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
241 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
242 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
244 [ C(OP_PREFETCH) ] = {
245 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
246 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
251 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
252 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
255 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
256 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
258 [ C(OP_PREFETCH) ] = {
259 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
260 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
265 static const struct sparc_pmu ultra3_pmu = {
266 .event_map = ultra3_event_map,
267 .cache_map = &ultra3_cache_map,
268 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map),
276 /* Niagara1 is very limited. The upper PIC is hard-locked to count
277 * only instructions, so it is free running which creates all kinds of
278 * problems. Some hardware designs make one wonder if the creator
279 * even looked at how this stuff gets used by software.
281 static const struct perf_event_map niagara1_perfmon_event_map[] = {
282 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
283 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
284 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
285 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
288 static const struct perf_event_map *niagara1_event_map(int event_id)
290 return &niagara1_perfmon_event_map[event_id];
293 static const cache_map_t niagara1_cache_map = {
296 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
297 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
300 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
301 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
304 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
305 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
310 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
311 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
314 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
315 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
317 [ C(OP_PREFETCH) ] = {
318 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
319 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
324 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
325 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
328 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
329 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
332 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
333 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
338 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
339 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
342 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
343 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
345 [ C(OP_PREFETCH) ] = {
346 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
347 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
352 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
353 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
356 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
357 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
359 [ C(OP_PREFETCH) ] = {
360 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
361 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
366 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
367 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
370 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
371 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
373 [ C(OP_PREFETCH) ] = {
374 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
375 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
380 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
381 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
384 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
385 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
387 [ C(OP_PREFETCH) ] = {
388 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
389 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
394 static const struct sparc_pmu niagara1_pmu = {
395 .event_map = niagara1_event_map,
396 .cache_map = &niagara1_cache_map,
397 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map),
405 static const struct perf_event_map niagara2_perfmon_event_map[] = {
406 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
407 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
408 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
409 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
410 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
411 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
414 static const struct perf_event_map *niagara2_event_map(int event_id)
416 return &niagara2_perfmon_event_map[event_id];
419 static const cache_map_t niagara2_cache_map = {
422 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
423 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
426 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
427 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
430 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
431 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
436 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
437 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
440 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
441 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
443 [ C(OP_PREFETCH) ] = {
444 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
445 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
450 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
451 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
454 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
455 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
458 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
459 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
464 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
465 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
468 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
469 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
471 [ C(OP_PREFETCH) ] = {
472 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
473 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
478 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
479 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
482 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
483 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
487 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
492 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
493 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
496 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
497 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
501 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
506 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
507 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
510 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
511 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
515 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
520 static const struct sparc_pmu niagara2_pmu = {
521 .event_map = niagara2_event_map,
522 .cache_map = &niagara2_cache_map,
523 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map),
533 static const struct sparc_pmu *sparc_pmu __read_mostly;
535 static u64 event_encoding(u64 event_id, int idx)
537 if (idx == PIC_UPPER_INDEX)
538 event_id <<= sparc_pmu->upper_shift;
540 event_id <<= sparc_pmu->lower_shift;
544 static u64 mask_for_index(int idx)
546 return event_encoding(sparc_pmu->event_mask, idx);
549 static u64 nop_for_index(int idx)
551 return event_encoding(idx == PIC_UPPER_INDEX ?
552 sparc_pmu->upper_nop :
553 sparc_pmu->lower_nop, idx);
556 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
558 u64 val, mask = mask_for_index(idx);
565 pcr_ops->write(cpuc->pcr);
568 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
570 u64 mask = mask_for_index(idx);
571 u64 nop = nop_for_index(idx);
579 pcr_ops->write(cpuc->pcr);
582 static u32 read_pmc(int idx)
587 if (idx == PIC_UPPER_INDEX)
590 return val & 0xffffffff;
593 static void write_pmc(int idx, u64 val)
595 u64 shift, mask, pic;
598 if (idx == PIC_UPPER_INDEX)
601 mask = ((u64) 0xffffffff) << shift;
610 static u64 sparc_perf_event_update(struct perf_event *event,
611 struct hw_perf_event *hwc, int idx)
614 u64 prev_raw_count, new_raw_count;
618 prev_raw_count = local64_read(&hwc->prev_count);
619 new_raw_count = read_pmc(idx);
621 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
622 new_raw_count) != prev_raw_count)
625 delta = (new_raw_count << shift) - (prev_raw_count << shift);
628 local64_add(delta, &event->count);
629 local64_sub(delta, &hwc->period_left);
631 return new_raw_count;
634 static int sparc_perf_event_set_period(struct perf_event *event,
635 struct hw_perf_event *hwc, int idx)
637 s64 left = local64_read(&hwc->period_left);
638 s64 period = hwc->sample_period;
641 if (unlikely(left <= -period)) {
643 local64_set(&hwc->period_left, left);
644 hwc->last_period = period;
648 if (unlikely(left <= 0)) {
650 local64_set(&hwc->period_left, left);
651 hwc->last_period = period;
654 if (left > MAX_PERIOD)
657 local64_set(&hwc->prev_count, (u64)-left);
659 write_pmc(idx, (u64)(-left) & 0xffffffff);
661 perf_event_update_userpage(event);
666 /* If performance event entries have been added, move existing
667 * events around (if necessary) and then assign new entries to
670 static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
677 /* Read in the counters which are moving. */
678 for (i = 0; i < cpuc->n_events; i++) {
679 struct perf_event *cp = cpuc->event[i];
681 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
682 cpuc->current_idx[i] != cp->hw.idx) {
683 sparc_perf_event_update(cp, &cp->hw,
684 cpuc->current_idx[i]);
685 cpuc->current_idx[i] = PIC_NO_INDEX;
689 /* Assign to counters all unassigned events. */
690 for (i = 0; i < cpuc->n_events; i++) {
691 struct perf_event *cp = cpuc->event[i];
692 struct hw_perf_event *hwc = &cp->hw;
696 if (cpuc->current_idx[i] != PIC_NO_INDEX)
699 sparc_perf_event_set_period(cp, hwc, idx);
700 cpuc->current_idx[i] = idx;
702 enc = perf_event_get_enc(cpuc->events[i]);
703 pcr &= ~mask_for_index(idx);
704 if (hwc->state & PERF_HES_STOPPED)
705 pcr |= nop_for_index(idx);
707 pcr |= event_encoding(enc, idx);
713 static void sparc_pmu_enable(struct pmu *pmu)
715 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
725 if (!cpuc->n_events) {
728 pcr = maybe_change_configuration(cpuc, pcr);
730 /* We require that all of the events have the same
731 * configuration, so just fetch the settings from the
734 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
737 pcr_ops->write(cpuc->pcr);
740 static void sparc_pmu_disable(struct pmu *pmu)
742 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
752 val &= ~(PCR_UTRACE | PCR_STRACE |
753 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
756 pcr_ops->write(cpuc->pcr);
759 static int active_event_index(struct cpu_hw_events *cpuc,
760 struct perf_event *event)
764 for (i = 0; i < cpuc->n_events; i++) {
765 if (cpuc->event[i] == event)
768 BUG_ON(i == cpuc->n_events);
769 return cpuc->current_idx[i];
772 static void sparc_pmu_start(struct perf_event *event, int flags)
774 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
775 int idx = active_event_index(cpuc, event);
777 if (flags & PERF_EF_RELOAD) {
778 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
779 sparc_perf_event_set_period(event, &event->hw, idx);
784 sparc_pmu_enable_event(cpuc, &event->hw, idx);
787 static void sparc_pmu_stop(struct perf_event *event, int flags)
789 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
790 int idx = active_event_index(cpuc, event);
792 if (!(event->hw.state & PERF_HES_STOPPED)) {
793 sparc_pmu_disable_event(cpuc, &event->hw, idx);
794 event->hw.state |= PERF_HES_STOPPED;
797 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
798 sparc_perf_event_update(event, &event->hw, idx);
799 event->hw.state |= PERF_HES_UPTODATE;
803 static void sparc_pmu_del(struct perf_event *event, int _flags)
805 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
809 local_irq_save(flags);
810 perf_pmu_disable(event->pmu);
812 for (i = 0; i < cpuc->n_events; i++) {
813 if (event == cpuc->event[i]) {
814 /* Absorb the final count and turn off the
817 sparc_pmu_stop(event, PERF_EF_UPDATE);
819 /* Shift remaining entries down into
822 while (++i < cpuc->n_events) {
823 cpuc->event[i - 1] = cpuc->event[i];
824 cpuc->events[i - 1] = cpuc->events[i];
825 cpuc->current_idx[i - 1] =
826 cpuc->current_idx[i];
829 perf_event_update_userpage(event);
836 perf_pmu_enable(event->pmu);
837 local_irq_restore(flags);
840 static void sparc_pmu_read(struct perf_event *event)
842 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
843 int idx = active_event_index(cpuc, event);
844 struct hw_perf_event *hwc = &event->hw;
846 sparc_perf_event_update(event, hwc, idx);
849 static atomic_t active_events = ATOMIC_INIT(0);
850 static DEFINE_MUTEX(pmc_grab_mutex);
852 static void perf_stop_nmi_watchdog(void *unused)
854 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
856 stop_nmi_watchdog(NULL);
857 cpuc->pcr = pcr_ops->read();
860 void perf_event_grab_pmc(void)
862 if (atomic_inc_not_zero(&active_events))
865 mutex_lock(&pmc_grab_mutex);
866 if (atomic_read(&active_events) == 0) {
867 if (atomic_read(&nmi_active) > 0) {
868 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
869 BUG_ON(atomic_read(&nmi_active) != 0);
871 atomic_inc(&active_events);
873 mutex_unlock(&pmc_grab_mutex);
876 void perf_event_release_pmc(void)
878 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
879 if (atomic_read(&nmi_active) == 0)
880 on_each_cpu(start_nmi_watchdog, NULL, 1);
881 mutex_unlock(&pmc_grab_mutex);
885 static const struct perf_event_map *sparc_map_cache_event(u64 config)
887 unsigned int cache_type, cache_op, cache_result;
888 const struct perf_event_map *pmap;
890 if (!sparc_pmu->cache_map)
891 return ERR_PTR(-ENOENT);
893 cache_type = (config >> 0) & 0xff;
894 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
895 return ERR_PTR(-EINVAL);
897 cache_op = (config >> 8) & 0xff;
898 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
899 return ERR_PTR(-EINVAL);
901 cache_result = (config >> 16) & 0xff;
902 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
903 return ERR_PTR(-EINVAL);
905 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
907 if (pmap->encoding == CACHE_OP_UNSUPPORTED)
908 return ERR_PTR(-ENOENT);
910 if (pmap->encoding == CACHE_OP_NONSENSE)
911 return ERR_PTR(-EINVAL);
916 static void hw_perf_event_destroy(struct perf_event *event)
918 perf_event_release_pmc();
921 /* Make sure all events can be scheduled into the hardware at
922 * the same time. This is simplified by the fact that we only
923 * need to support 2 simultaneous HW events.
925 * As a side effect, the evts[]->hw.idx values will be assigned
926 * on success. These are pending indexes. When the events are
927 * actually programmed into the chip, these values will propagate
928 * to the per-cpu cpuc->current_idx[] slots, see the code in
929 * maybe_change_configuration() for details.
931 static int sparc_check_constraints(struct perf_event **evts,
932 unsigned long *events, int n_ev)
934 u8 msk0 = 0, msk1 = 0;
937 /* This case is possible when we are invoked from
938 * hw_perf_group_sched_in().
943 if (n_ev > MAX_HWEVENTS)
946 msk0 = perf_event_get_msk(events[0]);
948 if (msk0 & PIC_LOWER)
953 msk1 = perf_event_get_msk(events[1]);
955 /* If both events can go on any counter, OK. */
956 if (msk0 == (PIC_UPPER | PIC_LOWER) &&
957 msk1 == (PIC_UPPER | PIC_LOWER))
960 /* If one event is limited to a specific counter,
961 * and the other can go on both, OK.
963 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
964 msk1 == (PIC_UPPER | PIC_LOWER)) {
965 if (msk0 & PIC_LOWER)
970 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
971 msk0 == (PIC_UPPER | PIC_LOWER)) {
972 if (msk1 & PIC_UPPER)
977 /* If the events are fixed to different counters, OK. */
978 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
979 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
980 if (msk0 & PIC_LOWER)
985 /* Otherwise, there is a conflict. */
989 evts[0]->hw.idx = idx0;
991 evts[1]->hw.idx = idx0 ^ 1;
995 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
997 int eu = 0, ek = 0, eh = 0;
998 struct perf_event *event;
1006 for (i = 0; i < n; i++) {
1009 eu = event->attr.exclude_user;
1010 ek = event->attr.exclude_kernel;
1011 eh = event->attr.exclude_hv;
1013 } else if (event->attr.exclude_user != eu ||
1014 event->attr.exclude_kernel != ek ||
1015 event->attr.exclude_hv != eh) {
1023 static int collect_events(struct perf_event *group, int max_count,
1024 struct perf_event *evts[], unsigned long *events,
1027 struct perf_event *event;
1030 if (!is_software_event(group)) {
1034 events[n] = group->hw.event_base;
1035 current_idx[n++] = PIC_NO_INDEX;
1037 list_for_each_entry(event, &group->sibling_list, group_entry) {
1038 if (!is_software_event(event) &&
1039 event->state != PERF_EVENT_STATE_OFF) {
1043 events[n] = event->hw.event_base;
1044 current_idx[n++] = PIC_NO_INDEX;
1050 static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1052 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1053 int n0, ret = -EAGAIN;
1054 unsigned long flags;
1056 local_irq_save(flags);
1057 perf_pmu_disable(event->pmu);
1059 n0 = cpuc->n_events;
1060 if (n0 >= MAX_HWEVENTS)
1063 cpuc->event[n0] = event;
1064 cpuc->events[n0] = event->hw.event_base;
1065 cpuc->current_idx[n0] = PIC_NO_INDEX;
1067 event->hw.state = PERF_HES_UPTODATE;
1068 if (!(ef_flags & PERF_EF_START))
1069 event->hw.state |= PERF_HES_STOPPED;
1072 * If group events scheduling transaction was started,
1073 * skip the schedulability test here, it will be performed
1074 * at commit time(->commit_txn) as a whole
1076 if (cpuc->group_flag & PERF_EVENT_TXN)
1079 if (check_excludes(cpuc->event, n0, 1))
1081 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1090 perf_pmu_enable(event->pmu);
1091 local_irq_restore(flags);
1095 static int sparc_pmu_event_init(struct perf_event *event)
1097 struct perf_event_attr *attr = &event->attr;
1098 struct perf_event *evts[MAX_HWEVENTS];
1099 struct hw_perf_event *hwc = &event->hw;
1100 unsigned long events[MAX_HWEVENTS];
1101 int current_idx_dmy[MAX_HWEVENTS];
1102 const struct perf_event_map *pmap;
1105 if (atomic_read(&nmi_active) < 0)
1108 switch (attr->type) {
1109 case PERF_TYPE_HARDWARE:
1110 if (attr->config >= sparc_pmu->max_events)
1112 pmap = sparc_pmu->event_map(attr->config);
1115 case PERF_TYPE_HW_CACHE:
1116 pmap = sparc_map_cache_event(attr->config);
1118 return PTR_ERR(pmap);
1131 hwc->event_base = perf_event_encode(pmap);
1134 * User gives us "(encoding << 16) | pic_mask" for
1135 * PERF_TYPE_RAW events.
1137 hwc->event_base = attr->config;
1140 /* We save the enable bits in the config_base. */
1141 hwc->config_base = sparc_pmu->irq_bit;
1142 if (!attr->exclude_user)
1143 hwc->config_base |= PCR_UTRACE;
1144 if (!attr->exclude_kernel)
1145 hwc->config_base |= PCR_STRACE;
1146 if (!attr->exclude_hv)
1147 hwc->config_base |= sparc_pmu->hv_bit;
1150 if (event->group_leader != event) {
1151 n = collect_events(event->group_leader,
1153 evts, events, current_idx_dmy);
1157 events[n] = hwc->event_base;
1160 if (check_excludes(evts, n, 1))
1163 if (sparc_check_constraints(evts, events, n + 1))
1166 hwc->idx = PIC_NO_INDEX;
1168 /* Try to do all error checking before this point, as unwinding
1169 * state after grabbing the PMC is difficult.
1171 perf_event_grab_pmc();
1172 event->destroy = hw_perf_event_destroy;
1174 if (!hwc->sample_period) {
1175 hwc->sample_period = MAX_PERIOD;
1176 hwc->last_period = hwc->sample_period;
1177 local64_set(&hwc->period_left, hwc->sample_period);
1184 * Start group events scheduling transaction
1185 * Set the flag to make pmu::enable() not perform the
1186 * schedulability test, it will be performed at commit time
1188 static void sparc_pmu_start_txn(struct pmu *pmu)
1190 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1192 perf_pmu_disable(pmu);
1193 cpuhw->group_flag |= PERF_EVENT_TXN;
1197 * Stop group events scheduling transaction
1198 * Clear the flag and pmu::enable() will perform the
1199 * schedulability test.
1201 static void sparc_pmu_cancel_txn(struct pmu *pmu)
1203 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1205 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1206 perf_pmu_enable(pmu);
1210 * Commit group events scheduling transaction
1211 * Perform the group schedulability test as a whole
1212 * Return 0 if success
1214 static int sparc_pmu_commit_txn(struct pmu *pmu)
1216 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1222 cpuc = &__get_cpu_var(cpu_hw_events);
1224 if (check_excludes(cpuc->event, 0, n))
1226 if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1229 cpuc->group_flag &= ~PERF_EVENT_TXN;
1230 perf_pmu_enable(pmu);
1234 static struct pmu pmu = {
1235 .pmu_enable = sparc_pmu_enable,
1236 .pmu_disable = sparc_pmu_disable,
1237 .event_init = sparc_pmu_event_init,
1238 .add = sparc_pmu_add,
1239 .del = sparc_pmu_del,
1240 .start = sparc_pmu_start,
1241 .stop = sparc_pmu_stop,
1242 .read = sparc_pmu_read,
1243 .start_txn = sparc_pmu_start_txn,
1244 .cancel_txn = sparc_pmu_cancel_txn,
1245 .commit_txn = sparc_pmu_commit_txn,
1248 void perf_event_print_debug(void)
1250 unsigned long flags;
1257 local_irq_save(flags);
1259 cpu = smp_processor_id();
1261 pcr = pcr_ops->read();
1265 pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
1268 local_irq_restore(flags);
1271 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1272 unsigned long cmd, void *__args)
1274 struct die_args *args = __args;
1275 struct perf_sample_data data;
1276 struct cpu_hw_events *cpuc;
1277 struct pt_regs *regs;
1280 if (!atomic_read(&active_events))
1293 perf_sample_data_init(&data, 0);
1295 cpuc = &__get_cpu_var(cpu_hw_events);
1297 /* If the PMU has the TOE IRQ enable bits, we need to do a
1298 * dummy write to the %pcr to clear the overflow bits and thus
1301 * Do this before we peek at the counters to determine
1302 * overflow so we don't lose any events.
1304 if (sparc_pmu->irq_bit)
1305 pcr_ops->write(cpuc->pcr);
1307 for (i = 0; i < cpuc->n_events; i++) {
1308 struct perf_event *event = cpuc->event[i];
1309 int idx = cpuc->current_idx[i];
1310 struct hw_perf_event *hwc;
1314 val = sparc_perf_event_update(event, hwc, idx);
1315 if (val & (1ULL << 31))
1318 data.period = event->hw.last_period;
1319 if (!sparc_perf_event_set_period(event, hwc, idx))
1322 if (perf_event_overflow(event, &data, regs))
1323 sparc_pmu_stop(event, 0);
1329 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1330 .notifier_call = perf_event_nmi_handler,
1333 static bool __init supported_pmu(void)
1335 if (!strcmp(sparc_pmu_type, "ultra3") ||
1336 !strcmp(sparc_pmu_type, "ultra3+") ||
1337 !strcmp(sparc_pmu_type, "ultra3i") ||
1338 !strcmp(sparc_pmu_type, "ultra4+")) {
1339 sparc_pmu = &ultra3_pmu;
1342 if (!strcmp(sparc_pmu_type, "niagara")) {
1343 sparc_pmu = &niagara1_pmu;
1346 if (!strcmp(sparc_pmu_type, "niagara2") ||
1347 !strcmp(sparc_pmu_type, "niagara3")) {
1348 sparc_pmu = &niagara2_pmu;
1354 int __init init_hw_perf_events(void)
1356 pr_info("Performance events: ");
1358 if (!supported_pmu()) {
1359 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1363 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1365 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1366 register_die_notifier(&perf_event_nmi_notifier);
1370 early_initcall(init_hw_perf_events);
1372 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1373 struct pt_regs *regs)
1375 unsigned long ksp, fp;
1376 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1380 stack_trace_flush();
1382 perf_callchain_store(entry, regs->tpc);
1384 ksp = regs->u_regs[UREG_I6];
1385 fp = ksp + STACK_BIAS;
1387 struct sparc_stackf *sf;
1388 struct pt_regs *regs;
1391 if (!kstack_valid(current_thread_info(), fp))
1394 sf = (struct sparc_stackf *) fp;
1395 regs = (struct pt_regs *) (sf + 1);
1397 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1398 if (user_mode(regs))
1401 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1403 pc = sf->callers_pc;
1404 fp = (unsigned long)sf->fp + STACK_BIAS;
1406 perf_callchain_store(entry, pc);
1407 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1408 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1409 int index = current->curr_ret_stack;
1410 if (current->ret_stack && index >= graph) {
1411 pc = current->ret_stack[index - graph].ret;
1412 perf_callchain_store(entry, pc);
1417 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1420 static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1421 struct pt_regs *regs)
1425 perf_callchain_store(entry, regs->tpc);
1427 ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1429 struct sparc_stackf *usf, sf;
1432 usf = (struct sparc_stackf *) ufp;
1433 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1437 ufp = (unsigned long)sf.fp + STACK_BIAS;
1438 perf_callchain_store(entry, pc);
1439 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1442 static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1443 struct pt_regs *regs)
1447 perf_callchain_store(entry, regs->tpc);
1449 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1451 struct sparc_stackf32 *usf, sf;
1454 usf = (struct sparc_stackf32 *) ufp;
1455 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1459 ufp = (unsigned long)sf.fp;
1460 perf_callchain_store(entry, pc);
1461 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1465 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1468 if (test_thread_flag(TIF_32BIT))
1469 perf_callchain_user_32(entry, regs);
1471 perf_callchain_user_64(entry, regs);