2 * Procedures for creating, accessing and interpreting the device tree.
4 * Paul Mackerras August 1996.
5 * Copyright (C) 1996-2005 Paul Mackerras.
7 * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
8 * {engebret|bergner}@us.ibm.com
10 * Adapted for sparc64 by David S. Miller davem@davemloft.net
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
22 #include <linux/module.h>
23 #include <linux/lmb.h>
24 #include <linux/of_device.h>
27 #include <asm/oplib.h>
35 static unsigned int prom_early_allocated __initdata;
37 static void * __init prom_early_alloc(unsigned long size)
39 unsigned long paddr = lmb_alloc(size, SMP_CACHE_BYTES);
43 prom_printf("prom_early_alloc(%lu) failed\n");
49 prom_early_allocated += size;
55 /* PSYCHO interrupt mapping support. */
56 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
57 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
58 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
60 unsigned int bus = (ino & 0x10) >> 4;
61 unsigned int slot = (ino & 0x0c) >> 2;
64 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
66 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
69 #define PSYCHO_OBIO_IMAP_BASE 0x1000UL
71 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
72 #define psycho_onboard_imap_offset(__ino) \
73 (PSYCHO_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
75 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
76 #define PSYCHO_ICLR_SCSI 0x1800UL
78 #define psycho_iclr_offset(ino) \
79 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
80 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
82 static unsigned int psycho_irq_build(struct device_node *dp,
86 unsigned long controller_regs = (unsigned long) _data;
87 unsigned long imap, iclr;
88 unsigned long imap_off, iclr_off;
92 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
94 imap_off = psycho_pcislot_imap_offset(ino);
97 imap_off = psycho_onboard_imap_offset(ino);
100 /* Now build the IRQ bucket. */
101 imap = controller_regs + imap_off;
103 iclr_off = psycho_iclr_offset(ino);
104 iclr = controller_regs + iclr_off;
106 if ((ino & 0x20) == 0)
107 inofixup = ino & 0x03;
109 return build_irq(inofixup, iclr, imap);
112 static void __init psycho_irq_trans_init(struct device_node *dp)
114 const struct linux_prom64_registers *regs;
116 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
117 dp->irq_trans->irq_build = psycho_irq_build;
119 regs = of_get_property(dp, "reg", NULL);
120 dp->irq_trans->data = (void *) regs[2].phys_addr;
123 #define sabre_read(__reg) \
125 __asm__ __volatile__("ldxa [%1] %2, %0" \
127 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
132 struct sabre_irq_data {
133 unsigned long controller_regs;
134 unsigned int pci_first_busno;
136 #define SABRE_CONFIGSPACE 0x001000000UL
137 #define SABRE_WRSYNC 0x1c20UL
139 #define SABRE_CONFIG_BASE(CONFIG_SPACE) \
140 (CONFIG_SPACE | (1UL << 24))
141 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
142 (((unsigned long)(BUS) << 16) | \
143 ((unsigned long)(DEVFN) << 8) | \
144 ((unsigned long)(REG)))
146 /* When a device lives behind a bridge deeper in the PCI bus topology
147 * than APB, a special sequence must run to make sure all pending DMA
148 * transfers at the time of IRQ delivery are visible in the coherency
149 * domain by the cpu. This sequence is to perform a read on the far
150 * side of the non-APB bridge, then perform a read of Sabre's DMA
151 * write-sync register.
153 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
155 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
156 struct sabre_irq_data *irq_data = _arg2;
157 unsigned long controller_regs = irq_data->controller_regs;
158 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
159 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
160 unsigned int bus, devfn;
163 config_space = SABRE_CONFIG_BASE(config_space);
165 bus = (phys_hi >> 16) & 0xff;
166 devfn = (phys_hi >> 8) & 0xff;
168 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
170 __asm__ __volatile__("membar #Sync\n\t"
171 "lduha [%1] %2, %0\n\t"
174 : "r" ((u16 *) config_space),
175 "i" (ASI_PHYS_BYPASS_EC_E_L)
178 sabre_read(sync_reg);
181 #define SABRE_IMAP_A_SLOT0 0x0c00UL
182 #define SABRE_IMAP_B_SLOT0 0x0c20UL
183 #define SABRE_ICLR_A_SLOT0 0x1400UL
184 #define SABRE_ICLR_B_SLOT0 0x1480UL
185 #define SABRE_ICLR_SCSI 0x1800UL
186 #define SABRE_ICLR_ETH 0x1808UL
187 #define SABRE_ICLR_BPP 0x1810UL
188 #define SABRE_ICLR_AU_REC 0x1818UL
189 #define SABRE_ICLR_AU_PLAY 0x1820UL
190 #define SABRE_ICLR_PFAIL 0x1828UL
191 #define SABRE_ICLR_KMS 0x1830UL
192 #define SABRE_ICLR_FLPY 0x1838UL
193 #define SABRE_ICLR_SHW 0x1840UL
194 #define SABRE_ICLR_KBD 0x1848UL
195 #define SABRE_ICLR_MS 0x1850UL
196 #define SABRE_ICLR_SER 0x1858UL
197 #define SABRE_ICLR_UE 0x1870UL
198 #define SABRE_ICLR_CE 0x1878UL
199 #define SABRE_ICLR_PCIERR 0x1880UL
201 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
203 unsigned int bus = (ino & 0x10) >> 4;
204 unsigned int slot = (ino & 0x0c) >> 2;
207 return SABRE_IMAP_A_SLOT0 + (slot * 8);
209 return SABRE_IMAP_B_SLOT0 + (slot * 8);
212 #define SABRE_OBIO_IMAP_BASE 0x1000UL
213 #define SABRE_ONBOARD_IRQ_BASE 0x20
214 #define sabre_onboard_imap_offset(__ino) \
215 (SABRE_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
217 #define sabre_iclr_offset(ino) \
218 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
219 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
221 static int sabre_device_needs_wsync(struct device_node *dp)
223 struct device_node *parent = dp->parent;
224 const char *parent_model, *parent_compat;
226 /* This traversal up towards the root is meant to
229 * 1) non-PCI bus sitting under PCI, such as 'ebus'
230 * 2) the PCI controller interrupts themselves, which
231 * will use the sabre_irq_build but do not need
232 * the DMA synchronization handling
235 if (!strcmp(parent->type, "pci"))
237 parent = parent->parent;
243 parent_model = of_get_property(parent,
246 (!strcmp(parent_model, "SUNW,sabre") ||
247 !strcmp(parent_model, "SUNW,simba")))
250 parent_compat = of_get_property(parent,
253 (!strcmp(parent_compat, "pci108e,a000") ||
254 !strcmp(parent_compat, "pci108e,a001")))
260 static unsigned int sabre_irq_build(struct device_node *dp,
264 struct sabre_irq_data *irq_data = _data;
265 unsigned long controller_regs = irq_data->controller_regs;
266 const struct linux_prom_pci_registers *regs;
267 unsigned long imap, iclr;
268 unsigned long imap_off, iclr_off;
273 if (ino < SABRE_ONBOARD_IRQ_BASE) {
275 imap_off = sabre_pcislot_imap_offset(ino);
278 imap_off = sabre_onboard_imap_offset(ino);
281 /* Now build the IRQ bucket. */
282 imap = controller_regs + imap_off;
284 iclr_off = sabre_iclr_offset(ino);
285 iclr = controller_regs + iclr_off;
287 if ((ino & 0x20) == 0)
288 inofixup = ino & 0x03;
290 virt_irq = build_irq(inofixup, iclr, imap);
292 /* If the parent device is a PCI<->PCI bridge other than
293 * APB, we have to install a pre-handler to ensure that
294 * all pending DMA is drained before the interrupt handler
297 regs = of_get_property(dp, "reg", NULL);
298 if (regs && sabre_device_needs_wsync(dp)) {
299 irq_install_pre_handler(virt_irq,
301 (void *) (long) regs->phys_hi,
308 static void __init sabre_irq_trans_init(struct device_node *dp)
310 const struct linux_prom64_registers *regs;
311 struct sabre_irq_data *irq_data;
314 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
315 dp->irq_trans->irq_build = sabre_irq_build;
317 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
319 regs = of_get_property(dp, "reg", NULL);
320 irq_data->controller_regs = regs[0].phys_addr;
322 busrange = of_get_property(dp, "bus-range", NULL);
323 irq_data->pci_first_busno = busrange[0];
325 dp->irq_trans->data = irq_data;
328 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
329 * imap/iclr registers are per-PBM.
331 #define SCHIZO_IMAP_BASE 0x1000UL
332 #define SCHIZO_ICLR_BASE 0x1400UL
334 static unsigned long schizo_imap_offset(unsigned long ino)
336 return SCHIZO_IMAP_BASE + (ino * 8UL);
339 static unsigned long schizo_iclr_offset(unsigned long ino)
341 return SCHIZO_ICLR_BASE + (ino * 8UL);
344 static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
348 return pbm_regs + schizo_iclr_offset(ino);
351 static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
354 return pbm_regs + schizo_imap_offset(ino);
357 #define schizo_read(__reg) \
359 __asm__ __volatile__("ldxa [%1] %2, %0" \
361 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
365 #define schizo_write(__reg, __val) \
366 __asm__ __volatile__("stxa %0, [%1] %2" \
368 : "r" (__val), "r" (__reg), \
369 "i" (ASI_PHYS_BYPASS_EC_E) \
372 static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
374 unsigned long sync_reg = (unsigned long) _arg2;
375 u64 mask = 1UL << (ino & IMAP_INO);
379 schizo_write(sync_reg, mask);
384 val = schizo_read(sync_reg);
389 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
394 static unsigned char cacheline[64]
395 __attribute__ ((aligned (64)));
397 __asm__ __volatile__("rd %%fprs, %0\n\t"
399 "wr %1, 0x0, %%fprs\n\t"
400 "stda %%f0, [%5] %6\n\t"
401 "wr %0, 0x0, %%fprs\n\t"
403 : "=&r" (mask), "=&r" (val)
404 : "0" (mask), "1" (val),
405 "i" (FPRS_FEF), "r" (&cacheline[0]),
406 "i" (ASI_BLK_COMMIT_P));
410 struct schizo_irq_data {
411 unsigned long pbm_regs;
412 unsigned long sync_reg;
417 static unsigned int schizo_irq_build(struct device_node *dp,
421 struct schizo_irq_data *irq_data = _data;
422 unsigned long pbm_regs = irq_data->pbm_regs;
423 unsigned long imap, iclr;
430 /* Now build the IRQ bucket. */
431 imap = schizo_ino_to_imap(pbm_regs, ino);
432 iclr = schizo_ino_to_iclr(pbm_regs, ino);
434 /* On Schizo, no inofixup occurs. This is because each
435 * INO has it's own IMAP register. On Psycho and Sabre
436 * there is only one IMAP register for each PCI slot even
437 * though four different INOs can be generated by each
440 * But, for JBUS variants (essentially, Tomatillo), we have
441 * to fixup the lowest bit of the interrupt group number.
445 is_tomatillo = (irq_data->sync_reg != 0UL);
448 if (irq_data->portid & 1)
449 ign_fixup = (1 << 6);
452 virt_irq = build_irq(ign_fixup, iclr, imap);
455 irq_install_pre_handler(virt_irq,
456 tomatillo_wsync_handler,
457 ((irq_data->chip_version <= 4) ?
458 (void *) 1 : (void *) 0),
459 (void *) irq_data->sync_reg);
465 static void __init __schizo_irq_trans_init(struct device_node *dp,
468 const struct linux_prom64_registers *regs;
469 struct schizo_irq_data *irq_data;
471 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
472 dp->irq_trans->irq_build = schizo_irq_build;
474 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
476 regs = of_get_property(dp, "reg", NULL);
477 dp->irq_trans->data = irq_data;
479 irq_data->pbm_regs = regs[0].phys_addr;
481 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
483 irq_data->sync_reg = 0UL;
484 irq_data->portid = of_getintprop_default(dp, "portid", 0);
485 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
488 static void __init schizo_irq_trans_init(struct device_node *dp)
490 __schizo_irq_trans_init(dp, 0);
493 static void __init tomatillo_irq_trans_init(struct device_node *dp)
495 __schizo_irq_trans_init(dp, 1);
498 static unsigned int pci_sun4v_irq_build(struct device_node *dp,
502 u32 devhandle = (u32) (unsigned long) _data;
504 return sun4v_build_irq(devhandle, devino);
507 static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
509 const struct linux_prom64_registers *regs;
511 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
512 dp->irq_trans->irq_build = pci_sun4v_irq_build;
514 regs = of_get_property(dp, "reg", NULL);
515 dp->irq_trans->data = (void *) (unsigned long)
516 ((regs->phys_addr >> 32UL) & 0x0fffffff);
519 struct fire_irq_data {
520 unsigned long pbm_regs;
524 #define FIRE_IMAP_BASE 0x001000
525 #define FIRE_ICLR_BASE 0x001400
527 static unsigned long fire_imap_offset(unsigned long ino)
529 return FIRE_IMAP_BASE + (ino * 8UL);
532 static unsigned long fire_iclr_offset(unsigned long ino)
534 return FIRE_ICLR_BASE + (ino * 8UL);
537 static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
540 return pbm_regs + fire_iclr_offset(ino);
543 static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
546 return pbm_regs + fire_imap_offset(ino);
549 static unsigned int fire_irq_build(struct device_node *dp,
553 struct fire_irq_data *irq_data = _data;
554 unsigned long pbm_regs = irq_data->pbm_regs;
555 unsigned long imap, iclr;
556 unsigned long int_ctrlr;
560 /* Now build the IRQ bucket. */
561 imap = fire_ino_to_imap(pbm_regs, ino);
562 iclr = fire_ino_to_iclr(pbm_regs, ino);
564 /* Set the interrupt controller number. */
566 upa_writeq(int_ctrlr, imap);
568 /* The interrupt map registers do not have an INO field
569 * like other chips do. They return zero in the INO
570 * field, and the interrupt controller number is controlled
571 * in bits 6 to 9. So in order for build_irq() to get
572 * the INO right we pass it in as part of the fixup
573 * which will get added to the map register zero value
574 * read by build_irq().
576 ino |= (irq_data->portid << 6);
578 return build_irq(ino, iclr, imap);
581 static void __init fire_irq_trans_init(struct device_node *dp)
583 const struct linux_prom64_registers *regs;
584 struct fire_irq_data *irq_data;
586 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
587 dp->irq_trans->irq_build = fire_irq_build;
589 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
591 regs = of_get_property(dp, "reg", NULL);
592 dp->irq_trans->data = irq_data;
594 irq_data->pbm_regs = regs[0].phys_addr;
595 irq_data->portid = of_getintprop_default(dp, "portid", 0);
597 #endif /* CONFIG_PCI */
600 /* INO number to IMAP register offset for SYSIO external IRQ's.
601 * This should conform to both Sunfire/Wildfire server and Fusion
604 #define SYSIO_IMAP_SLOT0 0x2c00UL
605 #define SYSIO_IMAP_SLOT1 0x2c08UL
606 #define SYSIO_IMAP_SLOT2 0x2c10UL
607 #define SYSIO_IMAP_SLOT3 0x2c18UL
608 #define SYSIO_IMAP_SCSI 0x3000UL
609 #define SYSIO_IMAP_ETH 0x3008UL
610 #define SYSIO_IMAP_BPP 0x3010UL
611 #define SYSIO_IMAP_AUDIO 0x3018UL
612 #define SYSIO_IMAP_PFAIL 0x3020UL
613 #define SYSIO_IMAP_KMS 0x3028UL
614 #define SYSIO_IMAP_FLPY 0x3030UL
615 #define SYSIO_IMAP_SHW 0x3038UL
616 #define SYSIO_IMAP_KBD 0x3040UL
617 #define SYSIO_IMAP_MS 0x3048UL
618 #define SYSIO_IMAP_SER 0x3050UL
619 #define SYSIO_IMAP_TIM0 0x3060UL
620 #define SYSIO_IMAP_TIM1 0x3068UL
621 #define SYSIO_IMAP_UE 0x3070UL
622 #define SYSIO_IMAP_CE 0x3078UL
623 #define SYSIO_IMAP_SBERR 0x3080UL
624 #define SYSIO_IMAP_PMGMT 0x3088UL
625 #define SYSIO_IMAP_GFX 0x3090UL
626 #define SYSIO_IMAP_EUPA 0x3098UL
628 #define bogon ((unsigned long) -1)
629 static unsigned long sysio_irq_offsets[] = {
630 /* SBUS Slot 0 --> 3, level 1 --> 7 */
631 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
632 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
633 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
634 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
635 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
636 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
637 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
638 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
640 /* Onboard devices (not relevant/used on SunFire). */
671 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
673 /* Convert Interrupt Mapping register pointer to associated
674 * Interrupt Clear register pointer, SYSIO specific version.
676 #define SYSIO_ICLR_UNUSED0 0x3400UL
677 #define SYSIO_ICLR_SLOT0 0x3408UL
678 #define SYSIO_ICLR_SLOT1 0x3448UL
679 #define SYSIO_ICLR_SLOT2 0x3488UL
680 #define SYSIO_ICLR_SLOT3 0x34c8UL
681 static unsigned long sysio_imap_to_iclr(unsigned long imap)
683 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
687 static unsigned int sbus_of_build_irq(struct device_node *dp,
691 unsigned long reg_base = (unsigned long) _data;
692 const struct linux_prom_registers *regs;
693 unsigned long imap, iclr;
699 regs = of_get_property(dp, "reg", NULL);
701 sbus_slot = regs->which_io;
704 ino += (sbus_slot * 8);
706 imap = sysio_irq_offsets[ino];
707 if (imap == ((unsigned long)-1)) {
708 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
714 /* SYSIO inconsistency. For external SLOTS, we have to select
715 * the right ICLR register based upon the lower SBUS irq level
719 iclr = sysio_imap_to_iclr(imap);
721 sbus_level = ino & 0x7;
725 iclr = reg_base + SYSIO_ICLR_SLOT0;
728 iclr = reg_base + SYSIO_ICLR_SLOT1;
731 iclr = reg_base + SYSIO_ICLR_SLOT2;
735 iclr = reg_base + SYSIO_ICLR_SLOT3;
739 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
741 return build_irq(sbus_level, iclr, imap);
744 static void __init sbus_irq_trans_init(struct device_node *dp)
746 const struct linux_prom64_registers *regs;
748 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
749 dp->irq_trans->irq_build = sbus_of_build_irq;
751 regs = of_get_property(dp, "reg", NULL);
752 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
754 #endif /* CONFIG_SBUS */
757 static unsigned int central_build_irq(struct device_node *dp,
761 struct device_node *central_dp = _data;
762 struct of_device *central_op = of_find_device_by_node(central_dp);
763 struct resource *res;
764 unsigned long imap, iclr;
767 if (!strcmp(dp->name, "eeprom")) {
768 res = ¢ral_op->resource[5];
769 } else if (!strcmp(dp->name, "zs")) {
770 res = ¢ral_op->resource[4];
771 } else if (!strcmp(dp->name, "clock-board")) {
772 res = ¢ral_op->resource[3];
777 imap = res->start + 0x00UL;
778 iclr = res->start + 0x10UL;
780 /* Set the INO state to idle, and disable. */
784 tmp = upa_readl(imap);
786 upa_writel(tmp, imap);
788 return build_irq(0, iclr, imap);
791 static void __init central_irq_trans_init(struct device_node *dp)
793 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
794 dp->irq_trans->irq_build = central_build_irq;
796 dp->irq_trans->data = dp;
801 void (*init)(struct device_node *);
805 static struct irq_trans __initdata pci_irq_trans_table[] = {
806 { "SUNW,sabre", sabre_irq_trans_init },
807 { "pci108e,a000", sabre_irq_trans_init },
808 { "pci108e,a001", sabre_irq_trans_init },
809 { "SUNW,psycho", psycho_irq_trans_init },
810 { "pci108e,8000", psycho_irq_trans_init },
811 { "SUNW,schizo", schizo_irq_trans_init },
812 { "pci108e,8001", schizo_irq_trans_init },
813 { "SUNW,schizo+", schizo_irq_trans_init },
814 { "pci108e,8002", schizo_irq_trans_init },
815 { "SUNW,tomatillo", tomatillo_irq_trans_init },
816 { "pci108e,a801", tomatillo_irq_trans_init },
817 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
818 { "pciex108e,80f0", fire_irq_trans_init },
822 static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
826 u32 devhandle = (u32) (unsigned long) _data;
828 return sun4v_build_irq(devhandle, devino);
831 static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
833 const struct linux_prom64_registers *regs;
835 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
836 dp->irq_trans->irq_build = sun4v_vdev_irq_build;
838 regs = of_get_property(dp, "reg", NULL);
839 dp->irq_trans->data = (void *) (unsigned long)
840 ((regs->phys_addr >> 32UL) & 0x0fffffff);
843 static void __init irq_trans_init(struct device_node *dp)
851 model = of_get_property(dp, "model", NULL);
853 model = of_get_property(dp, "compatible", NULL);
855 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
856 struct irq_trans *t = &pci_irq_trans_table[i];
858 if (!strcmp(model, t->name)) {
866 if (!strcmp(dp->name, "sbus") ||
867 !strcmp(dp->name, "sbi")) {
868 sbus_irq_trans_init(dp);
872 if (!strcmp(dp->name, "fhc") &&
873 !strcmp(dp->parent->name, "central")) {
874 central_irq_trans_init(dp);
877 if (!strcmp(dp->name, "virtual-devices") ||
878 !strcmp(dp->name, "niu")) {
879 sun4v_vdev_irq_trans_init(dp);
884 static int is_root_node(const struct device_node *dp)
889 return (dp->parent == NULL);
892 /* The following routines deal with the black magic of fully naming a
895 * Certain well known named nodes are just the simple name string.
897 * Actual devices have an address specifier appended to the base name
898 * string, like this "foo@addr". The "addr" can be in any number of
899 * formats, and the platform plus the type of the node determine the
900 * format and how it is constructed.
902 * For children of the ROOT node, the naming convention is fixed and
903 * determined by whether this is a sun4u or sun4v system.
905 * For children of other nodes, it is bus type specific. So
906 * we walk up the tree until we discover a "device_type" property
907 * we recognize and we go from there.
909 * As an example, the boot device on my workstation has a full path:
911 * /pci@1e,600000/ide@d/disk@0,0:c
913 static void __init sun4v_path_component(struct device_node *dp, char *tmp_buf)
915 struct linux_prom64_registers *regs;
916 struct property *rprop;
917 u32 high_bits, low_bits, type;
919 rprop = of_find_property(dp, "reg", NULL);
924 if (!is_root_node(dp->parent)) {
925 sprintf(tmp_buf, "%s@%x,%x",
927 (unsigned int) (regs->phys_addr >> 32UL),
928 (unsigned int) (regs->phys_addr & 0xffffffffUL));
932 type = regs->phys_addr >> 60UL;
933 high_bits = (regs->phys_addr >> 32UL) & 0x0fffffffUL;
934 low_bits = (regs->phys_addr & 0xffffffffUL);
936 if (type == 0 || type == 8) {
937 const char *prefix = (type == 0) ? "m" : "i";
940 sprintf(tmp_buf, "%s@%s%x,%x",
942 high_bits, low_bits);
944 sprintf(tmp_buf, "%s@%s%x",
948 } else if (type == 12) {
949 sprintf(tmp_buf, "%s@%x",
950 dp->name, high_bits);
954 static void __init sun4u_path_component(struct device_node *dp, char *tmp_buf)
956 struct linux_prom64_registers *regs;
957 struct property *prop;
959 prop = of_find_property(dp, "reg", NULL);
964 if (!is_root_node(dp->parent)) {
965 sprintf(tmp_buf, "%s@%x,%x",
967 (unsigned int) (regs->phys_addr >> 32UL),
968 (unsigned int) (regs->phys_addr & 0xffffffffUL));
972 prop = of_find_property(dp, "upa-portid", NULL);
974 prop = of_find_property(dp, "portid", NULL);
976 unsigned long mask = 0xffffffffUL;
978 if (tlb_type >= cheetah)
981 sprintf(tmp_buf, "%s@%x,%x",
984 (unsigned int) (regs->phys_addr & mask));
988 /* "name@slot,offset" */
989 static void __init sbus_path_component(struct device_node *dp, char *tmp_buf)
991 struct linux_prom_registers *regs;
992 struct property *prop;
994 prop = of_find_property(dp, "reg", NULL);
999 sprintf(tmp_buf, "%s@%x,%x",
1005 /* "name@devnum[,func]" */
1006 static void __init pci_path_component(struct device_node *dp, char *tmp_buf)
1008 struct linux_prom_pci_registers *regs;
1009 struct property *prop;
1012 prop = of_find_property(dp, "reg", NULL);
1017 devfn = (regs->phys_hi >> 8) & 0xff;
1019 sprintf(tmp_buf, "%s@%x,%x",
1024 sprintf(tmp_buf, "%s@%x",
1030 /* "name@UPA_PORTID,offset" */
1031 static void __init upa_path_component(struct device_node *dp, char *tmp_buf)
1033 struct linux_prom64_registers *regs;
1034 struct property *prop;
1036 prop = of_find_property(dp, "reg", NULL);
1042 prop = of_find_property(dp, "upa-portid", NULL);
1046 sprintf(tmp_buf, "%s@%x,%x",
1048 *(u32 *) prop->value,
1049 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1053 static void __init vdev_path_component(struct device_node *dp, char *tmp_buf)
1055 struct property *prop;
1058 prop = of_find_property(dp, "reg", NULL);
1064 sprintf(tmp_buf, "%s@%x", dp->name, *regs);
1067 /* "name@addrhi,addrlo" */
1068 static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
1070 struct linux_prom64_registers *regs;
1071 struct property *prop;
1073 prop = of_find_property(dp, "reg", NULL);
1079 sprintf(tmp_buf, "%s@%x,%x",
1081 (unsigned int) (regs->phys_addr >> 32UL),
1082 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1085 /* "name@bus,addr" */
1086 static void __init i2c_path_component(struct device_node *dp, char *tmp_buf)
1088 struct property *prop;
1091 prop = of_find_property(dp, "reg", NULL);
1097 /* This actually isn't right... should look at the #address-cells
1098 * property of the i2c bus node etc. etc.
1100 sprintf(tmp_buf, "%s@%x,%x",
1101 dp->name, regs[0], regs[1]);
1104 /* "name@reg0[,reg1]" */
1105 static void __init usb_path_component(struct device_node *dp, char *tmp_buf)
1107 struct property *prop;
1110 prop = of_find_property(dp, "reg", NULL);
1116 if (prop->length == sizeof(u32) || regs[1] == 1) {
1117 sprintf(tmp_buf, "%s@%x",
1120 sprintf(tmp_buf, "%s@%x,%x",
1121 dp->name, regs[0], regs[1]);
1125 /* "name@reg0reg1[,reg2reg3]" */
1126 static void __init ieee1394_path_component(struct device_node *dp, char *tmp_buf)
1128 struct property *prop;
1131 prop = of_find_property(dp, "reg", NULL);
1137 if (regs[2] || regs[3]) {
1138 sprintf(tmp_buf, "%s@%08x%08x,%04x%08x",
1139 dp->name, regs[0], regs[1], regs[2], regs[3]);
1141 sprintf(tmp_buf, "%s@%08x%08x",
1142 dp->name, regs[0], regs[1]);
1146 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
1148 struct device_node *parent = dp->parent;
1150 if (parent != NULL) {
1151 if (!strcmp(parent->type, "pci") ||
1152 !strcmp(parent->type, "pciex")) {
1153 pci_path_component(dp, tmp_buf);
1156 if (!strcmp(parent->type, "sbus")) {
1157 sbus_path_component(dp, tmp_buf);
1160 if (!strcmp(parent->type, "upa")) {
1161 upa_path_component(dp, tmp_buf);
1164 if (!strcmp(parent->type, "ebus")) {
1165 ebus_path_component(dp, tmp_buf);
1168 if (!strcmp(parent->name, "usb") ||
1169 !strcmp(parent->name, "hub")) {
1170 usb_path_component(dp, tmp_buf);
1173 if (!strcmp(parent->type, "i2c")) {
1174 i2c_path_component(dp, tmp_buf);
1177 if (!strcmp(parent->type, "firewire")) {
1178 ieee1394_path_component(dp, tmp_buf);
1181 if (!strcmp(parent->type, "virtual-devices")) {
1182 vdev_path_component(dp, tmp_buf);
1185 /* "isa" is handled with platform naming */
1188 /* Use platform naming convention. */
1189 if (tlb_type == hypervisor) {
1190 sun4v_path_component(dp, tmp_buf);
1193 sun4u_path_component(dp, tmp_buf);
1197 static char * __init build_path_component(struct device_node *dp)
1199 char tmp_buf[64], *n;
1202 __build_path_component(dp, tmp_buf);
1203 if (tmp_buf[0] == '\0')
1204 strcpy(tmp_buf, dp->name);
1206 n = prom_early_alloc(strlen(tmp_buf) + 1);
1212 static char * __init build_full_name(struct device_node *dp)
1214 int len, ourlen, plen;
1217 plen = strlen(dp->parent->full_name);
1218 ourlen = strlen(dp->path_component_name);
1219 len = ourlen + plen + 2;
1221 n = prom_early_alloc(len);
1222 strcpy(n, dp->parent->full_name);
1223 if (!is_root_node(dp->parent)) {
1224 strcpy(n + plen, "/");
1227 strcpy(n + plen, dp->path_component_name);
1232 static unsigned int unique_id;
1234 static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len)
1236 static struct property *tmp = NULL;
1241 memset(p, 0, sizeof(*p) + 32);
1244 p = prom_early_alloc(sizeof(struct property) + 32);
1245 p->unique_id = unique_id++;
1248 p->name = (char *) (p + 1);
1250 strcpy(p->name, special_name);
1251 p->length = special_len;
1252 p->value = prom_early_alloc(special_len);
1253 memcpy(p->value, special_val, special_len);
1256 prom_firstprop(node, p->name);
1258 prom_nextprop(node, prev, p->name);
1260 if (strlen(p->name) == 0) {
1264 p->length = prom_getproplen(node, p->name);
1265 if (p->length <= 0) {
1268 p->value = prom_early_alloc(p->length + 1);
1269 prom_getproperty(node, p->name, p->value, p->length);
1270 ((unsigned char *)p->value)[p->length] = '\0';
1276 static struct property * __init build_prop_list(phandle node)
1278 struct property *head, *tail;
1280 head = tail = build_one_prop(node, NULL,
1281 ".node", &node, sizeof(node));
1283 tail->next = build_one_prop(node, NULL, NULL, NULL, 0);
1286 tail->next = build_one_prop(node, tail->name,
1294 static char * __init get_one_property(phandle node, const char *name)
1296 char *buf = "<NULL>";
1299 len = prom_getproplen(node, name);
1301 buf = prom_early_alloc(len);
1302 prom_getproperty(node, name, buf, len);
1308 static struct device_node * __init create_node(phandle node, struct device_node *parent)
1310 struct device_node *dp;
1315 dp = prom_early_alloc(sizeof(*dp));
1316 dp->unique_id = unique_id++;
1317 dp->parent = parent;
1319 kref_init(&dp->kref);
1321 dp->name = get_one_property(node, "name");
1322 dp->type = get_one_property(node, "device_type");
1325 dp->properties = build_prop_list(node);
1332 static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp)
1334 struct device_node *ret = NULL, *prev_sibling = NULL;
1335 struct device_node *dp;
1338 dp = create_node(node, parent);
1343 prev_sibling->sibling = dp;
1350 *nextp = &dp->allnext;
1352 dp->path_component_name = build_path_component(dp);
1353 dp->full_name = build_full_name(dp);
1355 dp->child = build_tree(dp, prom_getchild(node), nextp);
1357 node = prom_getsibling(node);
1363 static const char *get_mid_prop(void)
1365 return (tlb_type == spitfire ? "upa-portid" : "portid");
1368 struct device_node *of_find_node_by_cpuid(int cpuid)
1370 struct device_node *dp;
1371 const char *mid_prop = get_mid_prop();
1373 for_each_node_by_type(dp, "cpu") {
1374 int id = of_getintprop_default(dp, mid_prop, -1);
1375 const char *this_mid_prop = mid_prop;
1378 this_mid_prop = "cpuid";
1379 id = of_getintprop_default(dp, this_mid_prop, -1);
1383 prom_printf("OF: Serious problem, cpu lacks "
1384 "%s property", this_mid_prop);
1393 static void __init of_fill_in_cpu_data(void)
1395 struct device_node *dp;
1396 const char *mid_prop = get_mid_prop();
1399 for_each_node_by_type(dp, "cpu") {
1400 int cpuid = of_getintprop_default(dp, mid_prop, -1);
1401 const char *this_mid_prop = mid_prop;
1402 struct device_node *portid_parent;
1405 portid_parent = NULL;
1407 this_mid_prop = "cpuid";
1408 cpuid = of_getintprop_default(dp, this_mid_prop, -1);
1414 portid_parent = portid_parent->parent;
1417 portid = of_getintprop_default(portid_parent,
1426 prom_printf("OF: Serious problem, cpu lacks "
1427 "%s property", this_mid_prop);
1434 if (cpuid >= NR_CPUS) {
1435 printk(KERN_WARNING "Ignoring CPU %d which is "
1436 ">= NR_CPUS (%d)\n",
1441 /* On uniprocessor we only want the values for the
1442 * real physical cpu the kernel booted onto, however
1443 * cpu_data() only has one entry at index 0.
1445 if (cpuid != real_hard_smp_processor_id())
1450 cpu_data(cpuid).clock_tick =
1451 of_getintprop_default(dp, "clock-frequency", 0);
1453 if (portid_parent) {
1454 cpu_data(cpuid).dcache_size =
1455 of_getintprop_default(dp, "l1-dcache-size",
1457 cpu_data(cpuid).dcache_line_size =
1458 of_getintprop_default(dp, "l1-dcache-line-size",
1460 cpu_data(cpuid).icache_size =
1461 of_getintprop_default(dp, "l1-icache-size",
1463 cpu_data(cpuid).icache_line_size =
1464 of_getintprop_default(dp, "l1-icache-line-size",
1466 cpu_data(cpuid).ecache_size =
1467 of_getintprop_default(dp, "l2-cache-size", 0);
1468 cpu_data(cpuid).ecache_line_size =
1469 of_getintprop_default(dp, "l2-cache-line-size", 0);
1470 if (!cpu_data(cpuid).ecache_size ||
1471 !cpu_data(cpuid).ecache_line_size) {
1472 cpu_data(cpuid).ecache_size =
1473 of_getintprop_default(portid_parent,
1476 cpu_data(cpuid).ecache_line_size =
1477 of_getintprop_default(portid_parent,
1478 "l2-cache-line-size", 64);
1481 cpu_data(cpuid).core_id = portid + 1;
1482 cpu_data(cpuid).proc_id = portid;
1484 sparc64_multi_core = 1;
1487 cpu_data(cpuid).dcache_size =
1488 of_getintprop_default(dp, "dcache-size", 16 * 1024);
1489 cpu_data(cpuid).dcache_line_size =
1490 of_getintprop_default(dp, "dcache-line-size", 32);
1492 cpu_data(cpuid).icache_size =
1493 of_getintprop_default(dp, "icache-size", 16 * 1024);
1494 cpu_data(cpuid).icache_line_size =
1495 of_getintprop_default(dp, "icache-line-size", 32);
1497 cpu_data(cpuid).ecache_size =
1498 of_getintprop_default(dp, "ecache-size",
1500 cpu_data(cpuid).ecache_line_size =
1501 of_getintprop_default(dp, "ecache-line-size", 64);
1503 cpu_data(cpuid).core_id = 0;
1504 cpu_data(cpuid).proc_id = -1;
1508 cpu_set(cpuid, cpu_present_map);
1509 cpu_set(cpuid, cpu_possible_map);
1513 smp_fill_in_sib_core_maps();
1516 struct device_node *of_console_device;
1517 EXPORT_SYMBOL(of_console_device);
1519 char *of_console_path;
1520 EXPORT_SYMBOL(of_console_path);
1522 char *of_console_options;
1523 EXPORT_SYMBOL(of_console_options);
1525 static void __init of_console_init(void)
1527 char *msg = "OF stdout device is: %s\n";
1528 struct device_node *dp;
1532 of_console_path = prom_early_alloc(256);
1533 if (prom_ihandle2path(prom_stdout, of_console_path, 256) < 0) {
1534 prom_printf("Cannot obtain path of stdout.\n");
1537 of_console_options = strrchr(of_console_path, ':');
1538 if (of_console_options) {
1539 of_console_options++;
1540 if (*of_console_options == '\0')
1541 of_console_options = NULL;
1544 node = prom_inst2pkg(prom_stdout);
1546 prom_printf("Cannot resolve stdout node from "
1547 "instance %08x.\n", prom_stdout);
1551 dp = of_find_node_by_phandle(node);
1552 type = of_get_property(dp, "device_type", NULL);
1554 prom_printf("Console stdout lacks device_type property.\n");
1558 if (strcmp(type, "display") && strcmp(type, "serial")) {
1559 prom_printf("Console device_type is neither display "
1564 of_console_device = dp;
1566 printk(msg, of_console_path);
1569 void __init prom_build_devicetree(void)
1571 struct device_node **nextp;
1573 allnodes = create_node(prom_root_node, NULL);
1574 allnodes->path_component_name = "";
1575 allnodes->full_name = "/";
1577 nextp = &allnodes->allnext;
1578 allnodes->child = build_tree(allnodes,
1579 prom_getchild(allnodes->node),
1583 printk("PROM: Built device tree with %u bytes of memory.\n",
1584 prom_early_allocated);
1586 if (tlb_type != hypervisor)
1587 of_fill_in_cpu_data();