2 * rtrap.S: Preparing for return from trap on Sparc V9.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
12 #include <asm/spitfire.h>
14 #include <asm/visasm.h>
15 #include <asm/processor.h>
17 #define RTRAP_PSTATE (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
18 #define RTRAP_PSTATE_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
19 #define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
26 ba,a,pt %xcc, __handle_softirq_continue
30 wrpr %g0, RTRAP_PSTATE, %pstate
31 ba,pt %xcc, __handle_preemption_continue
32 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
34 __handle_user_windows:
35 call fault_in_user_windows
36 wrpr %g0, RTRAP_PSTATE, %pstate
37 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
38 /* Redo sched+sig checks */
39 ldx [%g6 + TI_FLAGS], %l0
40 andcc %l0, _TIF_NEED_RESCHED, %g0
45 wrpr %g0, RTRAP_PSTATE, %pstate
46 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
47 ldx [%g6 + TI_FLAGS], %l0
49 1: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
50 be,pt %xcc, __handle_user_windows_continue
53 add %sp, PTREGS_OFF, %o0
57 wrpr %g0, RTRAP_PSTATE, %pstate
58 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
59 /* Signal delivery can modify pt_regs tstate, so we must
62 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
63 sethi %hi(0xf << 20), %l4
65 ba,pt %xcc, __handle_user_windows_continue
70 andcc %l5, FPRS_FEF, %g0
71 sethi %hi(TSTATE_PEF), %o0
72 be,a,pn %icc, __handle_userfpu_continue
74 ba,a,pt %xcc, __handle_userfpu_continue
78 add %sp, PTREGS_OFF, %o0
81 wrpr %g0, RTRAP_PSTATE, %pstate
82 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
84 /* Signal delivery can modify pt_regs tstate, so we must
87 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
88 sethi %hi(0xf << 20), %l4
90 ba,pt %xcc, __handle_signal_continue
93 /* When returning from a NMI (%pil==15) interrupt we want to
94 * avoid running softirqs, doing IRQ tracing, preempting, etc.
97 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
98 sethi %hi(0xf << 20), %l4
102 ba,pt %xcc, rtrap_no_irq_enable
106 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
110 sethi %hi(__cpu_data), %l0
111 lduw [%l0 + %lo(__cpu_data)], %l1
113 sethi %hi(__cpu_data), %l0
114 or %l0, %lo(__cpu_data), %l0
115 lduw [%l0 + %g5], %l1
119 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
120 bne,pn %icc, __handle_softirq
121 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
122 __handle_softirq_continue:
124 sethi %hi(0xf << 20), %l4
128 #ifdef CONFIG_TRACE_IRQFLAGS
129 brnz,pn %l4, rtrap_no_irq_enable
131 call trace_hardirqs_on
136 andcc %l1, TSTATE_PRIV, %l3
137 bne,pn %icc, to_kernel
140 /* We must hold IRQs off and atomically test schedule+signal
141 * state, then hold them off all the way back to userspace.
142 * If we are returning to kernel, none of this matters. Note
143 * that we are disabling interrupts via PSTATE_IE, not using
146 * If we do not do this, there is a window where we would do
147 * the tests, later the signal/resched event arrives but we do
148 * not process it since we are still in kernel mode. It would
149 * take until the next local IRQ before the signal/resched
150 * event would be handled.
152 * This also means that if we have to deal with user
153 * windows, we have to redo all of these sched+signal checks
154 * with IRQs disabled.
156 to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
158 __handle_preemption_continue:
159 ldx [%g6 + TI_FLAGS], %l0
160 sethi %hi(_TIF_USER_WORK_MASK), %o0
161 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
163 sethi %hi(TSTATE_PEF), %o0
164 be,pt %xcc, user_nowork
166 andcc %l0, _TIF_NEED_RESCHED, %g0
167 bne,pn %xcc, __handle_preemption
168 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
169 bne,pn %xcc, __handle_signal
170 __handle_signal_continue:
171 ldub [%g6 + TI_WSAVED], %o2
172 brnz,pn %o2, __handle_user_windows
174 __handle_user_windows_continue:
175 sethi %hi(TSTATE_PEF), %o0
178 /* This fpdepth clear is necessary for non-syscall rtraps only */
180 bne,pn %xcc, __handle_userfpu
181 stb %g0, [%g6 + TI_FPDEPTH]
182 __handle_userfpu_continue:
184 rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
185 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
187 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
188 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
189 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
193 /* Must do this before thread reg is clobbered below. */
194 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
196 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
197 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
199 /* Normal globals are restored, go to trap globals. */
200 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
202 .section .sun4v_2insn_patch, "ax"
204 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
210 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
211 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
213 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
214 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
215 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
216 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
217 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
218 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
219 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
220 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
222 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
226 andn %l1, TSTATE_SYSCALL, %l1
227 wrpr %l1, %g0, %tstate
231 brnz,pn %l3, kern_rtt
232 mov PRIMARY_CONTEXT, %l7
234 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
235 .section .sun4v_1insn_patch, "ax"
237 ldxa [%l7 + %l7] ASI_MMU, %l0
240 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
241 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
244 661: stxa %l0, [%l7] ASI_DMMU
245 .section .sun4v_1insn_patch, "ax"
247 stxa %l0, [%l7] ASI_MMU
250 sethi %hi(KERNBASE), %l7
256 wrpr %l2, %g0, %canrestore
257 wrpr %l1, %g0, %wstate
258 brnz,pt %l2, user_rtt_restore
259 wrpr %g0, %g0, %otherwin
261 ldx [%g6 + TI_FLAGS], %g3
262 wr %g0, ASI_AIUP, %asi
264 andcc %g3, _TIF_32BIT, %g0
266 bne,pt %xcc, user_rtt_fill_32bit
268 ba,a,pt %xcc, user_rtt_fill_64bit
277 wrpr %g2, 0x0, %wstate
279 /* We know %canrestore and %otherwin are both zero. */
281 sethi %hi(sparc64_kern_pri_context), %g2
282 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
283 mov PRIMARY_CONTEXT, %g1
285 661: stxa %g2, [%g1] ASI_DMMU
286 .section .sun4v_1insn_patch, "ax"
288 stxa %g2, [%g1] ASI_MMU
291 sethi %hi(KERNBASE), %g1
294 or %g4, FAULT_CODE_WINFIXUP, %g4
295 stb %g4, [%g6 + TI_FAULT_CODE]
296 stx %g5, [%g6 + TI_FAULT_ADDR]
302 .section .sun4v_1insn_patch, "ax"
307 wrpr %g0, RTRAP_PSTATE, %pstate
310 ldx [%g6 + TI_TASK], %g4
311 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
312 call do_sparc64_fault
313 add %sp, PTREGS_OFF, %o0
317 user_rtt_pre_restore:
323 rdpr %canrestore, %g1
324 wrpr %g1, 0x0, %cleanwin
328 kern_rtt: rdpr %canrestore, %g1
329 brz,pn %g1, kern_rtt_fill
332 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
337 #ifdef CONFIG_PREEMPT
338 ldsw [%g6 + TI_PRE_COUNT], %l5
339 brnz %l5, kern_fpucheck
340 ldx [%g6 + TI_FLAGS], %l5
341 andcc %l5, _TIF_NEED_RESCHED, %g0
342 be,pt %xcc, kern_fpucheck
345 bne,pn %xcc, kern_fpucheck
346 sethi %hi(PREEMPT_ACTIVE), %l6
347 stw %l6, [%g6 + TI_PRE_COUNT]
351 stw %g0, [%g6 + TI_PRE_COUNT]
353 kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
354 brz,pt %l5, rt_continue
356 add %g6, TI_FPSAVED, %l6
357 ldub [%l6 + %o0], %l2
361 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
363 and %l2, FPRS_DL, %l6
364 andcc %l2, FPRS_FEF, %g0
369 wr %g1, FPRS_FEF, %fprs
371 add %g6, TI_XFSR, %o1
373 add %g6, TI_FPREGS, %o3
375 add %g6, TI_FPREGS+0x40, %o4
378 ldda [%o3 + %o2] ASI_BLK_P, %f0
379 ldda [%o4 + %o2] ASI_BLK_P, %f16
381 1: andcc %l2, FPRS_DU, %g0
386 ldda [%o3 + %o2] ASI_BLK_P, %f32
387 ldda [%o4 + %o2] ASI_BLK_P, %f48
389 ldx [%o1 + %o5], %fsr
390 2: stb %l5, [%g6 + TI_FPDEPTH]
391 ba,pt %xcc, rt_continue
393 5: wr %g0, FPRS_FEF, %fprs
396 add %g6, TI_FPREGS+0x80, %o3
397 add %g6, TI_FPREGS+0xc0, %o4
399 ldda [%o3 + %o2] ASI_BLK_P, %f32
400 ldda [%o4 + %o2] ASI_BLK_P, %f48
402 wr %g0, FPRS_DU, %fprs
403 ba,pt %xcc, rt_continue
404 stb %l5, [%g6 + TI_FPDEPTH]