2 * arch/sparc/kernel/sun4c_irq.c:
4 * djhr: Hacked out of irq.c into a CPU dependent version.
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
12 #include <linux/errno.h>
13 #include <linux/linkage.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
16 #include <linux/sched.h>
17 #include <linux/ptrace.h>
18 #include <linux/interrupt.h>
19 #include <linux/init.h>
21 #include <linux/of_device.h>
24 #include <asm/ptrace.h>
25 #include <asm/processor.h>
26 #include <asm/system.h>
28 #include <asm/vaddrs.h>
29 #include <asm/timer.h>
30 #include <asm/openprom.h>
31 #include <asm/oplib.h>
32 #include <asm/traps.h>
35 #include <asm/idprom.h>
36 #include <asm/machines.h>
39 * Bit field defines for the interrupt registers on various
43 /* The sun4c interrupt register. */
44 #define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
45 #define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
46 #define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
47 #define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
48 #define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
49 #define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
50 #define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
52 /* Pointer to the interrupt enable byte
54 * Dave Redman (djhr@tadpole.co.uk)
55 * What you may not be aware of is that entry.S requires this variable.
57 * --- linux_trap_nmi_sun4c --
59 * so don't go making it static, like I tried. sigh.
61 unsigned char __iomem *interrupt_enable = NULL;
63 static void sun4c_disable_irq(unsigned int irq_nr)
66 unsigned char current_mask, new_mask;
68 local_irq_save(flags);
69 irq_nr &= (NR_IRQS - 1);
70 current_mask = sbus_readb(interrupt_enable);
73 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
76 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
79 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
82 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
85 local_irq_restore(flags);
88 sbus_writeb(new_mask, interrupt_enable);
89 local_irq_restore(flags);
92 static void sun4c_enable_irq(unsigned int irq_nr)
95 unsigned char current_mask, new_mask;
97 local_irq_save(flags);
98 irq_nr &= (NR_IRQS - 1);
99 current_mask = sbus_readb(interrupt_enable);
102 new_mask = ((current_mask) | SUN4C_INT_E1);
105 new_mask = ((current_mask) | SUN4C_INT_E8);
108 new_mask = ((current_mask) | SUN4C_INT_E10);
111 new_mask = ((current_mask) | SUN4C_INT_E14);
114 local_irq_restore(flags);
117 sbus_writeb(new_mask, interrupt_enable);
118 local_irq_restore(flags);
121 struct sun4c_timer_info {
128 static struct sun4c_timer_info __iomem *sun4c_timers;
130 static void sun4c_clear_clock_irq(void)
132 sbus_readl(&sun4c_timers->l10_limit);
135 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
137 /* Errm.. not sure how to do this.. */
140 static void __init sun4c_init_timers(irq_handler_t counter_fn)
142 const struct linux_prom_irqs *irq;
143 struct device_node *dp;
147 dp = of_find_node_by_name(NULL, "counter-timer");
149 prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
153 addr = of_get_property(dp, "address", NULL);
155 prom_printf("sun4c_init_timers: No address property\n");
159 sun4c_timers = (void __iomem *) (unsigned long) addr[0];
161 irq = of_get_property(dp, "intr", NULL);
164 prom_printf("sun4c_init_timers: No intr property\n");
168 /* Have the level 10 timer tick at 100HZ. We don't touch the
169 * level 14 timer limit since we are letting the prom handle
170 * them until we have a real console driver so L1-A works.
172 sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
174 master_l10_counter = &sun4c_timers->l10_count;
176 err = request_irq(irq[0].pri, counter_fn,
177 (IRQF_DISABLED | SA_STATIC_ALLOC),
180 prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
184 sun4c_disable_irq(irq[1].pri);
188 static void sun4c_nop(void) {}
191 void __init sun4c_init_IRQ(void)
193 struct device_node *dp;
196 dp = of_find_node_by_name(NULL, "interrupt-enable");
198 prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
202 addr = of_get_property(dp, "address", NULL);
205 prom_printf("sun4c_init_IRQ: No address property\n");
209 interrupt_enable = (void __iomem *) (unsigned long) addr[0];
211 BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
212 BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
213 BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
214 BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
215 BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
216 BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
217 sparc_init_timers = sun4c_init_timers;
219 BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
220 BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
221 BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
223 sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
224 /* Cannot enable interrupts until OBP ticker is disabled. */