1 /* clear_page.S: UltraSparc optimized copy page.
3 * Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1997 Jakub Jelinek (jakub@redhat.com)
7 #include <asm/visasm.h>
8 #include <asm/thread_info.h>
10 #include <asm/pgtable.h>
11 #include <asm/spitfire.h>
14 /* What we used to do was lock a TLB entry into a specific
15 * TLB slot, clear the page with interrupts disabled, then
16 * restore the original TLB entry. This was great for
17 * disturbing the TLB as little as possible, but it meant
18 * we had to keep interrupts disabled for a long time.
20 * Now, we simply use the normal TLB loading mechanism,
21 * and this makes the cpu choose a slot all by itself.
22 * Then we do a normal TLB flush on exit. We need only
23 * disable preemption during the clear.
26 #define DCACHE_SIZE (PAGE_SIZE * 2)
28 #if (PAGE_SHIFT == 13)
29 #define PAGE_SIZE_REM 0x80
30 #elif (PAGE_SHIFT == 16)
31 #define PAGE_SIZE_REM 0x100
33 #error Wrong PAGE_SHIFT specified
36 #define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7) \
37 fsrc2 %reg0, %f48; fsrc2 %reg1, %f50; \
38 fsrc2 %reg2, %f52; fsrc2 %reg3, %f54; \
39 fsrc2 %reg4, %f56; fsrc2 %reg5, %f58; \
40 fsrc2 %reg6, %f60; fsrc2 %reg7, %f62;
46 .type copy_user_page,#function
47 copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
48 lduw [%g6 + TI_PRE_COUNT], %o4
49 sethi %hi(PAGE_OFFSET), %g2
50 sethi %hi(PAGE_SIZE), %o3
52 ldx [%g2 + %lo(PAGE_OFFSET)], %g2
53 sethi %hi(PAGE_KERNEL_LOCKED), %g3
55 ldx [%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3
56 sub %o0, %g2, %g1 ! dest paddr
58 sub %o1, %g2, %g2 ! src paddr
60 and %o2, %o3, %o0 ! vaddr D-cache alias bit
61 or %g1, %g3, %g1 ! dest TTE data
63 or %g2, %g3, %g2 ! src TTE data
64 sethi %hi(TLBTEMP_BASE), %o3
66 sethi %hi(DCACHE_SIZE), %o1
67 add %o0, %o3, %o0 ! dest TTE vaddr
70 add %o0, %o1, %o1 ! src TTE vaddr
72 /* Disable preemption. */
73 mov TLB_TAG_ACCESS, %g3
74 stw %o2, [%g6 + TI_PRE_COUNT]
76 /* Load TLB entries. */
78 wrpr %o2, PSTATE_IE, %pstate
79 stxa %o0, [%g3] ASI_DMMU
80 stxa %g1, [%g0] ASI_DTLB_DATA_IN
82 stxa %o1, [%g3] ASI_DMMU
83 stxa %g2, [%g0] ASI_DTLB_DATA_IN
85 wrpr %o2, 0x0, %pstate
87 cheetah_copy_page_insn:
93 membar #StoreLoad | #StoreStore | #LoadStore
94 sethi %hi((PAGE_SIZE/64)-2), %o2
96 prefetch [%o1 + 0x000], #one_read
97 or %o2, %lo((PAGE_SIZE/64)-2), %o2
98 prefetch [%o1 + 0x040], #one_read
99 prefetch [%o1 + 0x080], #one_read
100 prefetch [%o1 + 0x0c0], #one_read
101 ldd [%o1 + 0x000], %f0
102 prefetch [%o1 + 0x100], #one_read
103 ldd [%o1 + 0x008], %f2
104 prefetch [%o1 + 0x140], #one_read
105 ldd [%o1 + 0x010], %f4
106 prefetch [%o1 + 0x180], #one_read
108 ldd [%o1 + 0x018], %f6
110 ldd [%o1 + 0x020], %f8
112 ldd [%o1 + 0x028], %f10
114 ldd [%o1 + 0x030], %f12
116 ldd [%o1 + 0x038], %f14
118 ldd [%o1 + 0x040], %f0
119 1: ldd [%o1 + 0x048], %f2
121 ldd [%o1 + 0x050], %f4
123 stda %f16, [%o0] ASI_BLK_P
124 ldd [%o1 + 0x058], %f6
126 ldd [%o1 + 0x060], %f8
128 ldd [%o1 + 0x068], %f10
130 ldd [%o1 + 0x070], %f12
132 ldd [%o1 + 0x078], %f14
134 ldd [%o1 + 0x080], %f0
135 prefetch [%o1 + 0x180], #one_read
142 ldd [%o1 + 0x048], %f2
144 ldd [%o1 + 0x050], %f4
146 stda %f16, [%o0] ASI_BLK_P
147 ldd [%o1 + 0x058], %f6
149 ldd [%o1 + 0x060], %f8
151 ldd [%o1 + 0x068], %f10
153 ldd [%o1 + 0x070], %f12
156 ldd [%o1 + 0x078], %f14
161 stda %f16, [%o0] ASI_BLK_P
169 ldub [%g6 + TI_FAULT_CODE], %g3
174 wr %g0, ASI_BLK_P, %asi
175 wr %g0, ASI_BLK_COMMIT_P, %asi
176 1: ldda [%o1] ASI_BLK_P, %f0
178 ldda [%o1] ASI_BLK_P, %f16
180 sethi %hi(PAGE_SIZE), %o2
181 1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
182 ldda [%o1] ASI_BLK_P, %f32
183 stda %f48, [%o0] %asi
187 TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
188 ldda [%o1] ASI_BLK_P, %f0
189 stda %f48, [%o0] %asi
193 TOUCH(f32, f34, f36, f38, f40, f42, f44, f46)
194 ldda [%o1] ASI_BLK_P, %f16
195 stda %f48, [%o0] %asi
198 cmp %o2, PAGE_SIZE_REM
201 #if (PAGE_SHIFT == 16)
202 TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
203 ldda [%o1] ASI_BLK_P, %f32
204 stda %f48, [%o0] %asi
208 TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
209 ldda [%o1] ASI_BLK_P, %f0
210 stda %f48, [%o0] %asi
215 stda %f32, [%o0] %asi
222 stda %f16, [%o0] %asi
229 stxa %g0, [%g1] ASI_DMMU_DEMAP
232 sethi %hi(DCACHE_SIZE), %g2
233 stxa %g0, [%g1 + %g2] ASI_DMMU_DEMAP
237 stw %o4, [%g6 + TI_PRE_COUNT]
239 .size copy_user_page, .-copy_user_page
241 .globl cheetah_patch_copy_page
242 cheetah_patch_copy_page:
243 sethi %hi(0x01000000), %o1 ! NOP
244 sethi %hi(cheetah_copy_page_insn), %o0
245 or %o0, %lo(cheetah_copy_page_insn), %o0