arch/sparc/mm/init_64.c

   1 /*
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/initrd.h>
  17 #include <linux/swap.h>
  18 #include <linux/pagemap.h>
  19 #include <linux/poison.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25 #include <linux/percpu.h>
  26 #include <linux/memblock.h>
  27 #include <linux/mmzone.h>
  28 #include <linux/gfp.h>
  29
  30 #include <asm/head.h>
  31 #include <asm/page.h>
  32 #include <asm/pgalloc.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/oplib.h>
  35 #include <asm/iommu.h>
  36 #include <asm/io.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/mmu_context.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/dma.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/spitfire.h>
  44 #include <asm/sections.h>
  45 #include <asm/tsb.h>
  46 #include <asm/hypervisor.h>
  47 #include <asm/prom.h>
  48 #include <asm/mdesc.h>
  49 #include <asm/cpudata.h>
  50 #include <asm/irq.h>
  51
  52 #include "init_64.h"
  53
  54 unsigned long kern_linear_pte_xor[4] __read_mostly;
  55
  56 /* A bitmap, two bits for every 256MB of physical memory.  These two
  57  * bits determine what page size we use for kernel linear
  58  * translations.  They form an index into kern_linear_pte_xor[].  The
  59  * value in the indexed slot is XOR'd with the TLB miss virtual
  60  * address to form the resulting TTE.  The mapping is:
  61  *
  62  *      0       ==>     4MB
  63  *      1       ==>     256MB
  64  *      2       ==>     2GB
  65  *      3       ==>     16GB
  66  *
  67  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  68  * support 2GB pages, and hopefully future cpus will support the 16GB
  69  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  70  * if these larger page sizes are not supported by the cpu.
  71  *
  72  * It would be nice to determine this from the machine description
  73  * 'cpu' properties, but we need to have this table setup before the
  74  * MDESC is initialized.
  75  */
  76 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
  77
  78 #ifndef CONFIG_DEBUG_PAGEALLOC
  79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  80  * Space is allocated for this right after the trap table in
  81  * arch/sparc64/kernel/head.S
  82  */
  83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  84 #endif
  85
  86 static unsigned long cpu_pgsz_mask;
  87
  88 #define MAX_BANKS       32
  89
  90 static struct linux_prom64_registers pavail[MAX_BANKS];
  91 static int pavail_ents;
  92
  93 static int cmp_p64(const void *a, const void *b)
  94 {
  95         const struct linux_prom64_registers *x = a, *y = b;
  96
  97         if (x->phys_addr > y->phys_addr)
  98                 return 1;
  99         if (x->phys_addr < y->phys_addr)
 100                 return -1;
 101         return 0;
 102 }
 103
 104 static void __init read_obp_memory(const char *property,
 105                                    struct linux_prom64_registers *regs,
 106                                    int *num_ents)
 107 {
 108         phandle node = prom_finddevice("/memory");
 109         int prop_size = prom_getproplen(node, property);
 110         int ents, ret, i;
 111
 112         ents = prop_size / sizeof(struct linux_prom64_registers);
 113         if (ents > MAX_BANKS) {
 114                 prom_printf("The machine has more %s property entries than "
 115                             "this kernel can support (%d).\n",
 116                             property, MAX_BANKS);
 117                 prom_halt();
 118         }
 119
 120         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 121         if (ret == -1) {
 122                 prom_printf("Couldn't get %s property from /memory.\n",
 123                                 property);
 124                 prom_halt();
 125         }
 126
 127         /* Sanitize what we got from the firmware, by page aligning
 128          * everything.
 129          */
 130         for (i = 0; i < ents; i++) {
 131                 unsigned long base, size;
 132
 133                 base = regs[i].phys_addr;
 134                 size = regs[i].reg_size;
 135
 136                 size &= PAGE_MASK;
 137                 if (base & ~PAGE_MASK) {
 138                         unsigned long new_base = PAGE_ALIGN(base);
 139
 140                         size -= new_base - base;
 141                         if ((long) size < 0L)
 142                                 size = 0UL;
 143                         base = new_base;
 144                 }
 145                 if (size == 0UL) {
 146                         /* If it is empty, simply get rid of it.
 147                          * This simplifies the logic of the other
 148                          * functions that process these arrays.
 149                          */
 150                         memmove(&regs[i], &regs[i + 1],
 151                                 (ents - i - 1) * sizeof(regs[0]));
 152                         i--;
 153                         ents--;
 154                         continue;
 155                 }
 156                 regs[i].phys_addr = base;
 157                 regs[i].reg_size = size;
 158         }
 159
 160         *num_ents = ents;
 161
 162         sort(regs, ents, sizeof(struct linux_prom64_registers),
 163              cmp_p64, NULL);
 164 }
 165
 166 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
 167                                         sizeof(unsigned long)];
 168 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
 169
 170 /* Kernel physical address base and size in bytes.  */
 171 unsigned long kern_base __read_mostly;
 172 unsigned long kern_size __read_mostly;
 173
 174 /* Initial ramdisk setup */
 175 extern unsigned long sparc_ramdisk_image64;
 176 extern unsigned int sparc_ramdisk_image;
 177 extern unsigned int sparc_ramdisk_size;
 178
 179 struct page *mem_map_zero __read_mostly;
 180 EXPORT_SYMBOL(mem_map_zero);
 181
 182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 183
 184 unsigned long sparc64_kern_pri_context __read_mostly;
 185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 186 unsigned long sparc64_kern_sec_context __read_mostly;
 187
 188 int num_kernel_image_mappings;
 189
 190 #ifdef CONFIG_DEBUG_DCFLUSH
 191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 192 #ifdef CONFIG_SMP
 193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 194 #endif
 195 #endif
 196
 197 inline void flush_dcache_page_impl(struct page *page)
 198 {
 199         BUG_ON(tlb_type == hypervisor);
 200 #ifdef CONFIG_DEBUG_DCFLUSH
 201         atomic_inc(&dcpage_flushes);
 202 #endif
 203
 204 #ifdef DCACHE_ALIASING_POSSIBLE
 205         __flush_dcache_page(page_address(page),
 206                             ((tlb_type == spitfire) &&
 207                              page_mapping(page) != NULL));
 208 #else
 209         if (page_mapping(page) != NULL &&
 210             tlb_type == spitfire)
 211                 __flush_icache_page(__pa(page_address(page)));
 212 #endif
 213 }
 214
 215 #define PG_dcache_dirty         PG_arch_1
 216 #define PG_dcache_cpu_shift     32UL
 217 #define PG_dcache_cpu_mask      \
 218         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 219
 220 #define dcache_dirty_cpu(page) \
 221         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 222
 223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 224 {
 225         unsigned long mask = this_cpu;
 226         unsigned long non_cpu_bits;
 227
 228         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 229         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 230
 231         __asm__ __volatile__("1:\n\t"
 232                              "ldx       [%2], %%g7\n\t"
 233                              "and       %%g7, %1, %%g1\n\t"
 234                              "or        %%g1, %0, %%g1\n\t"
 235                              "casx      [%2], %%g7, %%g1\n\t"
 236                              "cmp       %%g7, %%g1\n\t"
 237                              "bne,pn    %%xcc, 1b\n\t"
 238                              " nop"
 239                              : /* no outputs */
 240                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 241                              : "g1", "g7");
 242 }
 243
 244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 245 {
 246         unsigned long mask = (1UL << PG_dcache_dirty);
 247
 248         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 249                              "1:\n\t"
 250                              "ldx       [%2], %%g7\n\t"
 251                              "srlx      %%g7, %4, %%g1\n\t"
 252                              "and       %%g1, %3, %%g1\n\t"
 253                              "cmp       %%g1, %0\n\t"
 254                              "bne,pn    %%icc, 2f\n\t"
 255                              " andn     %%g7, %1, %%g1\n\t"
 256                              "casx      [%2], %%g7, %%g1\n\t"
 257                              "cmp       %%g7, %%g1\n\t"
 258                              "bne,pn    %%xcc, 1b\n\t"
 259                              " nop\n"
 260                              "2:"
 261                              : /* no outputs */
 262                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 263                                "i" (PG_dcache_cpu_mask),
 264                                "i" (PG_dcache_cpu_shift)
 265                              : "g1", "g7");
 266 }
 267
 268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 269 {
 270         unsigned long tsb_addr = (unsigned long) ent;
 271
 272         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 273                 tsb_addr = __pa(tsb_addr);
 274
 275         __tsb_insert(tsb_addr, tag, pte);
 276 }
 277
 278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 279
 280 static void flush_dcache(unsigned long pfn)
 281 {
 282         struct page *page;
 283
 284         page = pfn_to_page(pfn);
 285         if (page) {
 286                 unsigned long pg_flags;
 287
 288                 pg_flags = page->flags;
 289                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 290                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 291                                    PG_dcache_cpu_mask);
 292                         int this_cpu = get_cpu();
 293
 294                         /* This is just to optimize away some function calls
 295                          * in the SMP case.
 296                          */
 297                         if (cpu == this_cpu)
 298                                 flush_dcache_page_impl(page);
 299                         else
 300                                 smp_flush_dcache_page_impl(page, cpu);
 301
 302                         clear_dcache_dirty_cpu(page, cpu);
 303
 304                         put_cpu();
 305                 }
 306         }
 307 }
 308
 309 /* mm->context.lock must be held */
 310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 311                                     unsigned long tsb_hash_shift, unsigned long address,
 312                                     unsigned long tte)
 313 {
 314         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 315         unsigned long tag;
 316
 317         if (unlikely(!tsb))
 318                 return;
 319
 320         tsb += ((address >> tsb_hash_shift) &
 321                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 322         tag = (address >> 22UL);
 323         tsb_insert(tsb, tag, tte);
 324 }
 325
 326 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 327 static inline bool is_hugetlb_pte(pte_t pte)
 328 {
 329         if ((tlb_type == hypervisor &&
 330              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 331             (tlb_type != hypervisor &&
 332              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
 333                 return true;
 334         return false;
 335 }
 336 #endif
 337
 338 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 339 {
 340         struct mm_struct *mm;
 341         unsigned long flags;
 342         pte_t pte = *ptep;
 343
 344         if (tlb_type != hypervisor) {
 345                 unsigned long pfn = pte_pfn(pte);
 346
 347                 if (pfn_valid(pfn))
 348                         flush_dcache(pfn);
 349         }
 350
 351         mm = vma->vm_mm;
 352
 353         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
 354         if (!pte_accessible(mm, pte))
 355                 return;
 356
 357         spin_lock_irqsave(&mm->context.lock, flags);
 358
 359 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 360         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
 361                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
 362                                         address, pte_val(pte));
 363         else
 364 #endif
 365                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 366                                         address, pte_val(pte));
 367
 368         spin_unlock_irqrestore(&mm->context.lock, flags);
 369 }
 370
 371 void flush_dcache_page(struct page *page)
 372 {
 373         struct address_space *mapping;
 374         int this_cpu;
 375
 376         if (tlb_type == hypervisor)
 377                 return;
 378
 379         /* Do not bother with the expensive D-cache flush if it
 380          * is merely the zero page.  The 'bigcore' testcase in GDB
 381          * causes this case to run millions of times.
 382          */
 383         if (page == ZERO_PAGE(0))
 384                 return;
 385
 386         this_cpu = get_cpu();
 387
 388         mapping = page_mapping(page);
 389         if (mapping && !mapping_mapped(mapping)) {
 390                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 391                 if (dirty) {
 392                         int dirty_cpu = dcache_dirty_cpu(page);
 393
 394                         if (dirty_cpu == this_cpu)
 395                                 goto out;
 396                         smp_flush_dcache_page_impl(page, dirty_cpu);
 397                 }
 398                 set_dcache_dirty(page, this_cpu);
 399         } else {
 400                 /* We could delay the flush for the !page_mapping
 401                  * case too.  But that case is for exec env/arg
 402                  * pages and those are %99 certainly going to get
 403                  * faulted into the tlb (and thus flushed) anyways.
 404                  */
 405                 flush_dcache_page_impl(page);
 406         }
 407
 408 out:
 409         put_cpu();
 410 }
 411 EXPORT_SYMBOL(flush_dcache_page);
 412
 413 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 414 {
 415         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 416         if (tlb_type == spitfire) {
 417                 unsigned long kaddr;
 418
 419                 /* This code only runs on Spitfire cpus so this is
 420                  * why we can assume _PAGE_PADDR_4U.
 421                  */
 422                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 423                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 424
 425                         if (kaddr >= PAGE_OFFSET)
 426                                 paddr = kaddr & mask;
 427                         else {
 428                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 429                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 430                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 431                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 432
 433                                 paddr = pte_val(*ptep) & mask;
 434                         }
 435                         __flush_icache_page(paddr);
 436                 }
 437         }
 438 }
 439 EXPORT_SYMBOL(flush_icache_range);
 440
 441 void mmu_info(struct seq_file *m)
 442 {
 443         static const char *pgsz_strings[] = {
 444                 "8K", "64K", "512K", "4MB", "32MB",
 445                 "256MB", "2GB", "16GB",
 446         };
 447         int i, printed;
 448
 449         if (tlb_type == cheetah)
 450                 seq_printf(m, "MMU Type\t: Cheetah\n");
 451         else if (tlb_type == cheetah_plus)
 452                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 453         else if (tlb_type == spitfire)
 454                 seq_printf(m, "MMU Type\t: Spitfire\n");
 455         else if (tlb_type == hypervisor)
 456                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 457         else
 458                 seq_printf(m, "MMU Type\t: ???\n");
 459
 460         seq_printf(m, "MMU PGSZs\t: ");
 461         printed = 0;
 462         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 463                 if (cpu_pgsz_mask & (1UL << i)) {
 464                         seq_printf(m, "%s%s",
 465                                    printed ? "," : "", pgsz_strings[i]);
 466                         printed++;
 467                 }
 468         }
 469         seq_putc(m, '\n');
 470
 471 #ifdef CONFIG_DEBUG_DCFLUSH
 472         seq_printf(m, "DCPageFlushes\t: %d\n",
 473                    atomic_read(&dcpage_flushes));
 474 #ifdef CONFIG_SMP
 475         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 476                    atomic_read(&dcpage_flushes_xcall));
 477 #endif /* CONFIG_SMP */
 478 #endif /* CONFIG_DEBUG_DCFLUSH */
 479 }
 480
 481 struct linux_prom_translation prom_trans[512] __read_mostly;
 482 unsigned int prom_trans_ents __read_mostly;
 483
 484 unsigned long kern_locked_tte_data;
 485
 486 /* The obp translations are saved based on 8k pagesize, since obp can
 487  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 488  * HI_OBP_ADDRESS range are handled in ktlb.S.
 489  */
 490 static inline int in_obp_range(unsigned long vaddr)
 491 {
 492         return (vaddr >= LOW_OBP_ADDRESS &&
 493                 vaddr < HI_OBP_ADDRESS);
 494 }
 495
 496 static int cmp_ptrans(const void *a, const void *b)
 497 {
 498         const struct linux_prom_translation *x = a, *y = b;
 499
 500         if (x->virt > y->virt)
 501                 return 1;
 502         if (x->virt < y->virt)
 503                 return -1;
 504         return 0;
 505 }
 506
 507 /* Read OBP translations property into 'prom_trans[]'.  */
 508 static void __init read_obp_translations(void)
 509 {
 510         int n, node, ents, first, last, i;
 511
 512         node = prom_finddevice("/virtual-memory");
 513         n = prom_getproplen(node, "translations");
 514         if (unlikely(n == 0 || n == -1)) {
 515                 prom_printf("prom_mappings: Couldn't get size.\n");
 516                 prom_halt();
 517         }
 518         if (unlikely(n > sizeof(prom_trans))) {
 519                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 520                 prom_halt();
 521         }
 522
 523         if ((n = prom_getproperty(node, "translations",
 524                                   (char *)&prom_trans[0],
 525                                   sizeof(prom_trans))) == -1) {
 526                 prom_printf("prom_mappings: Couldn't get property.\n");
 527                 prom_halt();
 528         }
 529
 530         n = n / sizeof(struct linux_prom_translation);
 531
 532         ents = n;
 533
 534         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 535              cmp_ptrans, NULL);
 536
 537         /* Now kick out all the non-OBP entries.  */
 538         for (i = 0; i < ents; i++) {
 539                 if (in_obp_range(prom_trans[i].virt))
 540                         break;
 541         }
 542         first = i;
 543         for (; i < ents; i++) {
 544                 if (!in_obp_range(prom_trans[i].virt))
 545                         break;
 546         }
 547         last = i;
 548
 549         for (i = 0; i < (last - first); i++) {
 550                 struct linux_prom_translation *src = &prom_trans[i + first];
 551                 struct linux_prom_translation *dest = &prom_trans[i];
 552
 553                 *dest = *src;
 554         }
 555         for (; i < ents; i++) {
 556                 struct linux_prom_translation *dest = &prom_trans[i];
 557                 dest->virt = dest->size = dest->data = 0x0UL;
 558         }
 559
 560         prom_trans_ents = last - first;
 561
 562         if (tlb_type == spitfire) {
 563                 /* Clear diag TTE bits. */
 564                 for (i = 0; i < prom_trans_ents; i++)
 565                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 566         }
 567
 568         /* Force execute bit on.  */
 569         for (i = 0; i < prom_trans_ents; i++)
 570                 prom_trans[i].data |= (tlb_type == hypervisor ?
 571                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 572 }
 573
 574 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 575                                        unsigned long pte,
 576                                        unsigned long mmu)
 577 {
 578         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 579
 580         if (ret != 0) {
 581                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 582                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 583                 prom_halt();
 584         }
 585 }
 586
 587 static unsigned long kern_large_tte(unsigned long paddr);
 588
 589 static void __init remap_kernel(void)
 590 {
 591         unsigned long phys_page, tte_vaddr, tte_data;
 592         int i, tlb_ent = sparc64_highest_locked_tlbent();
 593
 594         tte_vaddr = (unsigned long) KERNBASE;
 595         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
 596         tte_data = kern_large_tte(phys_page);
 597
 598         kern_locked_tte_data = tte_data;
 599
 600         /* Now lock us into the TLBs via Hypervisor or OBP. */
 601         if (tlb_type == hypervisor) {
 602                 for (i = 0; i < num_kernel_image_mappings; i++) {
 603                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 604                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 605                         tte_vaddr += 0x400000;
 606                         tte_data += 0x400000;
 607                 }
 608         } else {
 609                 for (i = 0; i < num_kernel_image_mappings; i++) {
 610                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 611                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 612                         tte_vaddr += 0x400000;
 613                         tte_data += 0x400000;
 614                 }
 615                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 616         }
 617         if (tlb_type == cheetah_plus) {
 618                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 619                                             CTX_CHEETAH_PLUS_NUC);
 620                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 621                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 622         }
 623 }
 624
 625
 626 static void __init inherit_prom_mappings(void)
 627 {
 628         /* Now fixup OBP's idea about where we really are mapped. */
 629         printk("Remapping the kernel... ");
 630         remap_kernel();
 631         printk("done.\n");
 632 }
 633
 634 void prom_world(int enter)
 635 {
 636         if (!enter)
 637                 set_fs(get_fs());
 638
 639         __asm__ __volatile__("flushw");
 640 }
 641
 642 void __flush_dcache_range(unsigned long start, unsigned long end)
 643 {
 644         unsigned long va;
 645
 646         if (tlb_type == spitfire) {
 647                 int n = 0;
 648
 649                 for (va = start; va < end; va += 32) {
 650                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 651                         if (++n >= 512)
 652                                 break;
 653                 }
 654         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 655                 start = __pa(start);
 656                 end = __pa(end);
 657                 for (va = start; va < end; va += 32)
 658                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 659                                              "membar #Sync"
 660                                              : /* no outputs */
 661                                              : "r" (va),
 662                                                "i" (ASI_DCACHE_INVALIDATE));
 663         }
 664 }
 665 EXPORT_SYMBOL(__flush_dcache_range);
 666
 667 /* get_new_mmu_context() uses "cache + 1".  */
 668 DEFINE_SPINLOCK(ctx_alloc_lock);
 669 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 670 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 671 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 672 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 673
 674 /* Caller does TLB context flushing on local CPU if necessary.
 675  * The caller also ensures that CTX_VALID(mm->context) is false.
 676  *
 677  * We must be careful about boundary cases so that we never
 678  * let the user have CTX 0 (nucleus) or we ever use a CTX
 679  * version of zero (and thus NO_CONTEXT would not be caught
 680  * by version mis-match tests in mmu_context.h).
 681  *
 682  * Always invoked with interrupts disabled.
 683  */
 684 void get_new_mmu_context(struct mm_struct *mm)
 685 {
 686         unsigned long ctx, new_ctx;
 687         unsigned long orig_pgsz_bits;
 688         int new_version;
 689
 690         spin_lock(&ctx_alloc_lock);
 691         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 692         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 693         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 694         new_version = 0;
 695         if (new_ctx >= (1 << CTX_NR_BITS)) {
 696                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 697                 if (new_ctx >= ctx) {
 698                         int i;
 699                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 700                                 CTX_FIRST_VERSION;
 701                         if (new_ctx == 1)
 702                                 new_ctx = CTX_FIRST_VERSION;
 703
 704                         /* Don't call memset, for 16 entries that's just
 705                          * plain silly...
 706                          */
 707                         mmu_context_bmap[0] = 3;
 708                         mmu_context_bmap[1] = 0;
 709                         mmu_context_bmap[2] = 0;
 710                         mmu_context_bmap[3] = 0;
 711                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 712                                 mmu_context_bmap[i + 0] = 0;
 713                                 mmu_context_bmap[i + 1] = 0;
 714                                 mmu_context_bmap[i + 2] = 0;
 715                                 mmu_context_bmap[i + 3] = 0;
 716                         }
 717                         new_version = 1;
 718                         goto out;
 719                 }
 720         }
 721         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 722         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 723 out:
 724         tlb_context_cache = new_ctx;
 725         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 726         spin_unlock(&ctx_alloc_lock);
 727
 728         if (unlikely(new_version))
 729                 smp_new_mmu_context_version();
 730 }
 731
 732 static int numa_enabled = 1;
 733 static int numa_debug;
 734
 735 static int __init early_numa(char *p)
 736 {
 737         if (!p)
 738                 return 0;
 739
 740         if (strstr(p, "off"))
 741                 numa_enabled = 0;
 742
 743         if (strstr(p, "debug"))
 744                 numa_debug = 1;
 745
 746         return 0;
 747 }
 748 early_param("numa", early_numa);
 749
 750 #define numadbg(f, a...) \
 751 do {    if (numa_debug) \
 752                 printk(KERN_INFO f, ## a); \
 753 } while (0)
 754
 755 static void __init find_ramdisk(unsigned long phys_base)
 756 {
 757 #ifdef CONFIG_BLK_DEV_INITRD
 758         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 759                 unsigned long ramdisk_image;
 760
 761                 /* Older versions of the bootloader only supported a
 762                  * 32-bit physical address for the ramdisk image
 763                  * location, stored at sparc_ramdisk_image.  Newer
 764                  * SILO versions set sparc_ramdisk_image to zero and
 765                  * provide a full 64-bit physical address at
 766                  * sparc_ramdisk_image64.
 767                  */
 768                 ramdisk_image = sparc_ramdisk_image;
 769                 if (!ramdisk_image)
 770                         ramdisk_image = sparc_ramdisk_image64;
 771
 772                 /* Another bootloader quirk.  The bootloader normalizes
 773                  * the physical address to KERNBASE, so we have to
 774                  * factor that back out and add in the lowest valid
 775                  * physical page address to get the true physical address.
 776                  */
 777                 ramdisk_image -= KERNBASE;
 778                 ramdisk_image += phys_base;
 779
 780                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 781                         ramdisk_image, sparc_ramdisk_size);
 782
 783                 initrd_start = ramdisk_image;
 784                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 785
 786                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 787
 788                 initrd_start += PAGE_OFFSET;
 789                 initrd_end += PAGE_OFFSET;
 790         }
 791 #endif
 792 }
 793
 794 struct node_mem_mask {
 795         unsigned long mask;
 796         unsigned long val;
 797 };
 798 static struct node_mem_mask node_masks[MAX_NUMNODES];
 799 static int num_node_masks;
 800
 801 int numa_cpu_lookup_table[NR_CPUS];
 802 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 803
 804 #ifdef CONFIG_NEED_MULTIPLE_NODES
 805
 806 struct mdesc_mblock {
 807         u64     base;
 808         u64     size;
 809         u64     offset; /* RA-to-PA */
 810 };
 811 static struct mdesc_mblock *mblocks;
 812 static int num_mblocks;
 813
 814 static unsigned long ra_to_pa(unsigned long addr)
 815 {
 816         int i;
 817
 818         for (i = 0; i < num_mblocks; i++) {
 819                 struct mdesc_mblock *m = &mblocks[i];
 820
 821                 if (addr >= m->base &&
 822                     addr < (m->base + m->size)) {
 823                         addr += m->offset;
 824                         break;
 825                 }
 826         }
 827         return addr;
 828 }
 829
 830 static int find_node(unsigned long addr)
 831 {
 832         int i;
 833
 834         addr = ra_to_pa(addr);
 835         for (i = 0; i < num_node_masks; i++) {
 836                 struct node_mem_mask *p = &node_masks[i];
 837
 838                 if ((addr & p->mask) == p->val)
 839                         return i;
 840         }
 841         /* The following condition has been observed on LDOM guests.*/
 842         WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
 843                 " rule. Some physical memory will be owned by node 0.");
 844         return 0;
 845 }
 846
 847 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
 848 {
 849         *nid = find_node(start);
 850         start += PAGE_SIZE;
 851         while (start < end) {
 852                 int n = find_node(start);
 853
 854                 if (n != *nid)
 855                         break;
 856                 start += PAGE_SIZE;
 857         }
 858
 859         if (start > end)
 860                 start = end;
 861
 862         return start;
 863 }
 864 #endif
 865
 866 /* This must be invoked after performing all of the necessary
 867  * memblock_set_node() calls for 'nid'.  We need to be able to get
 868  * correct data from get_pfn_range_for_nid().
 869  */
 870 static void __init allocate_node_data(int nid)
 871 {
 872         struct pglist_data *p;
 873         unsigned long start_pfn, end_pfn;
 874 #ifdef CONFIG_NEED_MULTIPLE_NODES
 875         unsigned long paddr;
 876
 877         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
 878         if (!paddr) {
 879                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 880                 prom_halt();
 881         }
 882         NODE_DATA(nid) = __va(paddr);
 883         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 884
 885         NODE_DATA(nid)->node_id = nid;
 886 #endif
 887
 888         p = NODE_DATA(nid);
 889
 890         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 891         p->node_start_pfn = start_pfn;
 892         p->node_spanned_pages = end_pfn - start_pfn;
 893 }
 894
 895 static void init_node_masks_nonnuma(void)
 896 {
 897         int i;
 898
 899         numadbg("Initializing tables for non-numa.\n");
 900
 901         node_masks[0].mask = node_masks[0].val = 0;
 902         num_node_masks = 1;
 903
 904         for (i = 0; i < NR_CPUS; i++)
 905                 numa_cpu_lookup_table[i] = 0;
 906
 907         cpumask_setall(&numa_cpumask_lookup_table[0]);
 908 }
 909
 910 #ifdef CONFIG_NEED_MULTIPLE_NODES
 911 struct pglist_data *node_data[MAX_NUMNODES];
 912
 913 EXPORT_SYMBOL(numa_cpu_lookup_table);
 914 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 915 EXPORT_SYMBOL(node_data);
 916
 917 struct mdesc_mlgroup {
 918         u64     node;
 919         u64     latency;
 920         u64     match;
 921         u64     mask;
 922 };
 923 static struct mdesc_mlgroup *mlgroups;
 924 static int num_mlgroups;
 925
 926 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 927                                    u32 cfg_handle)
 928 {
 929         u64 arc;
 930
 931         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 932                 u64 target = mdesc_arc_target(md, arc);
 933                 const u64 *val;
 934
 935                 val = mdesc_get_property(md, target,
 936                                          "cfg-handle", NULL);
 937                 if (val && *val == cfg_handle)
 938                         return 0;
 939         }
 940         return -ENODEV;
 941 }
 942
 943 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 944                                     u32 cfg_handle)
 945 {
 946         u64 arc, candidate, best_latency = ~(u64)0;
 947
 948         candidate = MDESC_NODE_NULL;
 949         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 950                 u64 target = mdesc_arc_target(md, arc);
 951                 const char *name = mdesc_node_name(md, target);
 952                 const u64 *val;
 953
 954                 if (strcmp(name, "pio-latency-group"))
 955                         continue;
 956
 957                 val = mdesc_get_property(md, target, "latency", NULL);
 958                 if (!val)
 959                         continue;
 960
 961                 if (*val < best_latency) {
 962                         candidate = target;
 963                         best_latency = *val;
 964                 }
 965         }
 966
 967         if (candidate == MDESC_NODE_NULL)
 968                 return -ENODEV;
 969
 970         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 971 }
 972
 973 int of_node_to_nid(struct device_node *dp)
 974 {
 975         const struct linux_prom64_registers *regs;
 976         struct mdesc_handle *md;
 977         u32 cfg_handle;
 978         int count, nid;
 979         u64 grp;
 980
 981         /* This is the right thing to do on currently supported
 982          * SUN4U NUMA platforms as well, as the PCI controller does
 983          * not sit behind any particular memory controller.
 984          */
 985         if (!mlgroups)
 986                 return -1;
 987
 988         regs = of_get_property(dp, "reg", NULL);
 989         if (!regs)
 990                 return -1;
 991
 992         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 993
 994         md = mdesc_grab();
 995
 996         count = 0;
 997         nid = -1;
 998         mdesc_for_each_node_by_name(md, grp, "group") {
 999                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1000                         nid = count;
1001                         break;
1002                 }
1003                 count++;
1004         }
1005
1006         mdesc_release(md);
1007
1008         return nid;
1009 }
1010
1011 static void __init add_node_ranges(void)
1012 {
1013         struct memblock_region *reg;
1014
1015         for_each_memblock(memory, reg) {
1016                 unsigned long size = reg->size;
1017                 unsigned long start, end;
1018
1019                 start = reg->base;
1020                 end = start + size;
1021                 while (start < end) {
1022                         unsigned long this_end;
1023                         int nid;
1024
1025                         this_end = memblock_nid_range(start, end, &nid);
1026
1027                         numadbg("Setting memblock NUMA node nid[%d] "
1028                                 "start[%lx] end[%lx]\n",
1029                                 nid, start, this_end);
1030
1031                         memblock_set_node(start, this_end - start,
1032                                           &memblock.memory, nid);
1033                         start = this_end;
1034                 }
1035         }
1036 }
1037
1038 static int __init grab_mlgroups(struct mdesc_handle *md)
1039 {
1040         unsigned long paddr;
1041         int count = 0;
1042         u64 node;
1043
1044         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1045                 count++;
1046         if (!count)
1047                 return -ENOENT;
1048
1049         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1050                           SMP_CACHE_BYTES);
1051         if (!paddr)
1052                 return -ENOMEM;
1053
1054         mlgroups = __va(paddr);
1055         num_mlgroups = count;
1056
1057         count = 0;
1058         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1059                 struct mdesc_mlgroup *m = &mlgroups[count++];
1060                 const u64 *val;
1061
1062                 m->node = node;
1063
1064                 val = mdesc_get_property(md, node, "latency", NULL);
1065                 m->latency = *val;
1066                 val = mdesc_get_property(md, node, "address-match", NULL);
1067                 m->match = *val;
1068                 val = mdesc_get_property(md, node, "address-mask", NULL);
1069                 m->mask = *val;
1070
1071                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1072                         "match[%llx] mask[%llx]\n",
1073                         count - 1, m->node, m->latency, m->match, m->mask);
1074         }
1075
1076         return 0;
1077 }
1078
1079 static int __init grab_mblocks(struct mdesc_handle *md)
1080 {
1081         unsigned long paddr;
1082         int count = 0;
1083         u64 node;
1084
1085         mdesc_for_each_node_by_name(md, node, "mblock")
1086                 count++;
1087         if (!count)
1088                 return -ENOENT;
1089
1090         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1091                           SMP_CACHE_BYTES);
1092         if (!paddr)
1093                 return -ENOMEM;
1094
1095         mblocks = __va(paddr);
1096         num_mblocks = count;
1097
1098         count = 0;
1099         mdesc_for_each_node_by_name(md, node, "mblock") {
1100                 struct mdesc_mblock *m = &mblocks[count++];
1101                 const u64 *val;
1102
1103                 val = mdesc_get_property(md, node, "base", NULL);
1104                 m->base = *val;
1105                 val = mdesc_get_property(md, node, "size", NULL);
1106                 m->size = *val;
1107                 val = mdesc_get_property(md, node,
1108                                          "address-congruence-offset", NULL);
1109
1110                 /* The address-congruence-offset property is optional.
1111                  * Explicity zero it be identifty this.
1112                  */
1113                 if (val)
1114                         m->offset = *val;
1115                 else
1116                         m->offset = 0UL;
1117
1118                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1119                         count - 1, m->base, m->size, m->offset);
1120         }
1121
1122         return 0;
1123 }
1124
1125 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1126                                                u64 grp, cpumask_t *mask)
1127 {
1128         u64 arc;
1129
1130         cpumask_clear(mask);
1131
1132         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1133                 u64 target = mdesc_arc_target(md, arc);
1134                 const char *name = mdesc_node_name(md, target);
1135                 const u64 *id;
1136
1137                 if (strcmp(name, "cpu"))
1138                         continue;
1139                 id = mdesc_get_property(md, target, "id", NULL);
1140                 if (*id < nr_cpu_ids)
1141                         cpumask_set_cpu(*id, mask);
1142         }
1143 }
1144
1145 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1146 {
1147         int i;
1148
1149         for (i = 0; i < num_mlgroups; i++) {
1150                 struct mdesc_mlgroup *m = &mlgroups[i];
1151                 if (m->node == node)
1152                         return m;
1153         }
1154         return NULL;
1155 }
1156
1157 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1158                                       int index)
1159 {
1160         struct mdesc_mlgroup *candidate = NULL;
1161         u64 arc, best_latency = ~(u64)0;
1162         struct node_mem_mask *n;
1163
1164         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1165                 u64 target = mdesc_arc_target(md, arc);
1166                 struct mdesc_mlgroup *m = find_mlgroup(target);
1167                 if (!m)
1168                         continue;
1169                 if (m->latency < best_latency) {
1170                         candidate = m;
1171                         best_latency = m->latency;
1172                 }
1173         }
1174         if (!candidate)
1175                 return -ENOENT;
1176
1177         if (num_node_masks != index) {
1178                 printk(KERN_ERR "Inconsistent NUMA state, "
1179                        "index[%d] != num_node_masks[%d]\n",
1180                        index, num_node_masks);
1181                 return -EINVAL;
1182         }
1183
1184         n = &node_masks[num_node_masks++];
1185
1186         n->mask = candidate->mask;
1187         n->val = candidate->match;
1188
1189         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1190                 index, n->mask, n->val, candidate->latency);
1191
1192         return 0;
1193 }
1194
1195 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1196                                          int index)
1197 {
1198         cpumask_t mask;
1199         int cpu;
1200
1201         numa_parse_mdesc_group_cpus(md, grp, &mask);
1202
1203         for_each_cpu(cpu, &mask)
1204                 numa_cpu_lookup_table[cpu] = index;
1205         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1206
1207         if (numa_debug) {
1208                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1209                 for_each_cpu(cpu, &mask)
1210                         printk("%d ", cpu);
1211                 printk("]\n");
1212         }
1213
1214         return numa_attach_mlgroup(md, grp, index);
1215 }
1216
1217 static int __init numa_parse_mdesc(void)
1218 {
1219         struct mdesc_handle *md = mdesc_grab();
1220         int i, err, count;
1221         u64 node;
1222
1223         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1224         if (node == MDESC_NODE_NULL) {
1225                 mdesc_release(md);
1226                 return -ENOENT;
1227         }
1228
1229         err = grab_mblocks(md);
1230         if (err < 0)
1231                 goto out;
1232
1233         err = grab_mlgroups(md);
1234         if (err < 0)
1235                 goto out;
1236
1237         count = 0;
1238         mdesc_for_each_node_by_name(md, node, "group") {
1239                 err = numa_parse_mdesc_group(md, node, count);
1240                 if (err < 0)
1241                         break;
1242                 count++;
1243         }
1244
1245         add_node_ranges();
1246
1247         for (i = 0; i < num_node_masks; i++) {
1248                 allocate_node_data(i);
1249                 node_set_online(i);
1250         }
1251
1252         err = 0;
1253 out:
1254         mdesc_release(md);
1255         return err;
1256 }
1257
1258 static int __init numa_parse_jbus(void)
1259 {
1260         unsigned long cpu, index;
1261
1262         /* NUMA node id is encoded in bits 36 and higher, and there is
1263          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1264          */
1265         index = 0;
1266         for_each_present_cpu(cpu) {
1267                 numa_cpu_lookup_table[cpu] = index;
1268                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1269                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1270                 node_masks[index].val = cpu << 36UL;
1271
1272                 index++;
1273         }
1274         num_node_masks = index;
1275
1276         add_node_ranges();
1277
1278         for (index = 0; index < num_node_masks; index++) {
1279                 allocate_node_data(index);
1280                 node_set_online(index);
1281         }
1282
1283         return 0;
1284 }
1285
1286 static int __init numa_parse_sun4u(void)
1287 {
1288         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1289                 unsigned long ver;
1290
1291                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1292                 if ((ver >> 32UL) == __JALAPENO_ID ||
1293                     (ver >> 32UL) == __SERRANO_ID)
1294                         return numa_parse_jbus();
1295         }
1296         return -1;
1297 }
1298
1299 static int __init bootmem_init_numa(void)
1300 {
1301         int err = -1;
1302
1303         numadbg("bootmem_init_numa()\n");
1304
1305         if (numa_enabled) {
1306                 if (tlb_type == hypervisor)
1307                         err = numa_parse_mdesc();
1308                 else
1309                         err = numa_parse_sun4u();
1310         }
1311         return err;
1312 }
1313
1314 #else
1315
1316 static int bootmem_init_numa(void)
1317 {
1318         return -1;
1319 }
1320
1321 #endif
1322
1323 static void __init bootmem_init_nonnuma(void)
1324 {
1325         unsigned long top_of_ram = memblock_end_of_DRAM();
1326         unsigned long total_ram = memblock_phys_mem_size();
1327
1328         numadbg("bootmem_init_nonnuma()\n");
1329
1330         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1331                top_of_ram, total_ram);
1332         printk(KERN_INFO "Memory hole size: %ldMB\n",
1333                (top_of_ram - total_ram) >> 20);
1334
1335         init_node_masks_nonnuma();
1336         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1337         allocate_node_data(0);
1338         node_set_online(0);
1339 }
1340
1341 static unsigned long __init bootmem_init(unsigned long phys_base)
1342 {
1343         unsigned long end_pfn;
1344
1345         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1346         max_pfn = max_low_pfn = end_pfn;
1347         min_low_pfn = (phys_base >> PAGE_SHIFT);
1348
1349         if (bootmem_init_numa() < 0)
1350                 bootmem_init_nonnuma();
1351
1352         /* Dump memblock with node info. */
1353         memblock_dump_all();
1354
1355         /* XXX cpu notifier XXX */
1356
1357         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1358         sparse_init();
1359
1360         return end_pfn;
1361 }
1362
1363 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1364 static int pall_ents __initdata;
1365
1366 #ifdef CONFIG_DEBUG_PAGEALLOC
1367 static unsigned long __ref kernel_map_range(unsigned long pstart,
1368                                             unsigned long pend, pgprot_t prot)
1369 {
1370         unsigned long vstart = PAGE_OFFSET + pstart;
1371         unsigned long vend = PAGE_OFFSET + pend;
1372         unsigned long alloc_bytes = 0UL;
1373
1374         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1375                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1376                             vstart, vend);
1377                 prom_halt();
1378         }
1379
1380         while (vstart < vend) {
1381                 unsigned long this_end, paddr = __pa(vstart);
1382                 pgd_t *pgd = pgd_offset_k(vstart);
1383                 pud_t *pud;
1384                 pmd_t *pmd;
1385                 pte_t *pte;
1386
1387                 pud = pud_offset(pgd, vstart);
1388                 if (pud_none(*pud)) {
1389                         pmd_t *new;
1390
1391                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1392                         alloc_bytes += PAGE_SIZE;
1393                         pud_populate(&init_mm, pud, new);
1394                 }
1395
1396                 pmd = pmd_offset(pud, vstart);
1397                 if (!pmd_present(*pmd)) {
1398                         pte_t *new;
1399
1400                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1401                         alloc_bytes += PAGE_SIZE;
1402                         pmd_populate_kernel(&init_mm, pmd, new);
1403                 }
1404
1405                 pte = pte_offset_kernel(pmd, vstart);
1406                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1407                 if (this_end > vend)
1408                         this_end = vend;
1409
1410                 while (vstart < this_end) {
1411                         pte_val(*pte) = (paddr | pgprot_val(prot));
1412
1413                         vstart += PAGE_SIZE;
1414                         paddr += PAGE_SIZE;
1415                         pte++;
1416                 }
1417         }
1418
1419         return alloc_bytes;
1420 }
1421
1422 extern unsigned int kvmap_linear_patch[1];
1423 #endif /* CONFIG_DEBUG_PAGEALLOC */
1424
1425 static void __init kpte_set_val(unsigned long index, unsigned long val)
1426 {
1427         unsigned long *ptr = kpte_linear_bitmap;
1428
1429         val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1430         ptr += (index / (BITS_PER_LONG / 2));
1431
1432         *ptr |= val;
1433 }
1434
1435 static const unsigned long kpte_shift_min = 28; /* 256MB */
1436 static const unsigned long kpte_shift_max = 34; /* 16GB */
1437 static const unsigned long kpte_shift_incr = 3;
1438
1439 static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1440                                            unsigned long shift)
1441 {
1442         unsigned long size = (1UL << shift);
1443         unsigned long mask = (size - 1UL);
1444         unsigned long remains = end - start;
1445         unsigned long val;
1446
1447         if (remains < size || (start & mask))
1448                 return start;
1449
1450         /* VAL maps:
1451          *
1452          *      shift 28 --> kern_linear_pte_xor index 1
1453          *      shift 31 --> kern_linear_pte_xor index 2
1454          *      shift 34 --> kern_linear_pte_xor index 3
1455          */
1456         val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1457
1458         remains &= ~mask;
1459         if (shift != kpte_shift_max)
1460                 remains = size;
1461
1462         while (remains) {
1463                 unsigned long index = start >> kpte_shift_min;
1464
1465                 kpte_set_val(index, val);
1466
1467                 start += 1UL << kpte_shift_min;
1468                 remains -= 1UL << kpte_shift_min;
1469         }
1470
1471         return start;
1472 }
1473
1474 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1475 {
1476         unsigned long smallest_size, smallest_mask;
1477         unsigned long s;
1478
1479         smallest_size = (1UL << kpte_shift_min);
1480         smallest_mask = (smallest_size - 1UL);
1481
1482         while (start < end) {
1483                 unsigned long orig_start = start;
1484
1485                 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1486                         start = kpte_mark_using_shift(start, end, s);
1487
1488                         if (start != orig_start)
1489                                 break;
1490                 }
1491
1492                 if (start == orig_start)
1493                         start = (start + smallest_size) & ~smallest_mask;
1494         }
1495 }
1496
1497 static void __init init_kpte_bitmap(void)
1498 {
1499         unsigned long i;
1500
1501         for (i = 0; i < pall_ents; i++) {
1502                 unsigned long phys_start, phys_end;
1503
1504                 phys_start = pall[i].phys_addr;
1505                 phys_end = phys_start + pall[i].reg_size;
1506
1507                 mark_kpte_bitmap(phys_start, phys_end);
1508         }
1509 }
1510
1511 static void __init kernel_physical_mapping_init(void)
1512 {
1513 #ifdef CONFIG_DEBUG_PAGEALLOC
1514         unsigned long i, mem_alloced = 0UL;
1515
1516         for (i = 0; i < pall_ents; i++) {
1517                 unsigned long phys_start, phys_end;
1518
1519                 phys_start = pall[i].phys_addr;
1520                 phys_end = phys_start + pall[i].reg_size;
1521
1522                 mem_alloced += kernel_map_range(phys_start, phys_end,
1523                                                 PAGE_KERNEL);
1524         }
1525
1526         printk("Allocated %ld bytes for kernel page tables.\n",
1527                mem_alloced);
1528
1529         kvmap_linear_patch[0] = 0x01000000; /* nop */
1530         flushi(&kvmap_linear_patch[0]);
1531
1532         __flush_tlb_all();
1533 #endif
1534 }
1535
1536 #ifdef CONFIG_DEBUG_PAGEALLOC
1537 void kernel_map_pages(struct page *page, int numpages, int enable)
1538 {
1539         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1540         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1541
1542         kernel_map_range(phys_start, phys_end,
1543                          (enable ? PAGE_KERNEL : __pgprot(0)));
1544
1545         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1546                                PAGE_OFFSET + phys_end);
1547
1548         /* we should perform an IPI and flush all tlbs,
1549          * but that can deadlock->flush only current cpu.
1550          */
1551         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1552                                  PAGE_OFFSET + phys_end);
1553 }
1554 #endif
1555
1556 unsigned long __init find_ecache_flush_span(unsigned long size)
1557 {
1558         int i;
1559
1560         for (i = 0; i < pavail_ents; i++) {
1561                 if (pavail[i].reg_size >= size)
1562                         return pavail[i].phys_addr;
1563         }
1564
1565         return ~0UL;
1566 }
1567
1568 unsigned long PAGE_OFFSET;
1569 EXPORT_SYMBOL(PAGE_OFFSET);
1570
1571 static void __init page_offset_shift_patch_one(unsigned int *insn, unsigned long phys_bits)
1572 {
1573         unsigned long final_shift;
1574         unsigned int val = *insn;
1575         unsigned int cnt;
1576
1577         /* We are patching in ilog2(max_supported_phys_address), and
1578          * we are doing so in a manner similar to a relocation addend.
1579          * That is, we are adding the shift value to whatever value
1580          * is in the shift instruction count field already.
1581          */
1582         cnt = (val & 0x3f);
1583         val &= ~0x3f;
1584
1585         /* If we are trying to shift >= 64 bits, clear the destination
1586          * register.  This can happen when phys_bits ends up being equal
1587          * to MAX_PHYS_ADDRESS_BITS.
1588          */
1589         final_shift = (cnt + (64 - phys_bits));
1590         if (final_shift >= 64) {
1591                 unsigned int rd = (val >> 25) & 0x1f;
1592
1593                 val = 0x80100000 | (rd << 25);
1594         } else {
1595                 val |= final_shift;
1596         }
1597         *insn = val;
1598
1599         __asm__ __volatile__("flush     %0"
1600                              : /* no outputs */
1601                              : "r" (insn));
1602 }
1603
1604 static void __init page_offset_shift_patch(unsigned long phys_bits)
1605 {
1606         extern unsigned int __page_offset_shift_patch;
1607         extern unsigned int __page_offset_shift_patch_end;
1608         unsigned int *p;
1609
1610         p = &__page_offset_shift_patch;
1611         while (p < &__page_offset_shift_patch_end) {
1612                 unsigned int *insn = (unsigned int *)(unsigned long)*p;
1613
1614                 page_offset_shift_patch_one(insn, phys_bits);
1615
1616                 p++;
1617         }
1618 }
1619
1620 static void __init setup_page_offset(void)
1621 {
1622         unsigned long max_phys_bits = 40;
1623
1624         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1625                 max_phys_bits = 42;
1626         } else if (tlb_type == hypervisor) {
1627                 switch (sun4v_chip_type) {
1628                 case SUN4V_CHIP_NIAGARA1:
1629                 case SUN4V_CHIP_NIAGARA2:
1630                         max_phys_bits = 39;
1631                         break;
1632                 case SUN4V_CHIP_NIAGARA3:
1633                         max_phys_bits = 43;
1634                         break;
1635                 case SUN4V_CHIP_NIAGARA4:
1636                 case SUN4V_CHIP_NIAGARA5:
1637                 case SUN4V_CHIP_SPARC64X:
1638                 default:
1639                         max_phys_bits = 47;
1640                         break;
1641                 }
1642         }
1643
1644         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1645                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1646                             max_phys_bits);
1647                 prom_halt();
1648         }
1649
1650         PAGE_OFFSET = PAGE_OFFSET_BY_BITS(max_phys_bits);
1651
1652         pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1653                 PAGE_OFFSET, max_phys_bits);
1654
1655         page_offset_shift_patch(max_phys_bits);
1656 }
1657
1658 static void __init tsb_phys_patch(void)
1659 {
1660         struct tsb_ldquad_phys_patch_entry *pquad;
1661         struct tsb_phys_patch_entry *p;
1662
1663         pquad = &__tsb_ldquad_phys_patch;
1664         while (pquad < &__tsb_ldquad_phys_patch_end) {
1665                 unsigned long addr = pquad->addr;
1666
1667                 if (tlb_type == hypervisor)
1668                         *(unsigned int *) addr = pquad->sun4v_insn;
1669                 else
1670                         *(unsigned int *) addr = pquad->sun4u_insn;
1671                 wmb();
1672                 __asm__ __volatile__("flush     %0"
1673                                      : /* no outputs */
1674                                      : "r" (addr));
1675
1676                 pquad++;
1677         }
1678
1679         p = &__tsb_phys_patch;
1680         while (p < &__tsb_phys_patch_end) {
1681                 unsigned long addr = p->addr;
1682
1683                 *(unsigned int *) addr = p->insn;
1684                 wmb();
1685                 __asm__ __volatile__("flush     %0"
1686                                      : /* no outputs */
1687                                      : "r" (addr));
1688
1689                 p++;
1690         }
1691 }
1692
1693 /* Don't mark as init, we give this to the Hypervisor.  */
1694 #ifndef CONFIG_DEBUG_PAGEALLOC
1695 #define NUM_KTSB_DESCR  2
1696 #else
1697 #define NUM_KTSB_DESCR  1
1698 #endif
1699 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1700 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1701
1702 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1703 {
1704         pa >>= KTSB_PHYS_SHIFT;
1705
1706         while (start < end) {
1707                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1708
1709                 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1710                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1711
1712                 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1713                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1714
1715                 start++;
1716         }
1717 }
1718
1719 static void ktsb_phys_patch(void)
1720 {
1721         extern unsigned int __swapper_tsb_phys_patch;
1722         extern unsigned int __swapper_tsb_phys_patch_end;
1723         unsigned long ktsb_pa;
1724
1725         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1726         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1727                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1728 #ifndef CONFIG_DEBUG_PAGEALLOC
1729         {
1730         extern unsigned int __swapper_4m_tsb_phys_patch;
1731         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1732         ktsb_pa = (kern_base +
1733                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1734         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1735                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1736         }
1737 #endif
1738 }
1739
1740 static void __init sun4v_ktsb_init(void)
1741 {
1742         unsigned long ktsb_pa;
1743
1744         /* First KTSB for PAGE_SIZE mappings.  */
1745         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1746
1747         switch (PAGE_SIZE) {
1748         case 8 * 1024:
1749         default:
1750                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1751                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1752                 break;
1753
1754         case 64 * 1024:
1755                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1756                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1757                 break;
1758
1759         case 512 * 1024:
1760                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1761                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1762                 break;
1763
1764         case 4 * 1024 * 1024:
1765                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1766                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1767                 break;
1768         }
1769
1770         ktsb_descr[0].assoc = 1;
1771         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1772         ktsb_descr[0].ctx_idx = 0;
1773         ktsb_descr[0].tsb_base = ktsb_pa;
1774         ktsb_descr[0].resv = 0;
1775
1776 #ifndef CONFIG_DEBUG_PAGEALLOC
1777         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1778         ktsb_pa = (kern_base +
1779                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1780
1781         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1782         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1783                                     HV_PGSZ_MASK_256MB |
1784                                     HV_PGSZ_MASK_2GB |
1785                                     HV_PGSZ_MASK_16GB) &
1786                                    cpu_pgsz_mask);
1787         ktsb_descr[1].assoc = 1;
1788         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1789         ktsb_descr[1].ctx_idx = 0;
1790         ktsb_descr[1].tsb_base = ktsb_pa;
1791         ktsb_descr[1].resv = 0;
1792 #endif
1793 }
1794
1795 void sun4v_ktsb_register(void)
1796 {
1797         unsigned long pa, ret;
1798
1799         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1800
1801         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1802         if (ret != 0) {
1803                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1804                             "errors with %lx\n", pa, ret);
1805                 prom_halt();
1806         }
1807 }
1808
1809 static void __init sun4u_linear_pte_xor_finalize(void)
1810 {
1811 #ifndef CONFIG_DEBUG_PAGEALLOC
1812         /* This is where we would add Panther support for
1813          * 32MB and 256MB pages.
1814          */
1815 #endif
1816 }
1817
1818 static void __init sun4v_linear_pte_xor_finalize(void)
1819 {
1820 #ifndef CONFIG_DEBUG_PAGEALLOC
1821         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1822                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1823                         PAGE_OFFSET;
1824                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1825                                            _PAGE_P_4V | _PAGE_W_4V);
1826         } else {
1827                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1828         }
1829
1830         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1831                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1832                         PAGE_OFFSET;
1833                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1834                                            _PAGE_P_4V | _PAGE_W_4V);
1835         } else {
1836                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1837         }
1838
1839         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1840                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1841                         PAGE_OFFSET;
1842                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1843                                            _PAGE_P_4V | _PAGE_W_4V);
1844         } else {
1845                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1846         }
1847 #endif
1848 }
1849
1850 /* paging_init() sets up the page tables */
1851
1852 static unsigned long last_valid_pfn;
1853 pgd_t swapper_pg_dir[PTRS_PER_PGD];
1854
1855 static void sun4u_pgprot_init(void);
1856 static void sun4v_pgprot_init(void);
1857
1858 void __init paging_init(void)
1859 {
1860         unsigned long end_pfn, shift, phys_base;
1861         unsigned long real_end, i;
1862         int node;
1863
1864         setup_page_offset();
1865
1866         /* These build time checkes make sure that the dcache_dirty_cpu()
1867          * page->flags usage will work.
1868          *
1869          * When a page gets marked as dcache-dirty, we store the
1870          * cpu number starting at bit 32 in the page->flags.  Also,
1871          * functions like clear_dcache_dirty_cpu use the cpu mask
1872          * in 13-bit signed-immediate instruction fields.
1873          */
1874
1875         /*
1876          * Page flags must not reach into upper 32 bits that are used
1877          * for the cpu number
1878          */
1879         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1880
1881         /*
1882          * The bit fields placed in the high range must not reach below
1883          * the 32 bit boundary. Otherwise we cannot place the cpu field
1884          * at the 32 bit boundary.
1885          */
1886         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1887                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1888
1889         BUILD_BUG_ON(NR_CPUS > 4096);
1890
1891         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
1892         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1893
1894         /* Invalidate both kernel TSBs.  */
1895         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1896 #ifndef CONFIG_DEBUG_PAGEALLOC
1897         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1898 #endif
1899
1900         if (tlb_type == hypervisor)
1901                 sun4v_pgprot_init();
1902         else
1903                 sun4u_pgprot_init();
1904
1905         if (tlb_type == cheetah_plus ||
1906             tlb_type == hypervisor) {
1907                 tsb_phys_patch();
1908                 ktsb_phys_patch();
1909         }
1910
1911         if (tlb_type == hypervisor)
1912                 sun4v_patch_tlb_handlers();
1913
1914         /* Find available physical memory...
1915          *
1916          * Read it twice in order to work around a bug in openfirmware.
1917          * The call to grab this table itself can cause openfirmware to
1918          * allocate memory, which in turn can take away some space from
1919          * the list of available memory.  Reading it twice makes sure
1920          * we really do get the final value.
1921          */
1922         read_obp_translations();
1923         read_obp_memory("reg", &pall[0], &pall_ents);
1924         read_obp_memory("available", &pavail[0], &pavail_ents);
1925         read_obp_memory("available", &pavail[0], &pavail_ents);
1926
1927         phys_base = 0xffffffffffffffffUL;
1928         for (i = 0; i < pavail_ents; i++) {
1929                 phys_base = min(phys_base, pavail[i].phys_addr);
1930                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1931         }
1932
1933         memblock_reserve(kern_base, kern_size);
1934
1935         find_ramdisk(phys_base);
1936
1937         memblock_enforce_memory_limit(cmdline_memory_size);
1938
1939         memblock_allow_resize();
1940         memblock_dump_all();
1941
1942         set_bit(0, mmu_context_bmap);
1943
1944         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1945
1946         real_end = (unsigned long)_end;
1947         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
1948         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1949                num_kernel_image_mappings);
1950
1951         /* Set kernel pgd to upper alias so physical page computations
1952          * work.
1953          */
1954         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1955
1956         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1957
1958         /* Now can init the kernel/bad page tables. */
1959         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1960                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1961
1962         inherit_prom_mappings();
1963
1964         init_kpte_bitmap();
1965
1966         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1967         setup_tba();
1968
1969         __flush_tlb_all();
1970
1971         prom_build_devicetree();
1972         of_populate_present_mask();
1973 #ifndef CONFIG_SMP
1974         of_fill_in_cpu_data();
1975 #endif
1976
1977         if (tlb_type == hypervisor) {
1978                 sun4v_mdesc_init();
1979                 mdesc_populate_present_mask(cpu_all_mask);
1980 #ifndef CONFIG_SMP
1981                 mdesc_fill_in_cpu_data(cpu_all_mask);
1982 #endif
1983                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
1984
1985                 sun4v_linear_pte_xor_finalize();
1986
1987                 sun4v_ktsb_init();
1988                 sun4v_ktsb_register();
1989         } else {
1990                 unsigned long impl, ver;
1991
1992                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1993                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1994
1995                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1996                 impl = ((ver >> 32) & 0xffff);
1997                 if (impl == PANTHER_IMPL)
1998                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1999                                           HV_PGSZ_MASK_256MB);
2000
2001                 sun4u_linear_pte_xor_finalize();
2002         }
2003
2004         /* Flush the TLBs and the 4M TSB so that the updated linear
2005          * pte XOR settings are realized for all mappings.
2006          */
2007         __flush_tlb_all();
2008 #ifndef CONFIG_DEBUG_PAGEALLOC
2009         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2010 #endif
2011         __flush_tlb_all();
2012
2013         /* Setup bootmem... */
2014         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2015
2016         /* Once the OF device tree and MDESC have been setup, we know
2017          * the list of possible cpus.  Therefore we can allocate the
2018          * IRQ stacks.
2019          */
2020         for_each_possible_cpu(i) {
2021                 node = cpu_to_node(i);
2022
2023                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2024                                                         THREAD_SIZE,
2025                                                         THREAD_SIZE, 0);
2026                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2027                                                         THREAD_SIZE,
2028                                                         THREAD_SIZE, 0);
2029         }
2030
2031         kernel_physical_mapping_init();
2032
2033         {
2034                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2035
2036                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2037
2038                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2039
2040                 free_area_init_nodes(max_zone_pfns);
2041         }
2042
2043         printk("Booting Linux...\n");
2044 }
2045
2046 int page_in_phys_avail(unsigned long paddr)
2047 {
2048         int i;
2049
2050         paddr &= PAGE_MASK;
2051
2052         for (i = 0; i < pavail_ents; i++) {
2053                 unsigned long start, end;
2054
2055                 start = pavail[i].phys_addr;
2056                 end = start + pavail[i].reg_size;
2057
2058                 if (paddr >= start && paddr < end)
2059                         return 1;
2060         }
2061         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2062                 return 1;
2063 #ifdef CONFIG_BLK_DEV_INITRD
2064         if (paddr >= __pa(initrd_start) &&
2065             paddr < __pa(PAGE_ALIGN(initrd_end)))
2066                 return 1;
2067 #endif
2068
2069         return 0;
2070 }
2071
2072 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
2073 static int pavail_rescan_ents __initdata;
2074
2075 /* Certain OBP calls, such as fetching "available" properties, can
2076  * claim physical memory.  So, along with initializing the valid
2077  * address bitmap, what we do here is refetch the physical available
2078  * memory list again, and make sure it provides at least as much
2079  * memory as 'pavail' does.
2080  */
2081 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
2082 {
2083         int i;
2084
2085         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
2086
2087         for (i = 0; i < pavail_ents; i++) {
2088                 unsigned long old_start, old_end;
2089
2090                 old_start = pavail[i].phys_addr;
2091                 old_end = old_start + pavail[i].reg_size;
2092                 while (old_start < old_end) {
2093                         int n;
2094
2095                         for (n = 0; n < pavail_rescan_ents; n++) {
2096                                 unsigned long new_start, new_end;
2097
2098                                 new_start = pavail_rescan[n].phys_addr;
2099                                 new_end = new_start +
2100                                         pavail_rescan[n].reg_size;
2101
2102                                 if (new_start <= old_start &&
2103                                     new_end >= (old_start + PAGE_SIZE)) {
2104                                         set_bit(old_start >> ILOG2_4MB, bitmap);
2105                                         goto do_next_page;
2106                                 }
2107                         }
2108
2109                         prom_printf("mem_init: Lost memory in pavail\n");
2110                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2111                                     pavail[i].phys_addr,
2112                                     pavail[i].reg_size);
2113                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2114                                     pavail_rescan[i].phys_addr,
2115                                     pavail_rescan[i].reg_size);
2116                         prom_printf("mem_init: Cannot continue, aborting.\n");
2117                         prom_halt();
2118
2119                 do_next_page:
2120                         old_start += PAGE_SIZE;
2121                 }
2122         }
2123 }
2124
2125 static void __init patch_tlb_miss_handler_bitmap(void)
2126 {
2127         extern unsigned int valid_addr_bitmap_insn[];
2128         extern unsigned int valid_addr_bitmap_patch[];
2129
2130         valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2131         mb();
2132         valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2133         flushi(&valid_addr_bitmap_insn[0]);
2134 }
2135
2136 static void __init register_page_bootmem_info(void)
2137 {
2138 #ifdef CONFIG_NEED_MULTIPLE_NODES
2139         int i;
2140
2141         for_each_online_node(i)
2142                 if (NODE_DATA(i)->node_spanned_pages)
2143                         register_page_bootmem_info_node(NODE_DATA(i));
2144 #endif
2145 }
2146 void __init mem_init(void)
2147 {
2148         unsigned long addr, last;
2149
2150         addr = PAGE_OFFSET + kern_base;
2151         last = PAGE_ALIGN(kern_size) + addr;
2152         while (addr < last) {
2153                 set_bit(__pa(addr) >> ILOG2_4MB, sparc64_valid_addr_bitmap);
2154                 addr += PAGE_SIZE;
2155         }
2156
2157         setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2158         patch_tlb_miss_handler_bitmap();
2159
2160         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2161
2162         register_page_bootmem_info();
2163         free_all_bootmem();
2164
2165         /*
2166          * Set up the zero page, mark it reserved, so that page count
2167          * is not manipulated when freeing the page from user ptes.
2168          */
2169         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2170         if (mem_map_zero == NULL) {
2171                 prom_printf("paging_init: Cannot alloc zero page.\n");
2172                 prom_halt();
2173         }
2174         mark_page_reserved(mem_map_zero);
2175
2176         mem_init_print_info(NULL);
2177
2178         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2179                 cheetah_ecache_flush_init();
2180 }
2181
2182 void free_initmem(void)
2183 {
2184         unsigned long addr, initend;
2185         int do_free = 1;
2186
2187         /* If the physical memory maps were trimmed by kernel command
2188          * line options, don't even try freeing this initmem stuff up.
2189          * The kernel image could have been in the trimmed out region
2190          * and if so the freeing below will free invalid page structs.
2191          */
2192         if (cmdline_memory_size)
2193                 do_free = 0;
2194
2195         /*
2196          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2197          */
2198         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2199         initend = (unsigned long)(__init_end) & PAGE_MASK;
2200         for (; addr < initend; addr += PAGE_SIZE) {
2201                 unsigned long page;
2202
2203                 page = (addr +
2204                         ((unsigned long) __va(kern_base)) -
2205                         ((unsigned long) KERNBASE));
2206                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2207
2208                 if (do_free)
2209                         free_reserved_page(virt_to_page(page));
2210         }
2211 }
2212
2213 #ifdef CONFIG_BLK_DEV_INITRD
2214 void free_initrd_mem(unsigned long start, unsigned long end)
2215 {
2216         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2217                            "initrd");
2218 }
2219 #endif
2220
2221 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2222 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2223 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2224 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2225 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2226 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2227
2228 pgprot_t PAGE_KERNEL __read_mostly;
2229 EXPORT_SYMBOL(PAGE_KERNEL);
2230
2231 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2232 pgprot_t PAGE_COPY __read_mostly;
2233
2234 pgprot_t PAGE_SHARED __read_mostly;
2235 EXPORT_SYMBOL(PAGE_SHARED);
2236
2237 unsigned long pg_iobits __read_mostly;
2238
2239 unsigned long _PAGE_IE __read_mostly;
2240 EXPORT_SYMBOL(_PAGE_IE);
2241
2242 unsigned long _PAGE_E __read_mostly;
2243 EXPORT_SYMBOL(_PAGE_E);
2244
2245 unsigned long _PAGE_CACHE __read_mostly;
2246 EXPORT_SYMBOL(_PAGE_CACHE);
2247
2248 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2249 unsigned long vmemmap_table[VMEMMAP_SIZE];
2250
2251 static long __meminitdata addr_start, addr_end;
2252 static int __meminitdata node_start;
2253
2254 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2255                                int node)
2256 {
2257         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2258         unsigned long phys_end = (vend - VMEMMAP_BASE);
2259         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2260         unsigned long end = VMEMMAP_ALIGN(phys_end);
2261         unsigned long pte_base;
2262
2263         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2264                     _PAGE_CP_4U | _PAGE_CV_4U |
2265                     _PAGE_P_4U | _PAGE_W_4U);
2266         if (tlb_type == hypervisor)
2267                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2268                             _PAGE_CP_4V | _PAGE_CV_4V |
2269                             _PAGE_P_4V | _PAGE_W_4V);
2270
2271         for (; addr < end; addr += VMEMMAP_CHUNK) {
2272                 unsigned long *vmem_pp =
2273                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2274                 void *block;
2275
2276                 if (!(*vmem_pp & _PAGE_VALID)) {
2277                         block = vmemmap_alloc_block(1UL << ILOG2_4MB, node);
2278                         if (!block)
2279                                 return -ENOMEM;
2280
2281                         *vmem_pp = pte_base | __pa(block);
2282
2283                         /* check to see if we have contiguous blocks */
2284                         if (addr_end != addr || node_start != node) {
2285                                 if (addr_start)
2286                                         printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2287                                                addr_start, addr_end-1, node_start);
2288                                 addr_start = addr;
2289                                 node_start = node;
2290                         }
2291                         addr_end = addr + VMEMMAP_CHUNK;
2292                 }
2293         }
2294         return 0;
2295 }
2296
2297 void __meminit vmemmap_populate_print_last(void)
2298 {
2299         if (addr_start) {
2300                 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2301                        addr_start, addr_end-1, node_start);
2302                 addr_start = 0;
2303                 addr_end = 0;
2304                 node_start = 0;
2305         }
2306 }
2307
2308 void vmemmap_free(unsigned long start, unsigned long end)
2309 {
2310 }
2311
2312 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2313
2314 static void prot_init_common(unsigned long page_none,
2315                              unsigned long page_shared,
2316                              unsigned long page_copy,
2317                              unsigned long page_readonly,
2318                              unsigned long page_exec_bit)
2319 {
2320         PAGE_COPY = __pgprot(page_copy);
2321         PAGE_SHARED = __pgprot(page_shared);
2322
2323         protection_map[0x0] = __pgprot(page_none);
2324         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2325         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2326         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2327         protection_map[0x4] = __pgprot(page_readonly);
2328         protection_map[0x5] = __pgprot(page_readonly);
2329         protection_map[0x6] = __pgprot(page_copy);
2330         protection_map[0x7] = __pgprot(page_copy);
2331         protection_map[0x8] = __pgprot(page_none);
2332         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2333         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2334         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2335         protection_map[0xc] = __pgprot(page_readonly);
2336         protection_map[0xd] = __pgprot(page_readonly);
2337         protection_map[0xe] = __pgprot(page_shared);
2338         protection_map[0xf] = __pgprot(page_shared);
2339 }
2340
2341 static void __init sun4u_pgprot_init(void)
2342 {
2343         unsigned long page_none, page_shared, page_copy, page_readonly;
2344         unsigned long page_exec_bit;
2345         int i;
2346
2347         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2348                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2349                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2350                                 _PAGE_EXEC_4U);
2351         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2352                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2353                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2354                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2355
2356         _PAGE_IE = _PAGE_IE_4U;
2357         _PAGE_E = _PAGE_E_4U;
2358         _PAGE_CACHE = _PAGE_CACHE_4U;
2359
2360         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2361                      __ACCESS_BITS_4U | _PAGE_E_4U);
2362
2363 #ifdef CONFIG_DEBUG_PAGEALLOC
2364         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2365 #else
2366         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2367                 PAGE_OFFSET;
2368 #endif
2369         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2370                                    _PAGE_P_4U | _PAGE_W_4U);
2371
2372         for (i = 1; i < 4; i++)
2373                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2374
2375         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2376                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2377                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2378
2379
2380         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2381         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2382                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2383         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2384                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2385         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2386                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2387
2388         page_exec_bit = _PAGE_EXEC_4U;
2389
2390         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2391                          page_exec_bit);
2392 }
2393
2394 static void __init sun4v_pgprot_init(void)
2395 {
2396         unsigned long page_none, page_shared, page_copy, page_readonly;
2397         unsigned long page_exec_bit;
2398         int i;
2399
2400         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2401                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2402                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2403                                 _PAGE_EXEC_4V);
2404         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2405
2406         _PAGE_IE = _PAGE_IE_4V;
2407         _PAGE_E = _PAGE_E_4V;
2408         _PAGE_CACHE = _PAGE_CACHE_4V;
2409
2410 #ifdef CONFIG_DEBUG_PAGEALLOC
2411         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2412 #else
2413         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2414                 PAGE_OFFSET;
2415 #endif
2416         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2417                                    _PAGE_P_4V | _PAGE_W_4V);
2418
2419         for (i = 1; i < 4; i++)
2420                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2421
2422         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2423                      __ACCESS_BITS_4V | _PAGE_E_4V);
2424
2425         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2426                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2427                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2428                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2429
2430         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2431         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2432                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2433         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2434                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2435         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2436                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2437
2438         page_exec_bit = _PAGE_EXEC_4V;
2439
2440         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2441                          page_exec_bit);
2442 }
2443
2444 unsigned long pte_sz_bits(unsigned long sz)
2445 {
2446         if (tlb_type == hypervisor) {
2447                 switch (sz) {
2448                 case 8 * 1024:
2449                 default:
2450                         return _PAGE_SZ8K_4V;
2451                 case 64 * 1024:
2452                         return _PAGE_SZ64K_4V;
2453                 case 512 * 1024:
2454                         return _PAGE_SZ512K_4V;
2455                 case 4 * 1024 * 1024:
2456                         return _PAGE_SZ4MB_4V;
2457                 }
2458         } else {
2459                 switch (sz) {
2460                 case 8 * 1024:
2461                 default:
2462                         return _PAGE_SZ8K_4U;
2463                 case 64 * 1024:
2464                         return _PAGE_SZ64K_4U;
2465                 case 512 * 1024:
2466                         return _PAGE_SZ512K_4U;
2467                 case 4 * 1024 * 1024:
2468                         return _PAGE_SZ4MB_4U;
2469                 }
2470         }
2471 }
2472
2473 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2474 {
2475         pte_t pte;
2476
2477         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2478         pte_val(pte) |= (((unsigned long)space) << 32);
2479         pte_val(pte) |= pte_sz_bits(page_size);
2480
2481         return pte;
2482 }
2483
2484 static unsigned long kern_large_tte(unsigned long paddr)
2485 {
2486         unsigned long val;
2487
2488         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2489                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2490                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2491         if (tlb_type == hypervisor)
2492                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2493                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2494                        _PAGE_EXEC_4V | _PAGE_W_4V);
2495
2496         return val | paddr;
2497 }
2498
2499 /* If not locked, zap it. */
2500 void __flush_tlb_all(void)
2501 {
2502         unsigned long pstate;
2503         int i;
2504
2505         __asm__ __volatile__("flushw\n\t"
2506                              "rdpr      %%pstate, %0\n\t"
2507                              "wrpr      %0, %1, %%pstate"
2508                              : "=r" (pstate)
2509                              : "i" (PSTATE_IE));
2510         if (tlb_type == hypervisor) {
2511                 sun4v_mmu_demap_all();
2512         } else if (tlb_type == spitfire) {
2513                 for (i = 0; i < 64; i++) {
2514                         /* Spitfire Errata #32 workaround */
2515                         /* NOTE: Always runs on spitfire, so no
2516                          *       cheetah+ page size encodings.
2517                          */
2518                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2519                                              "flush     %%g6"
2520                                              : /* No outputs */
2521                                              : "r" (0),
2522                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2523
2524                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2525                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2526                                                      "membar #Sync"
2527                                                      : /* no outputs */
2528                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2529                                 spitfire_put_dtlb_data(i, 0x0UL);
2530                         }
2531
2532                         /* Spitfire Errata #32 workaround */
2533                         /* NOTE: Always runs on spitfire, so no
2534                          *       cheetah+ page size encodings.
2535                          */
2536                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2537                                              "flush     %%g6"
2538                                              : /* No outputs */
2539                                              : "r" (0),
2540                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2541
2542                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2543                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2544                                                      "membar #Sync"
2545                                                      : /* no outputs */
2546                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2547                                 spitfire_put_itlb_data(i, 0x0UL);
2548                         }
2549                 }
2550         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2551                 cheetah_flush_dtlb_all();
2552                 cheetah_flush_itlb_all();
2553         }
2554         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2555                              : : "r" (pstate));
2556 }
2557
2558 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2559                             unsigned long address)
2560 {
2561         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2562                                        __GFP_REPEAT | __GFP_ZERO);
2563         pte_t *pte = NULL;
2564
2565         if (page)
2566                 pte = (pte_t *) page_address(page);
2567
2568         return pte;
2569 }
2570
2571 pgtable_t pte_alloc_one(struct mm_struct *mm,
2572                         unsigned long address)
2573 {
2574         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2575                                        __GFP_REPEAT | __GFP_ZERO);
2576         if (!page)
2577                 return NULL;
2578         if (!pgtable_page_ctor(page)) {
2579                 free_hot_cold_page(page, 0);
2580                 return NULL;
2581         }
2582         return (pte_t *) page_address(page);
2583 }
2584
2585 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2586 {
2587         free_page((unsigned long)pte);
2588 }
2589
2590 static void __pte_free(pgtable_t pte)
2591 {
2592         struct page *page = virt_to_page(pte);
2593
2594         pgtable_page_dtor(page);
2595         __free_page(page);
2596 }
2597
2598 void pte_free(struct mm_struct *mm, pgtable_t pte)
2599 {
2600         __pte_free(pte);
2601 }
2602
2603 void pgtable_free(void *table, bool is_page)
2604 {
2605         if (is_page)
2606                 __pte_free(table);
2607         else
2608                 kmem_cache_free(pgtable_cache, table);
2609 }
2610
2611 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2612 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2613                           pmd_t *pmd)
2614 {
2615         unsigned long pte, flags;
2616         struct mm_struct *mm;
2617         pmd_t entry = *pmd;
2618
2619         if (!pmd_large(entry) || !pmd_young(entry))
2620                 return;
2621
2622         pte = pmd_val(entry);
2623
2624         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2625         if (!(pte & _PAGE_VALID))
2626                 return;
2627
2628         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2629         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2630
2631         mm = vma->vm_mm;
2632
2633         spin_lock_irqsave(&mm->context.lock, flags);
2634
2635         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2636                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2637                                         addr, pte);
2638
2639         spin_unlock_irqrestore(&mm->context.lock, flags);
2640 }
2641 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2642
2643 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2644 static void context_reload(void *__data)
2645 {
2646         struct mm_struct *mm = __data;
2647
2648         if (mm == current->mm)
2649                 load_secondary_context(mm);
2650 }
2651
2652 void hugetlb_setup(struct pt_regs *regs)
2653 {
2654         struct mm_struct *mm = current->mm;
2655         struct tsb_config *tp;
2656
2657         if (in_atomic() || !mm) {
2658                 const struct exception_table_entry *entry;
2659
2660                 entry = search_exception_tables(regs->tpc);
2661                 if (entry) {
2662                         regs->tpc = entry->fixup;
2663                         regs->tnpc = regs->tpc + 4;
2664                         return;
2665                 }
2666                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2667                 die_if_kernel("HugeTSB in atomic", regs);
2668         }
2669
2670         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2671         if (likely(tp->tsb == NULL))
2672                 tsb_grow(mm, MM_TSB_HUGE, 0);
2673
2674         tsb_context_switch(mm);
2675         smp_tsb_sync(mm);
2676
2677         /* On UltraSPARC-III+ and later, configure the second half of
2678          * the Data-TLB for huge pages.
2679          */
2680         if (tlb_type == cheetah_plus) {
2681                 unsigned long ctx;
2682
2683                 spin_lock(&ctx_alloc_lock);
2684                 ctx = mm->context.sparc64_ctx_val;
2685                 ctx &= ~CTX_PGSZ_MASK;
2686                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2687                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2688
2689                 if (ctx != mm->context.sparc64_ctx_val) {
2690                         /* When changing the page size fields, we
2691                          * must perform a context flush so that no
2692                          * stale entries match.  This flush must
2693                          * occur with the original context register
2694                          * settings.
2695                          */
2696                         do_flush_tlb_mm(mm);
2697
2698                         /* Reload the context register of all processors
2699                          * also executing in this address space.
2700                          */
2701                         mm->context.sparc64_ctx_val = ctx;
2702                         on_each_cpu(context_reload, mm, 0);
2703                 }
2704                 spin_unlock(&ctx_alloc_lock);
2705         }
2706 }
2707 #endif
2708
2709 #ifdef CONFIG_SMP
2710 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
2711 #else
2712 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
2713 #endif
2714
2715 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2716 {
2717         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2718                 if (start < LOW_OBP_ADDRESS) {
2719                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2720                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2721                 }
2722                 if (end > HI_OBP_ADDRESS) {
2723                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2724                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2725                 }
2726         } else {
2727                 flush_tsb_kernel_range(start, end);
2728                 do_flush_tlb_kernel_range(start, end);
2729         }
2730 }