2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/ioport.h>
26 #include <linux/percpu.h>
27 #include <linux/memblock.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor[4] __read_mostly;
57 static unsigned long page_cache4v_flag;
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
89 static unsigned long cpu_pgsz_mask;
91 #define MAX_BANKS 1024
93 static struct linux_prom64_registers pavail[MAX_BANKS];
94 static int pavail_ents;
96 static int cmp_p64(const void *a, const void *b)
98 const struct linux_prom64_registers *x = a, *y = b;
100 if (x->phys_addr > y->phys_addr)
102 if (x->phys_addr < y->phys_addr)
107 static void __init read_obp_memory(const char *property,
108 struct linux_prom64_registers *regs,
111 phandle node = prom_finddevice("/memory");
112 int prop_size = prom_getproplen(node, property);
115 ents = prop_size / sizeof(struct linux_prom64_registers);
116 if (ents > MAX_BANKS) {
117 prom_printf("The machine has more %s property entries than "
118 "this kernel can support (%d).\n",
119 property, MAX_BANKS);
123 ret = prom_getproperty(node, property, (char *) regs, prop_size);
125 prom_printf("Couldn't get %s property from /memory.\n",
130 /* Sanitize what we got from the firmware, by page aligning
133 for (i = 0; i < ents; i++) {
134 unsigned long base, size;
136 base = regs[i].phys_addr;
137 size = regs[i].reg_size;
140 if (base & ~PAGE_MASK) {
141 unsigned long new_base = PAGE_ALIGN(base);
143 size -= new_base - base;
144 if ((long) size < 0L)
149 /* If it is empty, simply get rid of it.
150 * This simplifies the logic of the other
151 * functions that process these arrays.
153 memmove(®s[i], ®s[i + 1],
154 (ents - i - 1) * sizeof(regs[0]));
159 regs[i].phys_addr = base;
160 regs[i].reg_size = size;
165 sort(regs, ents, sizeof(struct linux_prom64_registers),
169 /* Kernel physical address base and size in bytes. */
170 unsigned long kern_base __read_mostly;
171 unsigned long kern_size __read_mostly;
173 /* Initial ramdisk setup */
174 extern unsigned long sparc_ramdisk_image64;
175 extern unsigned int sparc_ramdisk_image;
176 extern unsigned int sparc_ramdisk_size;
178 struct page *mem_map_zero __read_mostly;
179 EXPORT_SYMBOL(mem_map_zero);
181 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
183 unsigned long sparc64_kern_pri_context __read_mostly;
184 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
185 unsigned long sparc64_kern_sec_context __read_mostly;
187 int num_kernel_image_mappings;
189 #ifdef CONFIG_DEBUG_DCFLUSH
190 atomic_t dcpage_flushes = ATOMIC_INIT(0);
192 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
196 inline void flush_dcache_page_impl(struct page *page)
198 BUG_ON(tlb_type == hypervisor);
199 #ifdef CONFIG_DEBUG_DCFLUSH
200 atomic_inc(&dcpage_flushes);
203 #ifdef DCACHE_ALIASING_POSSIBLE
204 __flush_dcache_page(page_address(page),
205 ((tlb_type == spitfire) &&
206 page_mapping(page) != NULL));
208 if (page_mapping(page) != NULL &&
209 tlb_type == spitfire)
210 __flush_icache_page(__pa(page_address(page)));
214 #define PG_dcache_dirty PG_arch_1
215 #define PG_dcache_cpu_shift 32UL
216 #define PG_dcache_cpu_mask \
217 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
219 #define dcache_dirty_cpu(page) \
220 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
222 static inline void set_dcache_dirty(struct page *page, int this_cpu)
224 unsigned long mask = this_cpu;
225 unsigned long non_cpu_bits;
227 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
228 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
230 __asm__ __volatile__("1:\n\t"
232 "and %%g7, %1, %%g1\n\t"
233 "or %%g1, %0, %%g1\n\t"
234 "casx [%2], %%g7, %%g1\n\t"
236 "bne,pn %%xcc, 1b\n\t"
239 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
243 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
245 unsigned long mask = (1UL << PG_dcache_dirty);
247 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
250 "srlx %%g7, %4, %%g1\n\t"
251 "and %%g1, %3, %%g1\n\t"
253 "bne,pn %%icc, 2f\n\t"
254 " andn %%g7, %1, %%g1\n\t"
255 "casx [%2], %%g7, %%g1\n\t"
257 "bne,pn %%xcc, 1b\n\t"
261 : "r" (cpu), "r" (mask), "r" (&page->flags),
262 "i" (PG_dcache_cpu_mask),
263 "i" (PG_dcache_cpu_shift)
267 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269 unsigned long tsb_addr = (unsigned long) ent;
271 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
272 tsb_addr = __pa(tsb_addr);
274 __tsb_insert(tsb_addr, tag, pte);
277 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
279 static void flush_dcache(unsigned long pfn)
283 page = pfn_to_page(pfn);
285 unsigned long pg_flags;
287 pg_flags = page->flags;
288 if (pg_flags & (1UL << PG_dcache_dirty)) {
289 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
291 int this_cpu = get_cpu();
293 /* This is just to optimize away some function calls
297 flush_dcache_page_impl(page);
299 smp_flush_dcache_page_impl(page, cpu);
301 clear_dcache_dirty_cpu(page, cpu);
308 /* mm->context.lock must be held */
309 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
310 unsigned long tsb_hash_shift, unsigned long address,
313 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
319 tsb += ((address >> tsb_hash_shift) &
320 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
321 tag = (address >> 22UL);
322 tsb_insert(tsb, tag, tte);
325 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
326 static inline bool is_hugetlb_pte(pte_t pte)
328 if ((tlb_type == hypervisor &&
329 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
330 (tlb_type != hypervisor &&
331 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
337 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
339 struct mm_struct *mm;
343 if (tlb_type != hypervisor) {
344 unsigned long pfn = pte_pfn(pte);
352 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
353 if (!pte_accessible(mm, pte))
356 spin_lock_irqsave(&mm->context.lock, flags);
358 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
359 if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
360 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
361 address, pte_val(pte));
364 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
365 address, pte_val(pte));
367 spin_unlock_irqrestore(&mm->context.lock, flags);
370 void flush_dcache_page(struct page *page)
372 struct address_space *mapping;
375 if (tlb_type == hypervisor)
378 /* Do not bother with the expensive D-cache flush if it
379 * is merely the zero page. The 'bigcore' testcase in GDB
380 * causes this case to run millions of times.
382 if (page == ZERO_PAGE(0))
385 this_cpu = get_cpu();
387 mapping = page_mapping(page);
388 if (mapping && !mapping_mapped(mapping)) {
389 int dirty = test_bit(PG_dcache_dirty, &page->flags);
391 int dirty_cpu = dcache_dirty_cpu(page);
393 if (dirty_cpu == this_cpu)
395 smp_flush_dcache_page_impl(page, dirty_cpu);
397 set_dcache_dirty(page, this_cpu);
399 /* We could delay the flush for the !page_mapping
400 * case too. But that case is for exec env/arg
401 * pages and those are %99 certainly going to get
402 * faulted into the tlb (and thus flushed) anyways.
404 flush_dcache_page_impl(page);
410 EXPORT_SYMBOL(flush_dcache_page);
412 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
414 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
415 if (tlb_type == spitfire) {
418 /* This code only runs on Spitfire cpus so this is
419 * why we can assume _PAGE_PADDR_4U.
421 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
422 unsigned long paddr, mask = _PAGE_PADDR_4U;
424 if (kaddr >= PAGE_OFFSET)
425 paddr = kaddr & mask;
427 pgd_t *pgdp = pgd_offset_k(kaddr);
428 pud_t *pudp = pud_offset(pgdp, kaddr);
429 pmd_t *pmdp = pmd_offset(pudp, kaddr);
430 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
432 paddr = pte_val(*ptep) & mask;
434 __flush_icache_page(paddr);
438 EXPORT_SYMBOL(flush_icache_range);
440 void mmu_info(struct seq_file *m)
442 static const char *pgsz_strings[] = {
443 "8K", "64K", "512K", "4MB", "32MB",
444 "256MB", "2GB", "16GB",
448 if (tlb_type == cheetah)
449 seq_printf(m, "MMU Type\t: Cheetah\n");
450 else if (tlb_type == cheetah_plus)
451 seq_printf(m, "MMU Type\t: Cheetah+\n");
452 else if (tlb_type == spitfire)
453 seq_printf(m, "MMU Type\t: Spitfire\n");
454 else if (tlb_type == hypervisor)
455 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
457 seq_printf(m, "MMU Type\t: ???\n");
459 seq_printf(m, "MMU PGSZs\t: ");
461 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
462 if (cpu_pgsz_mask & (1UL << i)) {
463 seq_printf(m, "%s%s",
464 printed ? "," : "", pgsz_strings[i]);
470 #ifdef CONFIG_DEBUG_DCFLUSH
471 seq_printf(m, "DCPageFlushes\t: %d\n",
472 atomic_read(&dcpage_flushes));
474 seq_printf(m, "DCPageFlushesXC\t: %d\n",
475 atomic_read(&dcpage_flushes_xcall));
476 #endif /* CONFIG_SMP */
477 #endif /* CONFIG_DEBUG_DCFLUSH */
480 struct linux_prom_translation prom_trans[512] __read_mostly;
481 unsigned int prom_trans_ents __read_mostly;
483 unsigned long kern_locked_tte_data;
485 /* The obp translations are saved based on 8k pagesize, since obp can
486 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
487 * HI_OBP_ADDRESS range are handled in ktlb.S.
489 static inline int in_obp_range(unsigned long vaddr)
491 return (vaddr >= LOW_OBP_ADDRESS &&
492 vaddr < HI_OBP_ADDRESS);
495 static int cmp_ptrans(const void *a, const void *b)
497 const struct linux_prom_translation *x = a, *y = b;
499 if (x->virt > y->virt)
501 if (x->virt < y->virt)
506 /* Read OBP translations property into 'prom_trans[]'. */
507 static void __init read_obp_translations(void)
509 int n, node, ents, first, last, i;
511 node = prom_finddevice("/virtual-memory");
512 n = prom_getproplen(node, "translations");
513 if (unlikely(n == 0 || n == -1)) {
514 prom_printf("prom_mappings: Couldn't get size.\n");
517 if (unlikely(n > sizeof(prom_trans))) {
518 prom_printf("prom_mappings: Size %d is too big.\n", n);
522 if ((n = prom_getproperty(node, "translations",
523 (char *)&prom_trans[0],
524 sizeof(prom_trans))) == -1) {
525 prom_printf("prom_mappings: Couldn't get property.\n");
529 n = n / sizeof(struct linux_prom_translation);
533 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
536 /* Now kick out all the non-OBP entries. */
537 for (i = 0; i < ents; i++) {
538 if (in_obp_range(prom_trans[i].virt))
542 for (; i < ents; i++) {
543 if (!in_obp_range(prom_trans[i].virt))
548 for (i = 0; i < (last - first); i++) {
549 struct linux_prom_translation *src = &prom_trans[i + first];
550 struct linux_prom_translation *dest = &prom_trans[i];
554 for (; i < ents; i++) {
555 struct linux_prom_translation *dest = &prom_trans[i];
556 dest->virt = dest->size = dest->data = 0x0UL;
559 prom_trans_ents = last - first;
561 if (tlb_type == spitfire) {
562 /* Clear diag TTE bits. */
563 for (i = 0; i < prom_trans_ents; i++)
564 prom_trans[i].data &= ~0x0003fe0000000000UL;
567 /* Force execute bit on. */
568 for (i = 0; i < prom_trans_ents; i++)
569 prom_trans[i].data |= (tlb_type == hypervisor ?
570 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
573 static void __init hypervisor_tlb_lock(unsigned long vaddr,
577 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
580 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
581 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
586 static unsigned long kern_large_tte(unsigned long paddr);
588 static void __init remap_kernel(void)
590 unsigned long phys_page, tte_vaddr, tte_data;
591 int i, tlb_ent = sparc64_highest_locked_tlbent();
593 tte_vaddr = (unsigned long) KERNBASE;
594 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
595 tte_data = kern_large_tte(phys_page);
597 kern_locked_tte_data = tte_data;
599 /* Now lock us into the TLBs via Hypervisor or OBP. */
600 if (tlb_type == hypervisor) {
601 for (i = 0; i < num_kernel_image_mappings; i++) {
602 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
603 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
604 tte_vaddr += 0x400000;
605 tte_data += 0x400000;
608 for (i = 0; i < num_kernel_image_mappings; i++) {
609 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
610 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
611 tte_vaddr += 0x400000;
612 tte_data += 0x400000;
614 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
616 if (tlb_type == cheetah_plus) {
617 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
618 CTX_CHEETAH_PLUS_NUC);
619 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
620 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
625 static void __init inherit_prom_mappings(void)
627 /* Now fixup OBP's idea about where we really are mapped. */
628 printk("Remapping the kernel... ");
633 void prom_world(int enter)
638 __asm__ __volatile__("flushw");
641 void __flush_dcache_range(unsigned long start, unsigned long end)
645 if (tlb_type == spitfire) {
648 for (va = start; va < end; va += 32) {
649 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
653 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
656 for (va = start; va < end; va += 32)
657 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
661 "i" (ASI_DCACHE_INVALIDATE));
664 EXPORT_SYMBOL(__flush_dcache_range);
666 /* get_new_mmu_context() uses "cache + 1". */
667 DEFINE_SPINLOCK(ctx_alloc_lock);
668 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
669 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
670 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
671 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
673 /* Caller does TLB context flushing on local CPU if necessary.
674 * The caller also ensures that CTX_VALID(mm->context) is false.
676 * We must be careful about boundary cases so that we never
677 * let the user have CTX 0 (nucleus) or we ever use a CTX
678 * version of zero (and thus NO_CONTEXT would not be caught
679 * by version mis-match tests in mmu_context.h).
681 * Always invoked with interrupts disabled.
683 void get_new_mmu_context(struct mm_struct *mm)
685 unsigned long ctx, new_ctx;
686 unsigned long orig_pgsz_bits;
689 spin_lock(&ctx_alloc_lock);
690 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
691 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
692 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
694 if (new_ctx >= (1 << CTX_NR_BITS)) {
695 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
696 if (new_ctx >= ctx) {
698 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
701 new_ctx = CTX_FIRST_VERSION;
703 /* Don't call memset, for 16 entries that's just
706 mmu_context_bmap[0] = 3;
707 mmu_context_bmap[1] = 0;
708 mmu_context_bmap[2] = 0;
709 mmu_context_bmap[3] = 0;
710 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
711 mmu_context_bmap[i + 0] = 0;
712 mmu_context_bmap[i + 1] = 0;
713 mmu_context_bmap[i + 2] = 0;
714 mmu_context_bmap[i + 3] = 0;
720 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
721 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
723 tlb_context_cache = new_ctx;
724 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
725 spin_unlock(&ctx_alloc_lock);
727 if (unlikely(new_version))
728 smp_new_mmu_context_version();
731 static int numa_enabled = 1;
732 static int numa_debug;
734 static int __init early_numa(char *p)
739 if (strstr(p, "off"))
742 if (strstr(p, "debug"))
747 early_param("numa", early_numa);
749 #define numadbg(f, a...) \
750 do { if (numa_debug) \
751 printk(KERN_INFO f, ## a); \
754 static void __init find_ramdisk(unsigned long phys_base)
756 #ifdef CONFIG_BLK_DEV_INITRD
757 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
758 unsigned long ramdisk_image;
760 /* Older versions of the bootloader only supported a
761 * 32-bit physical address for the ramdisk image
762 * location, stored at sparc_ramdisk_image. Newer
763 * SILO versions set sparc_ramdisk_image to zero and
764 * provide a full 64-bit physical address at
765 * sparc_ramdisk_image64.
767 ramdisk_image = sparc_ramdisk_image;
769 ramdisk_image = sparc_ramdisk_image64;
771 /* Another bootloader quirk. The bootloader normalizes
772 * the physical address to KERNBASE, so we have to
773 * factor that back out and add in the lowest valid
774 * physical page address to get the true physical address.
776 ramdisk_image -= KERNBASE;
777 ramdisk_image += phys_base;
779 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
780 ramdisk_image, sparc_ramdisk_size);
782 initrd_start = ramdisk_image;
783 initrd_end = ramdisk_image + sparc_ramdisk_size;
785 memblock_reserve(initrd_start, sparc_ramdisk_size);
787 initrd_start += PAGE_OFFSET;
788 initrd_end += PAGE_OFFSET;
793 struct node_mem_mask {
797 static struct node_mem_mask node_masks[MAX_NUMNODES];
798 static int num_node_masks;
800 #ifdef CONFIG_NEED_MULTIPLE_NODES
802 int numa_cpu_lookup_table[NR_CPUS];
803 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
805 struct mdesc_mblock {
808 u64 offset; /* RA-to-PA */
810 static struct mdesc_mblock *mblocks;
811 static int num_mblocks;
813 static unsigned long ra_to_pa(unsigned long addr)
817 for (i = 0; i < num_mblocks; i++) {
818 struct mdesc_mblock *m = &mblocks[i];
820 if (addr >= m->base &&
821 addr < (m->base + m->size)) {
829 static int find_node(unsigned long addr)
833 addr = ra_to_pa(addr);
834 for (i = 0; i < num_node_masks; i++) {
835 struct node_mem_mask *p = &node_masks[i];
837 if ((addr & p->mask) == p->val)
840 /* The following condition has been observed on LDOM guests.*/
841 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
842 " rule. Some physical memory will be owned by node 0.");
846 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
848 *nid = find_node(start);
850 while (start < end) {
851 int n = find_node(start);
865 /* This must be invoked after performing all of the necessary
866 * memblock_set_node() calls for 'nid'. We need to be able to get
867 * correct data from get_pfn_range_for_nid().
869 static void __init allocate_node_data(int nid)
871 struct pglist_data *p;
872 unsigned long start_pfn, end_pfn;
873 #ifdef CONFIG_NEED_MULTIPLE_NODES
876 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
878 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
881 NODE_DATA(nid) = __va(paddr);
882 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
884 NODE_DATA(nid)->node_id = nid;
889 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
890 p->node_start_pfn = start_pfn;
891 p->node_spanned_pages = end_pfn - start_pfn;
894 static void init_node_masks_nonnuma(void)
896 #ifdef CONFIG_NEED_MULTIPLE_NODES
900 numadbg("Initializing tables for non-numa.\n");
902 node_masks[0].mask = node_masks[0].val = 0;
905 #ifdef CONFIG_NEED_MULTIPLE_NODES
906 for (i = 0; i < NR_CPUS; i++)
907 numa_cpu_lookup_table[i] = 0;
909 cpumask_setall(&numa_cpumask_lookup_table[0]);
913 #ifdef CONFIG_NEED_MULTIPLE_NODES
914 struct pglist_data *node_data[MAX_NUMNODES];
916 EXPORT_SYMBOL(numa_cpu_lookup_table);
917 EXPORT_SYMBOL(numa_cpumask_lookup_table);
918 EXPORT_SYMBOL(node_data);
920 struct mdesc_mlgroup {
926 static struct mdesc_mlgroup *mlgroups;
927 static int num_mlgroups;
929 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
934 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
935 u64 target = mdesc_arc_target(md, arc);
938 val = mdesc_get_property(md, target,
940 if (val && *val == cfg_handle)
946 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
949 u64 arc, candidate, best_latency = ~(u64)0;
951 candidate = MDESC_NODE_NULL;
952 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
953 u64 target = mdesc_arc_target(md, arc);
954 const char *name = mdesc_node_name(md, target);
957 if (strcmp(name, "pio-latency-group"))
960 val = mdesc_get_property(md, target, "latency", NULL);
964 if (*val < best_latency) {
970 if (candidate == MDESC_NODE_NULL)
973 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
976 int of_node_to_nid(struct device_node *dp)
978 const struct linux_prom64_registers *regs;
979 struct mdesc_handle *md;
984 /* This is the right thing to do on currently supported
985 * SUN4U NUMA platforms as well, as the PCI controller does
986 * not sit behind any particular memory controller.
991 regs = of_get_property(dp, "reg", NULL);
995 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1001 mdesc_for_each_node_by_name(md, grp, "group") {
1002 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1014 static void __init add_node_ranges(void)
1016 struct memblock_region *reg;
1018 for_each_memblock(memory, reg) {
1019 unsigned long size = reg->size;
1020 unsigned long start, end;
1024 while (start < end) {
1025 unsigned long this_end;
1028 this_end = memblock_nid_range(start, end, &nid);
1030 numadbg("Setting memblock NUMA node nid[%d] "
1031 "start[%lx] end[%lx]\n",
1032 nid, start, this_end);
1034 memblock_set_node(start, this_end - start,
1035 &memblock.memory, nid);
1041 static int __init grab_mlgroups(struct mdesc_handle *md)
1043 unsigned long paddr;
1047 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1052 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1057 mlgroups = __va(paddr);
1058 num_mlgroups = count;
1061 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1062 struct mdesc_mlgroup *m = &mlgroups[count++];
1067 val = mdesc_get_property(md, node, "latency", NULL);
1069 val = mdesc_get_property(md, node, "address-match", NULL);
1071 val = mdesc_get_property(md, node, "address-mask", NULL);
1074 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1075 "match[%llx] mask[%llx]\n",
1076 count - 1, m->node, m->latency, m->match, m->mask);
1082 static int __init grab_mblocks(struct mdesc_handle *md)
1084 unsigned long paddr;
1088 mdesc_for_each_node_by_name(md, node, "mblock")
1093 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1098 mblocks = __va(paddr);
1099 num_mblocks = count;
1102 mdesc_for_each_node_by_name(md, node, "mblock") {
1103 struct mdesc_mblock *m = &mblocks[count++];
1106 val = mdesc_get_property(md, node, "base", NULL);
1108 val = mdesc_get_property(md, node, "size", NULL);
1110 val = mdesc_get_property(md, node,
1111 "address-congruence-offset", NULL);
1113 /* The address-congruence-offset property is optional.
1114 * Explicity zero it be identifty this.
1121 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1122 count - 1, m->base, m->size, m->offset);
1128 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1129 u64 grp, cpumask_t *mask)
1133 cpumask_clear(mask);
1135 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1136 u64 target = mdesc_arc_target(md, arc);
1137 const char *name = mdesc_node_name(md, target);
1140 if (strcmp(name, "cpu"))
1142 id = mdesc_get_property(md, target, "id", NULL);
1143 if (*id < nr_cpu_ids)
1144 cpumask_set_cpu(*id, mask);
1148 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1152 for (i = 0; i < num_mlgroups; i++) {
1153 struct mdesc_mlgroup *m = &mlgroups[i];
1154 if (m->node == node)
1160 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1163 struct mdesc_mlgroup *candidate = NULL;
1164 u64 arc, best_latency = ~(u64)0;
1165 struct node_mem_mask *n;
1167 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1168 u64 target = mdesc_arc_target(md, arc);
1169 struct mdesc_mlgroup *m = find_mlgroup(target);
1172 if (m->latency < best_latency) {
1174 best_latency = m->latency;
1180 if (num_node_masks != index) {
1181 printk(KERN_ERR "Inconsistent NUMA state, "
1182 "index[%d] != num_node_masks[%d]\n",
1183 index, num_node_masks);
1187 n = &node_masks[num_node_masks++];
1189 n->mask = candidate->mask;
1190 n->val = candidate->match;
1192 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1193 index, n->mask, n->val, candidate->latency);
1198 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1204 numa_parse_mdesc_group_cpus(md, grp, &mask);
1206 for_each_cpu(cpu, &mask)
1207 numa_cpu_lookup_table[cpu] = index;
1208 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1211 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1212 for_each_cpu(cpu, &mask)
1217 return numa_attach_mlgroup(md, grp, index);
1220 static int __init numa_parse_mdesc(void)
1222 struct mdesc_handle *md = mdesc_grab();
1226 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1227 if (node == MDESC_NODE_NULL) {
1232 err = grab_mblocks(md);
1236 err = grab_mlgroups(md);
1241 mdesc_for_each_node_by_name(md, node, "group") {
1242 err = numa_parse_mdesc_group(md, node, count);
1250 for (i = 0; i < num_node_masks; i++) {
1251 allocate_node_data(i);
1261 static int __init numa_parse_jbus(void)
1263 unsigned long cpu, index;
1265 /* NUMA node id is encoded in bits 36 and higher, and there is
1266 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1269 for_each_present_cpu(cpu) {
1270 numa_cpu_lookup_table[cpu] = index;
1271 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1272 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1273 node_masks[index].val = cpu << 36UL;
1277 num_node_masks = index;
1281 for (index = 0; index < num_node_masks; index++) {
1282 allocate_node_data(index);
1283 node_set_online(index);
1289 static int __init numa_parse_sun4u(void)
1291 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1294 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1295 if ((ver >> 32UL) == __JALAPENO_ID ||
1296 (ver >> 32UL) == __SERRANO_ID)
1297 return numa_parse_jbus();
1302 static int __init bootmem_init_numa(void)
1306 numadbg("bootmem_init_numa()\n");
1309 if (tlb_type == hypervisor)
1310 err = numa_parse_mdesc();
1312 err = numa_parse_sun4u();
1319 static int bootmem_init_numa(void)
1326 static void __init bootmem_init_nonnuma(void)
1328 unsigned long top_of_ram = memblock_end_of_DRAM();
1329 unsigned long total_ram = memblock_phys_mem_size();
1331 numadbg("bootmem_init_nonnuma()\n");
1333 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1334 top_of_ram, total_ram);
1335 printk(KERN_INFO "Memory hole size: %ldMB\n",
1336 (top_of_ram - total_ram) >> 20);
1338 init_node_masks_nonnuma();
1339 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1340 allocate_node_data(0);
1344 static unsigned long __init bootmem_init(unsigned long phys_base)
1346 unsigned long end_pfn;
1348 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1349 max_pfn = max_low_pfn = end_pfn;
1350 min_low_pfn = (phys_base >> PAGE_SHIFT);
1352 if (bootmem_init_numa() < 0)
1353 bootmem_init_nonnuma();
1355 /* Dump memblock with node info. */
1356 memblock_dump_all();
1358 /* XXX cpu notifier XXX */
1360 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1366 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1367 static int pall_ents __initdata;
1369 static unsigned long max_phys_bits = 40;
1371 bool kern_addr_valid(unsigned long addr)
1378 if ((long)addr < 0L) {
1379 unsigned long pa = __pa(addr);
1381 if ((addr >> max_phys_bits) != 0UL)
1384 return pfn_valid(pa >> PAGE_SHIFT);
1387 if (addr >= (unsigned long) KERNBASE &&
1388 addr < (unsigned long)&_end)
1391 pgd = pgd_offset_k(addr);
1395 pud = pud_offset(pgd, addr);
1399 if (pud_large(*pud))
1400 return pfn_valid(pud_pfn(*pud));
1402 pmd = pmd_offset(pud, addr);
1406 if (pmd_large(*pmd))
1407 return pfn_valid(pmd_pfn(*pmd));
1409 pte = pte_offset_kernel(pmd, addr);
1413 return pfn_valid(pte_pfn(*pte));
1415 EXPORT_SYMBOL(kern_addr_valid);
1417 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1421 const unsigned long mask16gb = (1UL << 34) - 1UL;
1422 u64 pte_val = vstart;
1424 /* Each PUD is 8GB */
1425 if ((vstart & mask16gb) ||
1426 (vend - vstart <= mask16gb)) {
1427 pte_val ^= kern_linear_pte_xor[2];
1428 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1430 return vstart + PUD_SIZE;
1433 pte_val ^= kern_linear_pte_xor[3];
1434 pte_val |= _PAGE_PUD_HUGE;
1436 vend = vstart + mask16gb + 1UL;
1437 while (vstart < vend) {
1438 pud_val(*pud) = pte_val;
1440 pte_val += PUD_SIZE;
1447 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1450 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1456 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1460 const unsigned long mask256mb = (1UL << 28) - 1UL;
1461 const unsigned long mask2gb = (1UL << 31) - 1UL;
1462 u64 pte_val = vstart;
1464 /* Each PMD is 8MB */
1465 if ((vstart & mask256mb) ||
1466 (vend - vstart <= mask256mb)) {
1467 pte_val ^= kern_linear_pte_xor[0];
1468 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1470 return vstart + PMD_SIZE;
1473 if ((vstart & mask2gb) ||
1474 (vend - vstart <= mask2gb)) {
1475 pte_val ^= kern_linear_pte_xor[1];
1476 pte_val |= _PAGE_PMD_HUGE;
1477 vend = vstart + mask256mb + 1UL;
1479 pte_val ^= kern_linear_pte_xor[2];
1480 pte_val |= _PAGE_PMD_HUGE;
1481 vend = vstart + mask2gb + 1UL;
1484 while (vstart < vend) {
1485 pmd_val(*pmd) = pte_val;
1487 pte_val += PMD_SIZE;
1495 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1498 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1504 static unsigned long __ref kernel_map_range(unsigned long pstart,
1505 unsigned long pend, pgprot_t prot,
1508 unsigned long vstart = PAGE_OFFSET + pstart;
1509 unsigned long vend = PAGE_OFFSET + pend;
1510 unsigned long alloc_bytes = 0UL;
1512 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1513 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1518 while (vstart < vend) {
1519 unsigned long this_end, paddr = __pa(vstart);
1520 pgd_t *pgd = pgd_offset_k(vstart);
1525 if (pgd_none(*pgd)) {
1528 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1529 alloc_bytes += PAGE_SIZE;
1530 pgd_populate(&init_mm, pgd, new);
1532 pud = pud_offset(pgd, vstart);
1533 if (pud_none(*pud)) {
1536 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1537 vstart = kernel_map_hugepud(vstart, vend, pud);
1540 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1541 alloc_bytes += PAGE_SIZE;
1542 pud_populate(&init_mm, pud, new);
1545 pmd = pmd_offset(pud, vstart);
1546 if (pmd_none(*pmd)) {
1549 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1550 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1553 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1554 alloc_bytes += PAGE_SIZE;
1555 pmd_populate_kernel(&init_mm, pmd, new);
1558 pte = pte_offset_kernel(pmd, vstart);
1559 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1560 if (this_end > vend)
1563 while (vstart < this_end) {
1564 pte_val(*pte) = (paddr | pgprot_val(prot));
1566 vstart += PAGE_SIZE;
1575 static void __init flush_all_kernel_tsbs(void)
1579 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1580 struct tsb *ent = &swapper_tsb[i];
1582 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1584 #ifndef CONFIG_DEBUG_PAGEALLOC
1585 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1586 struct tsb *ent = &swapper_4m_tsb[i];
1588 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1593 extern unsigned int kvmap_linear_patch[1];
1595 static void __init kernel_physical_mapping_init(void)
1597 unsigned long i, mem_alloced = 0UL;
1598 bool use_huge = true;
1600 #ifdef CONFIG_DEBUG_PAGEALLOC
1603 for (i = 0; i < pall_ents; i++) {
1604 unsigned long phys_start, phys_end;
1606 phys_start = pall[i].phys_addr;
1607 phys_end = phys_start + pall[i].reg_size;
1609 mem_alloced += kernel_map_range(phys_start, phys_end,
1610 PAGE_KERNEL, use_huge);
1613 printk("Allocated %ld bytes for kernel page tables.\n",
1616 kvmap_linear_patch[0] = 0x01000000; /* nop */
1617 flushi(&kvmap_linear_patch[0]);
1619 flush_all_kernel_tsbs();
1624 #ifdef CONFIG_DEBUG_PAGEALLOC
1625 void __kernel_map_pages(struct page *page, int numpages, int enable)
1627 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1628 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1630 kernel_map_range(phys_start, phys_end,
1631 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1633 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1634 PAGE_OFFSET + phys_end);
1636 /* we should perform an IPI and flush all tlbs,
1637 * but that can deadlock->flush only current cpu.
1639 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1640 PAGE_OFFSET + phys_end);
1644 unsigned long __init find_ecache_flush_span(unsigned long size)
1648 for (i = 0; i < pavail_ents; i++) {
1649 if (pavail[i].reg_size >= size)
1650 return pavail[i].phys_addr;
1656 unsigned long PAGE_OFFSET;
1657 EXPORT_SYMBOL(PAGE_OFFSET);
1659 unsigned long VMALLOC_END = 0x0000010000000000UL;
1660 EXPORT_SYMBOL(VMALLOC_END);
1662 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1663 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1665 static void __init setup_page_offset(void)
1667 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1668 /* Cheetah/Panther support a full 64-bit virtual
1669 * address, so we can use all that our page tables
1672 sparc64_va_hole_top = 0xfff0000000000000UL;
1673 sparc64_va_hole_bottom = 0x0010000000000000UL;
1676 } else if (tlb_type == hypervisor) {
1677 switch (sun4v_chip_type) {
1678 case SUN4V_CHIP_NIAGARA1:
1679 case SUN4V_CHIP_NIAGARA2:
1680 /* T1 and T2 support 48-bit virtual addresses. */
1681 sparc64_va_hole_top = 0xffff800000000000UL;
1682 sparc64_va_hole_bottom = 0x0000800000000000UL;
1686 case SUN4V_CHIP_NIAGARA3:
1687 /* T3 supports 48-bit virtual addresses. */
1688 sparc64_va_hole_top = 0xffff800000000000UL;
1689 sparc64_va_hole_bottom = 0x0000800000000000UL;
1693 case SUN4V_CHIP_NIAGARA4:
1694 case SUN4V_CHIP_NIAGARA5:
1695 case SUN4V_CHIP_SPARC64X:
1696 case SUN4V_CHIP_SPARC_M6:
1697 /* T4 and later support 52-bit virtual addresses. */
1698 sparc64_va_hole_top = 0xfff8000000000000UL;
1699 sparc64_va_hole_bottom = 0x0008000000000000UL;
1702 case SUN4V_CHIP_SPARC_M7:
1704 /* M7 and later support 52-bit virtual addresses. */
1705 sparc64_va_hole_top = 0xfff8000000000000UL;
1706 sparc64_va_hole_bottom = 0x0008000000000000UL;
1712 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1713 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1718 PAGE_OFFSET = sparc64_va_hole_top;
1719 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1720 (sparc64_va_hole_bottom >> 2));
1722 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1723 PAGE_OFFSET, max_phys_bits);
1724 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1725 VMALLOC_START, VMALLOC_END);
1726 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1727 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1730 static void __init tsb_phys_patch(void)
1732 struct tsb_ldquad_phys_patch_entry *pquad;
1733 struct tsb_phys_patch_entry *p;
1735 pquad = &__tsb_ldquad_phys_patch;
1736 while (pquad < &__tsb_ldquad_phys_patch_end) {
1737 unsigned long addr = pquad->addr;
1739 if (tlb_type == hypervisor)
1740 *(unsigned int *) addr = pquad->sun4v_insn;
1742 *(unsigned int *) addr = pquad->sun4u_insn;
1744 __asm__ __volatile__("flush %0"
1751 p = &__tsb_phys_patch;
1752 while (p < &__tsb_phys_patch_end) {
1753 unsigned long addr = p->addr;
1755 *(unsigned int *) addr = p->insn;
1757 __asm__ __volatile__("flush %0"
1765 /* Don't mark as init, we give this to the Hypervisor. */
1766 #ifndef CONFIG_DEBUG_PAGEALLOC
1767 #define NUM_KTSB_DESCR 2
1769 #define NUM_KTSB_DESCR 1
1771 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1773 /* The swapper TSBs are loaded with a base sequence of:
1775 * sethi %uhi(SYMBOL), REG1
1776 * sethi %hi(SYMBOL), REG2
1777 * or REG1, %ulo(SYMBOL), REG1
1778 * or REG2, %lo(SYMBOL), REG2
1779 * sllx REG1, 32, REG1
1780 * or REG1, REG2, REG1
1782 * When we use physical addressing for the TSB accesses, we patch the
1783 * first four instructions in the above sequence.
1786 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1788 unsigned long high_bits, low_bits;
1790 high_bits = (pa >> 32) & 0xffffffff;
1791 low_bits = (pa >> 0) & 0xffffffff;
1793 while (start < end) {
1794 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1796 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1797 __asm__ __volatile__("flush %0" : : "r" (ia));
1799 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1800 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1802 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1803 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
1805 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1806 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
1812 static void ktsb_phys_patch(void)
1814 extern unsigned int __swapper_tsb_phys_patch;
1815 extern unsigned int __swapper_tsb_phys_patch_end;
1816 unsigned long ktsb_pa;
1818 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1819 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1820 &__swapper_tsb_phys_patch_end, ktsb_pa);
1821 #ifndef CONFIG_DEBUG_PAGEALLOC
1823 extern unsigned int __swapper_4m_tsb_phys_patch;
1824 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1825 ktsb_pa = (kern_base +
1826 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1827 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1828 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1833 static void __init sun4v_ktsb_init(void)
1835 unsigned long ktsb_pa;
1837 /* First KTSB for PAGE_SIZE mappings. */
1838 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1840 switch (PAGE_SIZE) {
1843 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1844 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1848 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1849 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1853 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1854 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1857 case 4 * 1024 * 1024:
1858 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1859 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1863 ktsb_descr[0].assoc = 1;
1864 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1865 ktsb_descr[0].ctx_idx = 0;
1866 ktsb_descr[0].tsb_base = ktsb_pa;
1867 ktsb_descr[0].resv = 0;
1869 #ifndef CONFIG_DEBUG_PAGEALLOC
1870 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1871 ktsb_pa = (kern_base +
1872 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1874 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1875 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1876 HV_PGSZ_MASK_256MB |
1878 HV_PGSZ_MASK_16GB) &
1880 ktsb_descr[1].assoc = 1;
1881 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1882 ktsb_descr[1].ctx_idx = 0;
1883 ktsb_descr[1].tsb_base = ktsb_pa;
1884 ktsb_descr[1].resv = 0;
1888 void sun4v_ktsb_register(void)
1890 unsigned long pa, ret;
1892 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1894 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1896 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1897 "errors with %lx\n", pa, ret);
1902 static void __init sun4u_linear_pte_xor_finalize(void)
1904 #ifndef CONFIG_DEBUG_PAGEALLOC
1905 /* This is where we would add Panther support for
1906 * 32MB and 256MB pages.
1911 static void __init sun4v_linear_pte_xor_finalize(void)
1913 unsigned long pagecv_flag;
1915 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1916 * enables MCD error. Do not set bit 9 on M7 processor.
1918 switch (sun4v_chip_type) {
1919 case SUN4V_CHIP_SPARC_M7:
1923 pagecv_flag = _PAGE_CV_4V;
1926 #ifndef CONFIG_DEBUG_PAGEALLOC
1927 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1928 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1930 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
1931 _PAGE_P_4V | _PAGE_W_4V);
1933 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1936 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1937 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1939 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
1940 _PAGE_P_4V | _PAGE_W_4V);
1942 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1945 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1946 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1948 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
1949 _PAGE_P_4V | _PAGE_W_4V);
1951 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1956 /* paging_init() sets up the page tables */
1958 static unsigned long last_valid_pfn;
1960 static void sun4u_pgprot_init(void);
1961 static void sun4v_pgprot_init(void);
1963 static phys_addr_t __init available_memory(void)
1965 phys_addr_t available = 0ULL;
1966 phys_addr_t pa_start, pa_end;
1969 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
1971 available = available + (pa_end - pa_start);
1976 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1977 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1978 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1979 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1980 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1981 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1983 /* We need to exclude reserved regions. This exclusion will include
1984 * vmlinux and initrd. To be more precise the initrd size could be used to
1985 * compute a new lower limit because it is freed later during initialization.
1987 static void __init reduce_memory(phys_addr_t limit_ram)
1989 phys_addr_t avail_ram = available_memory();
1990 phys_addr_t pa_start, pa_end;
1993 if (limit_ram >= avail_ram)
1996 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
1998 phys_addr_t region_size = pa_end - pa_start;
1999 phys_addr_t clip_start = pa_start;
2001 avail_ram = avail_ram - region_size;
2002 /* Are we consuming too much? */
2003 if (avail_ram < limit_ram) {
2004 phys_addr_t give_back = limit_ram - avail_ram;
2006 region_size = region_size - give_back;
2007 clip_start = clip_start + give_back;
2010 memblock_remove(clip_start, region_size);
2012 if (avail_ram <= limit_ram)
2018 void __init paging_init(void)
2020 unsigned long end_pfn, shift, phys_base;
2021 unsigned long real_end, i;
2024 setup_page_offset();
2026 /* These build time checkes make sure that the dcache_dirty_cpu()
2027 * page->flags usage will work.
2029 * When a page gets marked as dcache-dirty, we store the
2030 * cpu number starting at bit 32 in the page->flags. Also,
2031 * functions like clear_dcache_dirty_cpu use the cpu mask
2032 * in 13-bit signed-immediate instruction fields.
2036 * Page flags must not reach into upper 32 bits that are used
2037 * for the cpu number
2039 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2042 * The bit fields placed in the high range must not reach below
2043 * the 32 bit boundary. Otherwise we cannot place the cpu field
2044 * at the 32 bit boundary.
2046 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2047 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2049 BUILD_BUG_ON(NR_CPUS > 4096);
2051 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2052 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2054 /* Invalidate both kernel TSBs. */
2055 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2056 #ifndef CONFIG_DEBUG_PAGEALLOC
2057 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2060 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2061 * bit on M7 processor. This is a conflicting usage of the same
2062 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2063 * Detection error on all pages and this will lead to problems
2064 * later. Kernel does not run with MCD enabled and hence rest
2065 * of the required steps to fully configure memory corruption
2066 * detection are not taken. We need to ensure TTE.mcde is not
2067 * set on M7 processor. Compute the value of cacheability
2068 * flag for use later taking this into consideration.
2070 switch (sun4v_chip_type) {
2071 case SUN4V_CHIP_SPARC_M7:
2072 page_cache4v_flag = _PAGE_CP_4V;
2075 page_cache4v_flag = _PAGE_CACHE_4V;
2079 if (tlb_type == hypervisor)
2080 sun4v_pgprot_init();
2082 sun4u_pgprot_init();
2084 if (tlb_type == cheetah_plus ||
2085 tlb_type == hypervisor) {
2090 if (tlb_type == hypervisor)
2091 sun4v_patch_tlb_handlers();
2093 /* Find available physical memory...
2095 * Read it twice in order to work around a bug in openfirmware.
2096 * The call to grab this table itself can cause openfirmware to
2097 * allocate memory, which in turn can take away some space from
2098 * the list of available memory. Reading it twice makes sure
2099 * we really do get the final value.
2101 read_obp_translations();
2102 read_obp_memory("reg", &pall[0], &pall_ents);
2103 read_obp_memory("available", &pavail[0], &pavail_ents);
2104 read_obp_memory("available", &pavail[0], &pavail_ents);
2106 phys_base = 0xffffffffffffffffUL;
2107 for (i = 0; i < pavail_ents; i++) {
2108 phys_base = min(phys_base, pavail[i].phys_addr);
2109 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2112 memblock_reserve(kern_base, kern_size);
2114 find_ramdisk(phys_base);
2116 if (cmdline_memory_size)
2117 reduce_memory(cmdline_memory_size);
2119 memblock_allow_resize();
2120 memblock_dump_all();
2122 set_bit(0, mmu_context_bmap);
2124 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2126 real_end = (unsigned long)_end;
2127 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2128 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2129 num_kernel_image_mappings);
2131 /* Set kernel pgd to upper alias so physical page computations
2134 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2136 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2138 inherit_prom_mappings();
2140 /* Ok, we can use our TLB miss and window trap handlers safely. */
2145 prom_build_devicetree();
2146 of_populate_present_mask();
2148 of_fill_in_cpu_data();
2151 if (tlb_type == hypervisor) {
2153 mdesc_populate_present_mask(cpu_all_mask);
2155 mdesc_fill_in_cpu_data(cpu_all_mask);
2157 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2159 sun4v_linear_pte_xor_finalize();
2162 sun4v_ktsb_register();
2164 unsigned long impl, ver;
2166 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2167 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2169 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2170 impl = ((ver >> 32) & 0xffff);
2171 if (impl == PANTHER_IMPL)
2172 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2173 HV_PGSZ_MASK_256MB);
2175 sun4u_linear_pte_xor_finalize();
2178 /* Flush the TLBs and the 4M TSB so that the updated linear
2179 * pte XOR settings are realized for all mappings.
2182 #ifndef CONFIG_DEBUG_PAGEALLOC
2183 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2187 /* Setup bootmem... */
2188 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2190 /* Once the OF device tree and MDESC have been setup, we know
2191 * the list of possible cpus. Therefore we can allocate the
2194 for_each_possible_cpu(i) {
2195 node = cpu_to_node(i);
2197 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2200 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2205 kernel_physical_mapping_init();
2208 unsigned long max_zone_pfns[MAX_NR_ZONES];
2210 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2212 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2214 free_area_init_nodes(max_zone_pfns);
2217 printk("Booting Linux...\n");
2220 int page_in_phys_avail(unsigned long paddr)
2226 for (i = 0; i < pavail_ents; i++) {
2227 unsigned long start, end;
2229 start = pavail[i].phys_addr;
2230 end = start + pavail[i].reg_size;
2232 if (paddr >= start && paddr < end)
2235 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2237 #ifdef CONFIG_BLK_DEV_INITRD
2238 if (paddr >= __pa(initrd_start) &&
2239 paddr < __pa(PAGE_ALIGN(initrd_end)))
2246 static void __init register_page_bootmem_info(void)
2248 #ifdef CONFIG_NEED_MULTIPLE_NODES
2251 for_each_online_node(i)
2252 if (NODE_DATA(i)->node_spanned_pages)
2253 register_page_bootmem_info_node(NODE_DATA(i));
2256 void __init mem_init(void)
2258 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2260 register_page_bootmem_info();
2264 * Set up the zero page, mark it reserved, so that page count
2265 * is not manipulated when freeing the page from user ptes.
2267 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2268 if (mem_map_zero == NULL) {
2269 prom_printf("paging_init: Cannot alloc zero page.\n");
2272 mark_page_reserved(mem_map_zero);
2274 mem_init_print_info(NULL);
2276 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2277 cheetah_ecache_flush_init();
2280 void free_initmem(void)
2282 unsigned long addr, initend;
2285 /* If the physical memory maps were trimmed by kernel command
2286 * line options, don't even try freeing this initmem stuff up.
2287 * The kernel image could have been in the trimmed out region
2288 * and if so the freeing below will free invalid page structs.
2290 if (cmdline_memory_size)
2294 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2296 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2297 initend = (unsigned long)(__init_end) & PAGE_MASK;
2298 for (; addr < initend; addr += PAGE_SIZE) {
2302 ((unsigned long) __va(kern_base)) -
2303 ((unsigned long) KERNBASE));
2304 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2307 free_reserved_page(virt_to_page(page));
2311 #ifdef CONFIG_BLK_DEV_INITRD
2312 void free_initrd_mem(unsigned long start, unsigned long end)
2314 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2319 pgprot_t PAGE_KERNEL __read_mostly;
2320 EXPORT_SYMBOL(PAGE_KERNEL);
2322 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2323 pgprot_t PAGE_COPY __read_mostly;
2325 pgprot_t PAGE_SHARED __read_mostly;
2326 EXPORT_SYMBOL(PAGE_SHARED);
2328 unsigned long pg_iobits __read_mostly;
2330 unsigned long _PAGE_IE __read_mostly;
2331 EXPORT_SYMBOL(_PAGE_IE);
2333 unsigned long _PAGE_E __read_mostly;
2334 EXPORT_SYMBOL(_PAGE_E);
2336 unsigned long _PAGE_CACHE __read_mostly;
2337 EXPORT_SYMBOL(_PAGE_CACHE);
2339 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2340 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2343 unsigned long pte_base;
2345 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2346 _PAGE_CP_4U | _PAGE_CV_4U |
2347 _PAGE_P_4U | _PAGE_W_4U);
2348 if (tlb_type == hypervisor)
2349 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2350 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2352 pte_base |= _PAGE_PMD_HUGE;
2354 vstart = vstart & PMD_MASK;
2355 vend = ALIGN(vend, PMD_SIZE);
2356 for (; vstart < vend; vstart += PMD_SIZE) {
2357 pgd_t *pgd = pgd_offset_k(vstart);
2362 if (pgd_none(*pgd)) {
2363 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2367 pgd_populate(&init_mm, pgd, new);
2370 pud = pud_offset(pgd, vstart);
2371 if (pud_none(*pud)) {
2372 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2376 pud_populate(&init_mm, pud, new);
2379 pmd = pmd_offset(pud, vstart);
2381 pte = pmd_val(*pmd);
2382 if (!(pte & _PAGE_VALID)) {
2383 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2388 pmd_val(*pmd) = pte_base | __pa(block);
2395 void vmemmap_free(unsigned long start, unsigned long end)
2398 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2400 static void prot_init_common(unsigned long page_none,
2401 unsigned long page_shared,
2402 unsigned long page_copy,
2403 unsigned long page_readonly,
2404 unsigned long page_exec_bit)
2406 PAGE_COPY = __pgprot(page_copy);
2407 PAGE_SHARED = __pgprot(page_shared);
2409 protection_map[0x0] = __pgprot(page_none);
2410 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2411 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2412 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2413 protection_map[0x4] = __pgprot(page_readonly);
2414 protection_map[0x5] = __pgprot(page_readonly);
2415 protection_map[0x6] = __pgprot(page_copy);
2416 protection_map[0x7] = __pgprot(page_copy);
2417 protection_map[0x8] = __pgprot(page_none);
2418 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2419 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2420 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2421 protection_map[0xc] = __pgprot(page_readonly);
2422 protection_map[0xd] = __pgprot(page_readonly);
2423 protection_map[0xe] = __pgprot(page_shared);
2424 protection_map[0xf] = __pgprot(page_shared);
2427 static void __init sun4u_pgprot_init(void)
2429 unsigned long page_none, page_shared, page_copy, page_readonly;
2430 unsigned long page_exec_bit;
2433 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2434 _PAGE_CACHE_4U | _PAGE_P_4U |
2435 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2437 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2438 _PAGE_CACHE_4U | _PAGE_P_4U |
2439 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2440 _PAGE_EXEC_4U | _PAGE_L_4U);
2442 _PAGE_IE = _PAGE_IE_4U;
2443 _PAGE_E = _PAGE_E_4U;
2444 _PAGE_CACHE = _PAGE_CACHE_4U;
2446 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2447 __ACCESS_BITS_4U | _PAGE_E_4U);
2449 #ifdef CONFIG_DEBUG_PAGEALLOC
2450 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2452 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2455 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2456 _PAGE_P_4U | _PAGE_W_4U);
2458 for (i = 1; i < 4; i++)
2459 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2461 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2462 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2463 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2466 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2467 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2468 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2469 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2470 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2471 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2472 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2474 page_exec_bit = _PAGE_EXEC_4U;
2476 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2480 static void __init sun4v_pgprot_init(void)
2482 unsigned long page_none, page_shared, page_copy, page_readonly;
2483 unsigned long page_exec_bit;
2486 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2487 page_cache4v_flag | _PAGE_P_4V |
2488 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2490 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2492 _PAGE_IE = _PAGE_IE_4V;
2493 _PAGE_E = _PAGE_E_4V;
2494 _PAGE_CACHE = page_cache4v_flag;
2496 #ifdef CONFIG_DEBUG_PAGEALLOC
2497 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2499 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2502 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2505 for (i = 1; i < 4; i++)
2506 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2508 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2509 __ACCESS_BITS_4V | _PAGE_E_4V);
2511 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2512 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2513 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2514 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2516 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2517 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2518 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2519 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2520 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2521 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2522 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2524 page_exec_bit = _PAGE_EXEC_4V;
2526 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2530 unsigned long pte_sz_bits(unsigned long sz)
2532 if (tlb_type == hypervisor) {
2536 return _PAGE_SZ8K_4V;
2538 return _PAGE_SZ64K_4V;
2540 return _PAGE_SZ512K_4V;
2541 case 4 * 1024 * 1024:
2542 return _PAGE_SZ4MB_4V;
2548 return _PAGE_SZ8K_4U;
2550 return _PAGE_SZ64K_4U;
2552 return _PAGE_SZ512K_4U;
2553 case 4 * 1024 * 1024:
2554 return _PAGE_SZ4MB_4U;
2559 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2563 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2564 pte_val(pte) |= (((unsigned long)space) << 32);
2565 pte_val(pte) |= pte_sz_bits(page_size);
2570 static unsigned long kern_large_tte(unsigned long paddr)
2574 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2575 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2576 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2577 if (tlb_type == hypervisor)
2578 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2579 page_cache4v_flag | _PAGE_P_4V |
2580 _PAGE_EXEC_4V | _PAGE_W_4V);
2585 /* If not locked, zap it. */
2586 void __flush_tlb_all(void)
2588 unsigned long pstate;
2591 __asm__ __volatile__("flushw\n\t"
2592 "rdpr %%pstate, %0\n\t"
2593 "wrpr %0, %1, %%pstate"
2596 if (tlb_type == hypervisor) {
2597 sun4v_mmu_demap_all();
2598 } else if (tlb_type == spitfire) {
2599 for (i = 0; i < 64; i++) {
2600 /* Spitfire Errata #32 workaround */
2601 /* NOTE: Always runs on spitfire, so no
2602 * cheetah+ page size encodings.
2604 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2608 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2610 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2611 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2614 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2615 spitfire_put_dtlb_data(i, 0x0UL);
2618 /* Spitfire Errata #32 workaround */
2619 /* NOTE: Always runs on spitfire, so no
2620 * cheetah+ page size encodings.
2622 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2626 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2628 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2629 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2632 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2633 spitfire_put_itlb_data(i, 0x0UL);
2636 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2637 cheetah_flush_dtlb_all();
2638 cheetah_flush_itlb_all();
2640 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2644 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2645 unsigned long address)
2647 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2648 __GFP_REPEAT | __GFP_ZERO);
2652 pte = (pte_t *) page_address(page);
2657 pgtable_t pte_alloc_one(struct mm_struct *mm,
2658 unsigned long address)
2660 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2661 __GFP_REPEAT | __GFP_ZERO);
2664 if (!pgtable_page_ctor(page)) {
2665 free_hot_cold_page(page, 0);
2668 return (pte_t *) page_address(page);
2671 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2673 free_page((unsigned long)pte);
2676 static void __pte_free(pgtable_t pte)
2678 struct page *page = virt_to_page(pte);
2680 pgtable_page_dtor(page);
2684 void pte_free(struct mm_struct *mm, pgtable_t pte)
2689 void pgtable_free(void *table, bool is_page)
2694 kmem_cache_free(pgtable_cache, table);
2697 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2698 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2701 unsigned long pte, flags;
2702 struct mm_struct *mm;
2705 if (!pmd_large(entry) || !pmd_young(entry))
2708 pte = pmd_val(entry);
2710 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2711 if (!(pte & _PAGE_VALID))
2714 /* We are fabricating 8MB pages using 4MB real hw pages. */
2715 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2719 spin_lock_irqsave(&mm->context.lock, flags);
2721 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2722 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2725 spin_unlock_irqrestore(&mm->context.lock, flags);
2727 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2729 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2730 static void context_reload(void *__data)
2732 struct mm_struct *mm = __data;
2734 if (mm == current->mm)
2735 load_secondary_context(mm);
2738 void hugetlb_setup(struct pt_regs *regs)
2740 struct mm_struct *mm = current->mm;
2741 struct tsb_config *tp;
2743 if (faulthandler_disabled() || !mm) {
2744 const struct exception_table_entry *entry;
2746 entry = search_exception_tables(regs->tpc);
2748 regs->tpc = entry->fixup;
2749 regs->tnpc = regs->tpc + 4;
2752 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2753 die_if_kernel("HugeTSB in atomic", regs);
2756 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2757 if (likely(tp->tsb == NULL))
2758 tsb_grow(mm, MM_TSB_HUGE, 0);
2760 tsb_context_switch(mm);
2763 /* On UltraSPARC-III+ and later, configure the second half of
2764 * the Data-TLB for huge pages.
2766 if (tlb_type == cheetah_plus) {
2769 spin_lock(&ctx_alloc_lock);
2770 ctx = mm->context.sparc64_ctx_val;
2771 ctx &= ~CTX_PGSZ_MASK;
2772 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2773 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2775 if (ctx != mm->context.sparc64_ctx_val) {
2776 /* When changing the page size fields, we
2777 * must perform a context flush so that no
2778 * stale entries match. This flush must
2779 * occur with the original context register
2782 do_flush_tlb_mm(mm);
2784 /* Reload the context register of all processors
2785 * also executing in this address space.
2787 mm->context.sparc64_ctx_val = ctx;
2788 on_each_cpu(context_reload, mm, 0);
2790 spin_unlock(&ctx_alloc_lock);
2795 static struct resource code_resource = {
2796 .name = "Kernel code",
2797 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
2800 static struct resource data_resource = {
2801 .name = "Kernel data",
2802 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
2805 static struct resource bss_resource = {
2806 .name = "Kernel bss",
2807 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
2810 static inline resource_size_t compute_kern_paddr(void *addr)
2812 return (resource_size_t) (addr - KERNBASE + kern_base);
2815 static void __init kernel_lds_init(void)
2817 code_resource.start = compute_kern_paddr(_text);
2818 code_resource.end = compute_kern_paddr(_etext - 1);
2819 data_resource.start = compute_kern_paddr(_etext);
2820 data_resource.end = compute_kern_paddr(_edata - 1);
2821 bss_resource.start = compute_kern_paddr(__bss_start);
2822 bss_resource.end = compute_kern_paddr(_end - 1);
2825 static int __init report_memory(void)
2828 struct resource *res;
2832 for (i = 0; i < pavail_ents; i++) {
2833 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2836 pr_warn("Failed to allocate source.\n");
2840 res->name = "System RAM";
2841 res->start = pavail[i].phys_addr;
2842 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2843 res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
2845 if (insert_resource(&iomem_resource, res) < 0) {
2846 pr_warn("Resource insertion failed.\n");
2850 insert_resource(res, &code_resource);
2851 insert_resource(res, &data_resource);
2852 insert_resource(res, &bss_resource);
2857 arch_initcall(report_memory);
2860 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2862 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2865 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2867 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2868 if (start < LOW_OBP_ADDRESS) {
2869 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2870 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2872 if (end > HI_OBP_ADDRESS) {
2873 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2874 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2877 flush_tsb_kernel_range(start, end);
2878 do_flush_tlb_kernel_range(start, end);