2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/percpu.h>
26 #include <linux/memblock.h>
27 #include <linux/mmzone.h>
28 #include <linux/gfp.h>
32 #include <asm/pgalloc.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/iommu.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
41 #include <asm/starfire.h>
43 #include <asm/spitfire.h>
44 #include <asm/sections.h>
46 #include <asm/hypervisor.h>
48 #include <asm/mdesc.h>
49 #include <asm/cpudata.h>
54 unsigned long kern_linear_pte_xor[4] __read_mostly;
56 /* A bitmap, two bits for every 256MB of physical memory. These two
57 * bits determine what page size we use for kernel linear
58 * translations. They form an index into kern_linear_pte_xor[]. The
59 * value in the indexed slot is XOR'd with the TLB miss virtual
60 * address to form the resulting TTE. The mapping is:
67 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
68 * support 2GB pages, and hopefully future cpus will support the 16GB
69 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
70 * if these larger page sizes are not supported by the cpu.
72 * It would be nice to determine this from the machine description
73 * 'cpu' properties, but we need to have this table setup before the
74 * MDESC is initialized.
76 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
78 #ifndef CONFIG_DEBUG_PAGEALLOC
79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
80 * Space is allocated for this right after the trap table in
81 * arch/sparc64/kernel/head.S
83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
86 static unsigned long cpu_pgsz_mask;
90 static struct linux_prom64_registers pavail[MAX_BANKS];
91 static int pavail_ents;
93 static int cmp_p64(const void *a, const void *b)
95 const struct linux_prom64_registers *x = a, *y = b;
97 if (x->phys_addr > y->phys_addr)
99 if (x->phys_addr < y->phys_addr)
104 static void __init read_obp_memory(const char *property,
105 struct linux_prom64_registers *regs,
108 phandle node = prom_finddevice("/memory");
109 int prop_size = prom_getproplen(node, property);
112 ents = prop_size / sizeof(struct linux_prom64_registers);
113 if (ents > MAX_BANKS) {
114 prom_printf("The machine has more %s property entries than "
115 "this kernel can support (%d).\n",
116 property, MAX_BANKS);
120 ret = prom_getproperty(node, property, (char *) regs, prop_size);
122 prom_printf("Couldn't get %s property from /memory.\n",
127 /* Sanitize what we got from the firmware, by page aligning
130 for (i = 0; i < ents; i++) {
131 unsigned long base, size;
133 base = regs[i].phys_addr;
134 size = regs[i].reg_size;
137 if (base & ~PAGE_MASK) {
138 unsigned long new_base = PAGE_ALIGN(base);
140 size -= new_base - base;
141 if ((long) size < 0L)
146 /* If it is empty, simply get rid of it.
147 * This simplifies the logic of the other
148 * functions that process these arrays.
150 memmove(®s[i], ®s[i + 1],
151 (ents - i - 1) * sizeof(regs[0]));
156 regs[i].phys_addr = base;
157 regs[i].reg_size = size;
162 sort(regs, ents, sizeof(struct linux_prom64_registers),
166 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
167 sizeof(unsigned long)];
168 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
170 /* Kernel physical address base and size in bytes. */
171 unsigned long kern_base __read_mostly;
172 unsigned long kern_size __read_mostly;
174 /* Initial ramdisk setup */
175 extern unsigned long sparc_ramdisk_image64;
176 extern unsigned int sparc_ramdisk_image;
177 extern unsigned int sparc_ramdisk_size;
179 struct page *mem_map_zero __read_mostly;
180 EXPORT_SYMBOL(mem_map_zero);
182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184 unsigned long sparc64_kern_pri_context __read_mostly;
185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
186 unsigned long sparc64_kern_sec_context __read_mostly;
188 int num_kernel_image_mappings;
190 #ifdef CONFIG_DEBUG_DCFLUSH
191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
197 inline void flush_dcache_page_impl(struct page *page)
199 BUG_ON(tlb_type == hypervisor);
200 #ifdef CONFIG_DEBUG_DCFLUSH
201 atomic_inc(&dcpage_flushes);
204 #ifdef DCACHE_ALIASING_POSSIBLE
205 __flush_dcache_page(page_address(page),
206 ((tlb_type == spitfire) &&
207 page_mapping(page) != NULL));
209 if (page_mapping(page) != NULL &&
210 tlb_type == spitfire)
211 __flush_icache_page(__pa(page_address(page)));
215 #define PG_dcache_dirty PG_arch_1
216 #define PG_dcache_cpu_shift 32UL
217 #define PG_dcache_cpu_mask \
218 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
220 #define dcache_dirty_cpu(page) \
221 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
225 unsigned long mask = this_cpu;
226 unsigned long non_cpu_bits;
228 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
229 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
231 __asm__ __volatile__("1:\n\t"
233 "and %%g7, %1, %%g1\n\t"
234 "or %%g1, %0, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
237 "bne,pn %%xcc, 1b\n\t"
240 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
246 unsigned long mask = (1UL << PG_dcache_dirty);
248 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
251 "srlx %%g7, %4, %%g1\n\t"
252 "and %%g1, %3, %%g1\n\t"
254 "bne,pn %%icc, 2f\n\t"
255 " andn %%g7, %1, %%g1\n\t"
256 "casx [%2], %%g7, %%g1\n\t"
258 "bne,pn %%xcc, 1b\n\t"
262 : "r" (cpu), "r" (mask), "r" (&page->flags),
263 "i" (PG_dcache_cpu_mask),
264 "i" (PG_dcache_cpu_shift)
268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
270 unsigned long tsb_addr = (unsigned long) ent;
272 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
273 tsb_addr = __pa(tsb_addr);
275 __tsb_insert(tsb_addr, tag, pte);
278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
280 static void flush_dcache(unsigned long pfn)
284 page = pfn_to_page(pfn);
286 unsigned long pg_flags;
288 pg_flags = page->flags;
289 if (pg_flags & (1UL << PG_dcache_dirty)) {
290 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
292 int this_cpu = get_cpu();
294 /* This is just to optimize away some function calls
298 flush_dcache_page_impl(page);
300 smp_flush_dcache_page_impl(page, cpu);
302 clear_dcache_dirty_cpu(page, cpu);
309 /* mm->context.lock must be held */
310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
311 unsigned long tsb_hash_shift, unsigned long address,
314 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
320 tsb += ((address >> tsb_hash_shift) &
321 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322 tag = (address >> 22UL);
323 tsb_insert(tsb, tag, tte);
326 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
327 static inline bool is_hugetlb_pte(pte_t pte)
329 if ((tlb_type == hypervisor &&
330 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
331 (tlb_type != hypervisor &&
332 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
338 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
340 struct mm_struct *mm;
344 if (tlb_type != hypervisor) {
345 unsigned long pfn = pte_pfn(pte);
353 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
354 if (!pte_accessible(mm, pte))
357 spin_lock_irqsave(&mm->context.lock, flags);
359 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
360 if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
361 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
362 address, pte_val(pte));
365 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
366 address, pte_val(pte));
368 spin_unlock_irqrestore(&mm->context.lock, flags);
371 void flush_dcache_page(struct page *page)
373 struct address_space *mapping;
376 if (tlb_type == hypervisor)
379 /* Do not bother with the expensive D-cache flush if it
380 * is merely the zero page. The 'bigcore' testcase in GDB
381 * causes this case to run millions of times.
383 if (page == ZERO_PAGE(0))
386 this_cpu = get_cpu();
388 mapping = page_mapping(page);
389 if (mapping && !mapping_mapped(mapping)) {
390 int dirty = test_bit(PG_dcache_dirty, &page->flags);
392 int dirty_cpu = dcache_dirty_cpu(page);
394 if (dirty_cpu == this_cpu)
396 smp_flush_dcache_page_impl(page, dirty_cpu);
398 set_dcache_dirty(page, this_cpu);
400 /* We could delay the flush for the !page_mapping
401 * case too. But that case is for exec env/arg
402 * pages and those are %99 certainly going to get
403 * faulted into the tlb (and thus flushed) anyways.
405 flush_dcache_page_impl(page);
411 EXPORT_SYMBOL(flush_dcache_page);
413 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
415 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
416 if (tlb_type == spitfire) {
419 /* This code only runs on Spitfire cpus so this is
420 * why we can assume _PAGE_PADDR_4U.
422 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
423 unsigned long paddr, mask = _PAGE_PADDR_4U;
425 if (kaddr >= PAGE_OFFSET)
426 paddr = kaddr & mask;
428 pgd_t *pgdp = pgd_offset_k(kaddr);
429 pud_t *pudp = pud_offset(pgdp, kaddr);
430 pmd_t *pmdp = pmd_offset(pudp, kaddr);
431 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
433 paddr = pte_val(*ptep) & mask;
435 __flush_icache_page(paddr);
439 EXPORT_SYMBOL(flush_icache_range);
441 void mmu_info(struct seq_file *m)
443 static const char *pgsz_strings[] = {
444 "8K", "64K", "512K", "4MB", "32MB",
445 "256MB", "2GB", "16GB",
449 if (tlb_type == cheetah)
450 seq_printf(m, "MMU Type\t: Cheetah\n");
451 else if (tlb_type == cheetah_plus)
452 seq_printf(m, "MMU Type\t: Cheetah+\n");
453 else if (tlb_type == spitfire)
454 seq_printf(m, "MMU Type\t: Spitfire\n");
455 else if (tlb_type == hypervisor)
456 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
458 seq_printf(m, "MMU Type\t: ???\n");
460 seq_printf(m, "MMU PGSZs\t: ");
462 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
463 if (cpu_pgsz_mask & (1UL << i)) {
464 seq_printf(m, "%s%s",
465 printed ? "," : "", pgsz_strings[i]);
471 #ifdef CONFIG_DEBUG_DCFLUSH
472 seq_printf(m, "DCPageFlushes\t: %d\n",
473 atomic_read(&dcpage_flushes));
475 seq_printf(m, "DCPageFlushesXC\t: %d\n",
476 atomic_read(&dcpage_flushes_xcall));
477 #endif /* CONFIG_SMP */
478 #endif /* CONFIG_DEBUG_DCFLUSH */
481 struct linux_prom_translation prom_trans[512] __read_mostly;
482 unsigned int prom_trans_ents __read_mostly;
484 unsigned long kern_locked_tte_data;
486 /* The obp translations are saved based on 8k pagesize, since obp can
487 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
488 * HI_OBP_ADDRESS range are handled in ktlb.S.
490 static inline int in_obp_range(unsigned long vaddr)
492 return (vaddr >= LOW_OBP_ADDRESS &&
493 vaddr < HI_OBP_ADDRESS);
496 static int cmp_ptrans(const void *a, const void *b)
498 const struct linux_prom_translation *x = a, *y = b;
500 if (x->virt > y->virt)
502 if (x->virt < y->virt)
507 /* Read OBP translations property into 'prom_trans[]'. */
508 static void __init read_obp_translations(void)
510 int n, node, ents, first, last, i;
512 node = prom_finddevice("/virtual-memory");
513 n = prom_getproplen(node, "translations");
514 if (unlikely(n == 0 || n == -1)) {
515 prom_printf("prom_mappings: Couldn't get size.\n");
518 if (unlikely(n > sizeof(prom_trans))) {
519 prom_printf("prom_mappings: Size %d is too big.\n", n);
523 if ((n = prom_getproperty(node, "translations",
524 (char *)&prom_trans[0],
525 sizeof(prom_trans))) == -1) {
526 prom_printf("prom_mappings: Couldn't get property.\n");
530 n = n / sizeof(struct linux_prom_translation);
534 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
537 /* Now kick out all the non-OBP entries. */
538 for (i = 0; i < ents; i++) {
539 if (in_obp_range(prom_trans[i].virt))
543 for (; i < ents; i++) {
544 if (!in_obp_range(prom_trans[i].virt))
549 for (i = 0; i < (last - first); i++) {
550 struct linux_prom_translation *src = &prom_trans[i + first];
551 struct linux_prom_translation *dest = &prom_trans[i];
555 for (; i < ents; i++) {
556 struct linux_prom_translation *dest = &prom_trans[i];
557 dest->virt = dest->size = dest->data = 0x0UL;
560 prom_trans_ents = last - first;
562 if (tlb_type == spitfire) {
563 /* Clear diag TTE bits. */
564 for (i = 0; i < prom_trans_ents; i++)
565 prom_trans[i].data &= ~0x0003fe0000000000UL;
568 /* Force execute bit on. */
569 for (i = 0; i < prom_trans_ents; i++)
570 prom_trans[i].data |= (tlb_type == hypervisor ?
571 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
574 static void __init hypervisor_tlb_lock(unsigned long vaddr,
578 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
581 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
582 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
587 static unsigned long kern_large_tte(unsigned long paddr);
589 static void __init remap_kernel(void)
591 unsigned long phys_page, tte_vaddr, tte_data;
592 int i, tlb_ent = sparc64_highest_locked_tlbent();
594 tte_vaddr = (unsigned long) KERNBASE;
595 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
596 tte_data = kern_large_tte(phys_page);
598 kern_locked_tte_data = tte_data;
600 /* Now lock us into the TLBs via Hypervisor or OBP. */
601 if (tlb_type == hypervisor) {
602 for (i = 0; i < num_kernel_image_mappings; i++) {
603 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
604 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
605 tte_vaddr += 0x400000;
606 tte_data += 0x400000;
609 for (i = 0; i < num_kernel_image_mappings; i++) {
610 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
611 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
612 tte_vaddr += 0x400000;
613 tte_data += 0x400000;
615 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
617 if (tlb_type == cheetah_plus) {
618 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
619 CTX_CHEETAH_PLUS_NUC);
620 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
621 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
626 static void __init inherit_prom_mappings(void)
628 /* Now fixup OBP's idea about where we really are mapped. */
629 printk("Remapping the kernel... ");
634 void prom_world(int enter)
639 __asm__ __volatile__("flushw");
642 void __flush_dcache_range(unsigned long start, unsigned long end)
646 if (tlb_type == spitfire) {
649 for (va = start; va < end; va += 32) {
650 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
654 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
657 for (va = start; va < end; va += 32)
658 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
662 "i" (ASI_DCACHE_INVALIDATE));
665 EXPORT_SYMBOL(__flush_dcache_range);
667 /* get_new_mmu_context() uses "cache + 1". */
668 DEFINE_SPINLOCK(ctx_alloc_lock);
669 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
670 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
671 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
672 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
674 /* Caller does TLB context flushing on local CPU if necessary.
675 * The caller also ensures that CTX_VALID(mm->context) is false.
677 * We must be careful about boundary cases so that we never
678 * let the user have CTX 0 (nucleus) or we ever use a CTX
679 * version of zero (and thus NO_CONTEXT would not be caught
680 * by version mis-match tests in mmu_context.h).
682 * Always invoked with interrupts disabled.
684 void get_new_mmu_context(struct mm_struct *mm)
686 unsigned long ctx, new_ctx;
687 unsigned long orig_pgsz_bits;
690 spin_lock(&ctx_alloc_lock);
691 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
692 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
693 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
695 if (new_ctx >= (1 << CTX_NR_BITS)) {
696 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
697 if (new_ctx >= ctx) {
699 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
702 new_ctx = CTX_FIRST_VERSION;
704 /* Don't call memset, for 16 entries that's just
707 mmu_context_bmap[0] = 3;
708 mmu_context_bmap[1] = 0;
709 mmu_context_bmap[2] = 0;
710 mmu_context_bmap[3] = 0;
711 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
712 mmu_context_bmap[i + 0] = 0;
713 mmu_context_bmap[i + 1] = 0;
714 mmu_context_bmap[i + 2] = 0;
715 mmu_context_bmap[i + 3] = 0;
721 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
722 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
724 tlb_context_cache = new_ctx;
725 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
726 spin_unlock(&ctx_alloc_lock);
728 if (unlikely(new_version))
729 smp_new_mmu_context_version();
732 static int numa_enabled = 1;
733 static int numa_debug;
735 static int __init early_numa(char *p)
740 if (strstr(p, "off"))
743 if (strstr(p, "debug"))
748 early_param("numa", early_numa);
750 #define numadbg(f, a...) \
751 do { if (numa_debug) \
752 printk(KERN_INFO f, ## a); \
755 static void __init find_ramdisk(unsigned long phys_base)
757 #ifdef CONFIG_BLK_DEV_INITRD
758 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
759 unsigned long ramdisk_image;
761 /* Older versions of the bootloader only supported a
762 * 32-bit physical address for the ramdisk image
763 * location, stored at sparc_ramdisk_image. Newer
764 * SILO versions set sparc_ramdisk_image to zero and
765 * provide a full 64-bit physical address at
766 * sparc_ramdisk_image64.
768 ramdisk_image = sparc_ramdisk_image;
770 ramdisk_image = sparc_ramdisk_image64;
772 /* Another bootloader quirk. The bootloader normalizes
773 * the physical address to KERNBASE, so we have to
774 * factor that back out and add in the lowest valid
775 * physical page address to get the true physical address.
777 ramdisk_image -= KERNBASE;
778 ramdisk_image += phys_base;
780 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
781 ramdisk_image, sparc_ramdisk_size);
783 initrd_start = ramdisk_image;
784 initrd_end = ramdisk_image + sparc_ramdisk_size;
786 memblock_reserve(initrd_start, sparc_ramdisk_size);
788 initrd_start += PAGE_OFFSET;
789 initrd_end += PAGE_OFFSET;
794 struct node_mem_mask {
798 static struct node_mem_mask node_masks[MAX_NUMNODES];
799 static int num_node_masks;
801 int numa_cpu_lookup_table[NR_CPUS];
802 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
804 #ifdef CONFIG_NEED_MULTIPLE_NODES
806 struct mdesc_mblock {
809 u64 offset; /* RA-to-PA */
811 static struct mdesc_mblock *mblocks;
812 static int num_mblocks;
814 static unsigned long ra_to_pa(unsigned long addr)
818 for (i = 0; i < num_mblocks; i++) {
819 struct mdesc_mblock *m = &mblocks[i];
821 if (addr >= m->base &&
822 addr < (m->base + m->size)) {
830 static int find_node(unsigned long addr)
834 addr = ra_to_pa(addr);
835 for (i = 0; i < num_node_masks; i++) {
836 struct node_mem_mask *p = &node_masks[i];
838 if ((addr & p->mask) == p->val)
841 /* The following condition has been observed on LDOM guests.*/
842 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
843 " rule. Some physical memory will be owned by node 0.");
847 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
849 *nid = find_node(start);
851 while (start < end) {
852 int n = find_node(start);
866 /* This must be invoked after performing all of the necessary
867 * memblock_set_node() calls for 'nid'. We need to be able to get
868 * correct data from get_pfn_range_for_nid().
870 static void __init allocate_node_data(int nid)
872 struct pglist_data *p;
873 unsigned long start_pfn, end_pfn;
874 #ifdef CONFIG_NEED_MULTIPLE_NODES
877 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
879 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
882 NODE_DATA(nid) = __va(paddr);
883 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
885 NODE_DATA(nid)->node_id = nid;
890 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
891 p->node_start_pfn = start_pfn;
892 p->node_spanned_pages = end_pfn - start_pfn;
895 static void init_node_masks_nonnuma(void)
899 numadbg("Initializing tables for non-numa.\n");
901 node_masks[0].mask = node_masks[0].val = 0;
904 for (i = 0; i < NR_CPUS; i++)
905 numa_cpu_lookup_table[i] = 0;
907 cpumask_setall(&numa_cpumask_lookup_table[0]);
910 #ifdef CONFIG_NEED_MULTIPLE_NODES
911 struct pglist_data *node_data[MAX_NUMNODES];
913 EXPORT_SYMBOL(numa_cpu_lookup_table);
914 EXPORT_SYMBOL(numa_cpumask_lookup_table);
915 EXPORT_SYMBOL(node_data);
917 struct mdesc_mlgroup {
923 static struct mdesc_mlgroup *mlgroups;
924 static int num_mlgroups;
926 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
931 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
932 u64 target = mdesc_arc_target(md, arc);
935 val = mdesc_get_property(md, target,
937 if (val && *val == cfg_handle)
943 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
946 u64 arc, candidate, best_latency = ~(u64)0;
948 candidate = MDESC_NODE_NULL;
949 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
950 u64 target = mdesc_arc_target(md, arc);
951 const char *name = mdesc_node_name(md, target);
954 if (strcmp(name, "pio-latency-group"))
957 val = mdesc_get_property(md, target, "latency", NULL);
961 if (*val < best_latency) {
967 if (candidate == MDESC_NODE_NULL)
970 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
973 int of_node_to_nid(struct device_node *dp)
975 const struct linux_prom64_registers *regs;
976 struct mdesc_handle *md;
981 /* This is the right thing to do on currently supported
982 * SUN4U NUMA platforms as well, as the PCI controller does
983 * not sit behind any particular memory controller.
988 regs = of_get_property(dp, "reg", NULL);
992 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
998 mdesc_for_each_node_by_name(md, grp, "group") {
999 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1011 static void __init add_node_ranges(void)
1013 struct memblock_region *reg;
1015 for_each_memblock(memory, reg) {
1016 unsigned long size = reg->size;
1017 unsigned long start, end;
1021 while (start < end) {
1022 unsigned long this_end;
1025 this_end = memblock_nid_range(start, end, &nid);
1027 numadbg("Setting memblock NUMA node nid[%d] "
1028 "start[%lx] end[%lx]\n",
1029 nid, start, this_end);
1031 memblock_set_node(start, this_end - start,
1032 &memblock.memory, nid);
1038 static int __init grab_mlgroups(struct mdesc_handle *md)
1040 unsigned long paddr;
1044 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1049 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1054 mlgroups = __va(paddr);
1055 num_mlgroups = count;
1058 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1059 struct mdesc_mlgroup *m = &mlgroups[count++];
1064 val = mdesc_get_property(md, node, "latency", NULL);
1066 val = mdesc_get_property(md, node, "address-match", NULL);
1068 val = mdesc_get_property(md, node, "address-mask", NULL);
1071 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1072 "match[%llx] mask[%llx]\n",
1073 count - 1, m->node, m->latency, m->match, m->mask);
1079 static int __init grab_mblocks(struct mdesc_handle *md)
1081 unsigned long paddr;
1085 mdesc_for_each_node_by_name(md, node, "mblock")
1090 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1095 mblocks = __va(paddr);
1096 num_mblocks = count;
1099 mdesc_for_each_node_by_name(md, node, "mblock") {
1100 struct mdesc_mblock *m = &mblocks[count++];
1103 val = mdesc_get_property(md, node, "base", NULL);
1105 val = mdesc_get_property(md, node, "size", NULL);
1107 val = mdesc_get_property(md, node,
1108 "address-congruence-offset", NULL);
1110 /* The address-congruence-offset property is optional.
1111 * Explicity zero it be identifty this.
1118 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1119 count - 1, m->base, m->size, m->offset);
1125 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1126 u64 grp, cpumask_t *mask)
1130 cpumask_clear(mask);
1132 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1133 u64 target = mdesc_arc_target(md, arc);
1134 const char *name = mdesc_node_name(md, target);
1137 if (strcmp(name, "cpu"))
1139 id = mdesc_get_property(md, target, "id", NULL);
1140 if (*id < nr_cpu_ids)
1141 cpumask_set_cpu(*id, mask);
1145 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1149 for (i = 0; i < num_mlgroups; i++) {
1150 struct mdesc_mlgroup *m = &mlgroups[i];
1151 if (m->node == node)
1157 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1160 struct mdesc_mlgroup *candidate = NULL;
1161 u64 arc, best_latency = ~(u64)0;
1162 struct node_mem_mask *n;
1164 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1165 u64 target = mdesc_arc_target(md, arc);
1166 struct mdesc_mlgroup *m = find_mlgroup(target);
1169 if (m->latency < best_latency) {
1171 best_latency = m->latency;
1177 if (num_node_masks != index) {
1178 printk(KERN_ERR "Inconsistent NUMA state, "
1179 "index[%d] != num_node_masks[%d]\n",
1180 index, num_node_masks);
1184 n = &node_masks[num_node_masks++];
1186 n->mask = candidate->mask;
1187 n->val = candidate->match;
1189 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1190 index, n->mask, n->val, candidate->latency);
1195 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1201 numa_parse_mdesc_group_cpus(md, grp, &mask);
1203 for_each_cpu(cpu, &mask)
1204 numa_cpu_lookup_table[cpu] = index;
1205 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1208 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1209 for_each_cpu(cpu, &mask)
1214 return numa_attach_mlgroup(md, grp, index);
1217 static int __init numa_parse_mdesc(void)
1219 struct mdesc_handle *md = mdesc_grab();
1223 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1224 if (node == MDESC_NODE_NULL) {
1229 err = grab_mblocks(md);
1233 err = grab_mlgroups(md);
1238 mdesc_for_each_node_by_name(md, node, "group") {
1239 err = numa_parse_mdesc_group(md, node, count);
1247 for (i = 0; i < num_node_masks; i++) {
1248 allocate_node_data(i);
1258 static int __init numa_parse_jbus(void)
1260 unsigned long cpu, index;
1262 /* NUMA node id is encoded in bits 36 and higher, and there is
1263 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1266 for_each_present_cpu(cpu) {
1267 numa_cpu_lookup_table[cpu] = index;
1268 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1269 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1270 node_masks[index].val = cpu << 36UL;
1274 num_node_masks = index;
1278 for (index = 0; index < num_node_masks; index++) {
1279 allocate_node_data(index);
1280 node_set_online(index);
1286 static int __init numa_parse_sun4u(void)
1288 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1291 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1292 if ((ver >> 32UL) == __JALAPENO_ID ||
1293 (ver >> 32UL) == __SERRANO_ID)
1294 return numa_parse_jbus();
1299 static int __init bootmem_init_numa(void)
1303 numadbg("bootmem_init_numa()\n");
1306 if (tlb_type == hypervisor)
1307 err = numa_parse_mdesc();
1309 err = numa_parse_sun4u();
1316 static int bootmem_init_numa(void)
1323 static void __init bootmem_init_nonnuma(void)
1325 unsigned long top_of_ram = memblock_end_of_DRAM();
1326 unsigned long total_ram = memblock_phys_mem_size();
1328 numadbg("bootmem_init_nonnuma()\n");
1330 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1331 top_of_ram, total_ram);
1332 printk(KERN_INFO "Memory hole size: %ldMB\n",
1333 (top_of_ram - total_ram) >> 20);
1335 init_node_masks_nonnuma();
1336 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1337 allocate_node_data(0);
1341 static unsigned long __init bootmem_init(unsigned long phys_base)
1343 unsigned long end_pfn;
1345 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1346 max_pfn = max_low_pfn = end_pfn;
1347 min_low_pfn = (phys_base >> PAGE_SHIFT);
1349 if (bootmem_init_numa() < 0)
1350 bootmem_init_nonnuma();
1352 /* Dump memblock with node info. */
1353 memblock_dump_all();
1355 /* XXX cpu notifier XXX */
1357 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1363 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1364 static int pall_ents __initdata;
1366 #ifdef CONFIG_DEBUG_PAGEALLOC
1367 static unsigned long __ref kernel_map_range(unsigned long pstart,
1368 unsigned long pend, pgprot_t prot)
1370 unsigned long vstart = PAGE_OFFSET + pstart;
1371 unsigned long vend = PAGE_OFFSET + pend;
1372 unsigned long alloc_bytes = 0UL;
1374 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1375 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1380 while (vstart < vend) {
1381 unsigned long this_end, paddr = __pa(vstart);
1382 pgd_t *pgd = pgd_offset_k(vstart);
1387 if (pgd_none(*pgd)) {
1390 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1391 alloc_bytes += PAGE_SIZE;
1392 pgd_populate(&init_mm, pgd, new);
1394 pud = pud_offset(pgd, vstart);
1395 if (pud_none(*pud)) {
1398 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1399 alloc_bytes += PAGE_SIZE;
1400 pud_populate(&init_mm, pud, new);
1403 pmd = pmd_offset(pud, vstart);
1404 if (!pmd_present(*pmd)) {
1407 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1408 alloc_bytes += PAGE_SIZE;
1409 pmd_populate_kernel(&init_mm, pmd, new);
1412 pte = pte_offset_kernel(pmd, vstart);
1413 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1414 if (this_end > vend)
1417 while (vstart < this_end) {
1418 pte_val(*pte) = (paddr | pgprot_val(prot));
1420 vstart += PAGE_SIZE;
1429 extern unsigned int kvmap_linear_patch[1];
1430 #endif /* CONFIG_DEBUG_PAGEALLOC */
1432 static void __init kpte_set_val(unsigned long index, unsigned long val)
1434 unsigned long *ptr = kpte_linear_bitmap;
1436 val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1437 ptr += (index / (BITS_PER_LONG / 2));
1442 static const unsigned long kpte_shift_min = 28; /* 256MB */
1443 static const unsigned long kpte_shift_max = 34; /* 16GB */
1444 static const unsigned long kpte_shift_incr = 3;
1446 static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1447 unsigned long shift)
1449 unsigned long size = (1UL << shift);
1450 unsigned long mask = (size - 1UL);
1451 unsigned long remains = end - start;
1454 if (remains < size || (start & mask))
1459 * shift 28 --> kern_linear_pte_xor index 1
1460 * shift 31 --> kern_linear_pte_xor index 2
1461 * shift 34 --> kern_linear_pte_xor index 3
1463 val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1466 if (shift != kpte_shift_max)
1470 unsigned long index = start >> kpte_shift_min;
1472 kpte_set_val(index, val);
1474 start += 1UL << kpte_shift_min;
1475 remains -= 1UL << kpte_shift_min;
1481 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1483 unsigned long smallest_size, smallest_mask;
1486 smallest_size = (1UL << kpte_shift_min);
1487 smallest_mask = (smallest_size - 1UL);
1489 while (start < end) {
1490 unsigned long orig_start = start;
1492 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1493 start = kpte_mark_using_shift(start, end, s);
1495 if (start != orig_start)
1499 if (start == orig_start)
1500 start = (start + smallest_size) & ~smallest_mask;
1504 static void __init init_kpte_bitmap(void)
1508 for (i = 0; i < pall_ents; i++) {
1509 unsigned long phys_start, phys_end;
1511 phys_start = pall[i].phys_addr;
1512 phys_end = phys_start + pall[i].reg_size;
1514 mark_kpte_bitmap(phys_start, phys_end);
1518 static void __init kernel_physical_mapping_init(void)
1520 #ifdef CONFIG_DEBUG_PAGEALLOC
1521 unsigned long i, mem_alloced = 0UL;
1523 for (i = 0; i < pall_ents; i++) {
1524 unsigned long phys_start, phys_end;
1526 phys_start = pall[i].phys_addr;
1527 phys_end = phys_start + pall[i].reg_size;
1529 mem_alloced += kernel_map_range(phys_start, phys_end,
1533 printk("Allocated %ld bytes for kernel page tables.\n",
1536 kvmap_linear_patch[0] = 0x01000000; /* nop */
1537 flushi(&kvmap_linear_patch[0]);
1543 #ifdef CONFIG_DEBUG_PAGEALLOC
1544 void kernel_map_pages(struct page *page, int numpages, int enable)
1546 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1547 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1549 kernel_map_range(phys_start, phys_end,
1550 (enable ? PAGE_KERNEL : __pgprot(0)));
1552 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1553 PAGE_OFFSET + phys_end);
1555 /* we should perform an IPI and flush all tlbs,
1556 * but that can deadlock->flush only current cpu.
1558 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1559 PAGE_OFFSET + phys_end);
1563 unsigned long __init find_ecache_flush_span(unsigned long size)
1567 for (i = 0; i < pavail_ents; i++) {
1568 if (pavail[i].reg_size >= size)
1569 return pavail[i].phys_addr;
1575 unsigned long PAGE_OFFSET;
1576 EXPORT_SYMBOL(PAGE_OFFSET);
1578 static void __init page_offset_shift_patch_one(unsigned int *insn, unsigned long phys_bits)
1580 unsigned long final_shift;
1581 unsigned int val = *insn;
1584 /* We are patching in ilog2(max_supported_phys_address), and
1585 * we are doing so in a manner similar to a relocation addend.
1586 * That is, we are adding the shift value to whatever value
1587 * is in the shift instruction count field already.
1592 /* If we are trying to shift >= 64 bits, clear the destination
1593 * register. This can happen when phys_bits ends up being equal
1594 * to MAX_PHYS_ADDRESS_BITS.
1596 final_shift = (cnt + (64 - phys_bits));
1597 if (final_shift >= 64) {
1598 unsigned int rd = (val >> 25) & 0x1f;
1600 val = 0x80100000 | (rd << 25);
1606 __asm__ __volatile__("flush %0"
1611 static void __init page_offset_shift_patch(unsigned long phys_bits)
1613 extern unsigned int __page_offset_shift_patch;
1614 extern unsigned int __page_offset_shift_patch_end;
1617 p = &__page_offset_shift_patch;
1618 while (p < &__page_offset_shift_patch_end) {
1619 unsigned int *insn = (unsigned int *)(unsigned long)*p;
1621 page_offset_shift_patch_one(insn, phys_bits);
1627 static void __init setup_page_offset(void)
1629 unsigned long max_phys_bits = 40;
1631 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1633 } else if (tlb_type == hypervisor) {
1634 switch (sun4v_chip_type) {
1635 case SUN4V_CHIP_NIAGARA1:
1636 case SUN4V_CHIP_NIAGARA2:
1639 case SUN4V_CHIP_NIAGARA3:
1642 case SUN4V_CHIP_NIAGARA4:
1643 case SUN4V_CHIP_NIAGARA5:
1644 case SUN4V_CHIP_SPARC64X:
1651 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1652 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1657 PAGE_OFFSET = PAGE_OFFSET_BY_BITS(max_phys_bits);
1659 pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1660 PAGE_OFFSET, max_phys_bits);
1662 page_offset_shift_patch(max_phys_bits);
1665 static void __init tsb_phys_patch(void)
1667 struct tsb_ldquad_phys_patch_entry *pquad;
1668 struct tsb_phys_patch_entry *p;
1670 pquad = &__tsb_ldquad_phys_patch;
1671 while (pquad < &__tsb_ldquad_phys_patch_end) {
1672 unsigned long addr = pquad->addr;
1674 if (tlb_type == hypervisor)
1675 *(unsigned int *) addr = pquad->sun4v_insn;
1677 *(unsigned int *) addr = pquad->sun4u_insn;
1679 __asm__ __volatile__("flush %0"
1686 p = &__tsb_phys_patch;
1687 while (p < &__tsb_phys_patch_end) {
1688 unsigned long addr = p->addr;
1690 *(unsigned int *) addr = p->insn;
1692 __asm__ __volatile__("flush %0"
1700 /* Don't mark as init, we give this to the Hypervisor. */
1701 #ifndef CONFIG_DEBUG_PAGEALLOC
1702 #define NUM_KTSB_DESCR 2
1704 #define NUM_KTSB_DESCR 1
1706 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1707 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1709 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1711 pa >>= KTSB_PHYS_SHIFT;
1713 while (start < end) {
1714 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1716 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1717 __asm__ __volatile__("flush %0" : : "r" (ia));
1719 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1720 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1726 static void ktsb_phys_patch(void)
1728 extern unsigned int __swapper_tsb_phys_patch;
1729 extern unsigned int __swapper_tsb_phys_patch_end;
1730 unsigned long ktsb_pa;
1732 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1733 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1734 &__swapper_tsb_phys_patch_end, ktsb_pa);
1735 #ifndef CONFIG_DEBUG_PAGEALLOC
1737 extern unsigned int __swapper_4m_tsb_phys_patch;
1738 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1739 ktsb_pa = (kern_base +
1740 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1741 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1742 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1747 static void __init sun4v_ktsb_init(void)
1749 unsigned long ktsb_pa;
1751 /* First KTSB for PAGE_SIZE mappings. */
1752 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1754 switch (PAGE_SIZE) {
1757 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1758 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1762 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1763 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1767 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1768 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1771 case 4 * 1024 * 1024:
1772 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1773 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1777 ktsb_descr[0].assoc = 1;
1778 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1779 ktsb_descr[0].ctx_idx = 0;
1780 ktsb_descr[0].tsb_base = ktsb_pa;
1781 ktsb_descr[0].resv = 0;
1783 #ifndef CONFIG_DEBUG_PAGEALLOC
1784 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1785 ktsb_pa = (kern_base +
1786 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1788 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1789 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1790 HV_PGSZ_MASK_256MB |
1792 HV_PGSZ_MASK_16GB) &
1794 ktsb_descr[1].assoc = 1;
1795 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1796 ktsb_descr[1].ctx_idx = 0;
1797 ktsb_descr[1].tsb_base = ktsb_pa;
1798 ktsb_descr[1].resv = 0;
1802 void sun4v_ktsb_register(void)
1804 unsigned long pa, ret;
1806 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1808 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1810 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1811 "errors with %lx\n", pa, ret);
1816 static void __init sun4u_linear_pte_xor_finalize(void)
1818 #ifndef CONFIG_DEBUG_PAGEALLOC
1819 /* This is where we would add Panther support for
1820 * 32MB and 256MB pages.
1825 static void __init sun4v_linear_pte_xor_finalize(void)
1827 #ifndef CONFIG_DEBUG_PAGEALLOC
1828 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1829 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1831 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1832 _PAGE_P_4V | _PAGE_W_4V);
1834 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1837 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1838 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1840 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1841 _PAGE_P_4V | _PAGE_W_4V);
1843 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1846 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1847 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1849 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1850 _PAGE_P_4V | _PAGE_W_4V);
1852 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1857 /* paging_init() sets up the page tables */
1859 static unsigned long last_valid_pfn;
1861 /* These must be page aligned in order to not trigger the
1862 * alignment tests of pgd_bad() and pud_bad().
1864 pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned (PAGE_SIZE)));
1865 static pud_t swapper_pud_dir[PTRS_PER_PUD] __attribute__ ((aligned (PAGE_SIZE)));
1867 static void sun4u_pgprot_init(void);
1868 static void sun4v_pgprot_init(void);
1870 void __init paging_init(void)
1872 unsigned long end_pfn, shift, phys_base;
1873 unsigned long real_end, i;
1878 setup_page_offset();
1880 /* These build time checkes make sure that the dcache_dirty_cpu()
1881 * page->flags usage will work.
1883 * When a page gets marked as dcache-dirty, we store the
1884 * cpu number starting at bit 32 in the page->flags. Also,
1885 * functions like clear_dcache_dirty_cpu use the cpu mask
1886 * in 13-bit signed-immediate instruction fields.
1890 * Page flags must not reach into upper 32 bits that are used
1891 * for the cpu number
1893 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1896 * The bit fields placed in the high range must not reach below
1897 * the 32 bit boundary. Otherwise we cannot place the cpu field
1898 * at the 32 bit boundary.
1900 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1901 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1903 BUILD_BUG_ON(NR_CPUS > 4096);
1905 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
1906 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1908 /* Invalidate both kernel TSBs. */
1909 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1910 #ifndef CONFIG_DEBUG_PAGEALLOC
1911 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1914 if (tlb_type == hypervisor)
1915 sun4v_pgprot_init();
1917 sun4u_pgprot_init();
1919 if (tlb_type == cheetah_plus ||
1920 tlb_type == hypervisor) {
1925 if (tlb_type == hypervisor)
1926 sun4v_patch_tlb_handlers();
1928 /* Find available physical memory...
1930 * Read it twice in order to work around a bug in openfirmware.
1931 * The call to grab this table itself can cause openfirmware to
1932 * allocate memory, which in turn can take away some space from
1933 * the list of available memory. Reading it twice makes sure
1934 * we really do get the final value.
1936 read_obp_translations();
1937 read_obp_memory("reg", &pall[0], &pall_ents);
1938 read_obp_memory("available", &pavail[0], &pavail_ents);
1939 read_obp_memory("available", &pavail[0], &pavail_ents);
1941 phys_base = 0xffffffffffffffffUL;
1942 for (i = 0; i < pavail_ents; i++) {
1943 phys_base = min(phys_base, pavail[i].phys_addr);
1944 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1947 memblock_reserve(kern_base, kern_size);
1949 find_ramdisk(phys_base);
1951 memblock_enforce_memory_limit(cmdline_memory_size);
1953 memblock_allow_resize();
1954 memblock_dump_all();
1956 set_bit(0, mmu_context_bmap);
1958 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1960 real_end = (unsigned long)_end;
1961 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
1962 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1963 num_kernel_image_mappings);
1965 /* Set kernel pgd to upper alias so physical page computations
1968 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1970 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1972 /* The kernel page tables we publish into what the rest of the
1973 * world sees must be adjusted so that they see the PAGE_OFFSET
1974 * address of these in-kerenel data structures. However right
1975 * here we must access them from the kernel image side, because
1976 * the trap tables haven't been taken over and therefore we cannot
1977 * take TLB misses in the PAGE_OFFSET linear mappings yet.
1979 pud = swapper_pud_dir + (shift / sizeof(pud_t));
1980 pgd_set(&swapper_pg_dir[0], pud);
1982 pmd = swapper_low_pmd_dir + (shift / sizeof(pmd_t));
1983 pud_set(&swapper_pud_dir[0], pmd);
1985 inherit_prom_mappings();
1989 /* Ok, we can use our TLB miss and window trap handlers safely. */
1994 prom_build_devicetree();
1995 of_populate_present_mask();
1997 of_fill_in_cpu_data();
2000 if (tlb_type == hypervisor) {
2002 mdesc_populate_present_mask(cpu_all_mask);
2004 mdesc_fill_in_cpu_data(cpu_all_mask);
2006 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2008 sun4v_linear_pte_xor_finalize();
2011 sun4v_ktsb_register();
2013 unsigned long impl, ver;
2015 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2016 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2018 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2019 impl = ((ver >> 32) & 0xffff);
2020 if (impl == PANTHER_IMPL)
2021 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2022 HV_PGSZ_MASK_256MB);
2024 sun4u_linear_pte_xor_finalize();
2027 /* Flush the TLBs and the 4M TSB so that the updated linear
2028 * pte XOR settings are realized for all mappings.
2031 #ifndef CONFIG_DEBUG_PAGEALLOC
2032 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2036 /* Setup bootmem... */
2037 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2039 /* Once the OF device tree and MDESC have been setup, we know
2040 * the list of possible cpus. Therefore we can allocate the
2043 for_each_possible_cpu(i) {
2044 node = cpu_to_node(i);
2046 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2049 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2054 kernel_physical_mapping_init();
2057 unsigned long max_zone_pfns[MAX_NR_ZONES];
2059 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2061 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2063 free_area_init_nodes(max_zone_pfns);
2066 printk("Booting Linux...\n");
2069 int page_in_phys_avail(unsigned long paddr)
2075 for (i = 0; i < pavail_ents; i++) {
2076 unsigned long start, end;
2078 start = pavail[i].phys_addr;
2079 end = start + pavail[i].reg_size;
2081 if (paddr >= start && paddr < end)
2084 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2086 #ifdef CONFIG_BLK_DEV_INITRD
2087 if (paddr >= __pa(initrd_start) &&
2088 paddr < __pa(PAGE_ALIGN(initrd_end)))
2095 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
2096 static int pavail_rescan_ents __initdata;
2098 /* Certain OBP calls, such as fetching "available" properties, can
2099 * claim physical memory. So, along with initializing the valid
2100 * address bitmap, what we do here is refetch the physical available
2101 * memory list again, and make sure it provides at least as much
2102 * memory as 'pavail' does.
2104 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
2108 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
2110 for (i = 0; i < pavail_ents; i++) {
2111 unsigned long old_start, old_end;
2113 old_start = pavail[i].phys_addr;
2114 old_end = old_start + pavail[i].reg_size;
2115 while (old_start < old_end) {
2118 for (n = 0; n < pavail_rescan_ents; n++) {
2119 unsigned long new_start, new_end;
2121 new_start = pavail_rescan[n].phys_addr;
2122 new_end = new_start +
2123 pavail_rescan[n].reg_size;
2125 if (new_start <= old_start &&
2126 new_end >= (old_start + PAGE_SIZE)) {
2127 set_bit(old_start >> ILOG2_4MB, bitmap);
2132 prom_printf("mem_init: Lost memory in pavail\n");
2133 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2134 pavail[i].phys_addr,
2135 pavail[i].reg_size);
2136 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2137 pavail_rescan[i].phys_addr,
2138 pavail_rescan[i].reg_size);
2139 prom_printf("mem_init: Cannot continue, aborting.\n");
2143 old_start += PAGE_SIZE;
2148 static void __init patch_tlb_miss_handler_bitmap(void)
2150 extern unsigned int valid_addr_bitmap_insn[];
2151 extern unsigned int valid_addr_bitmap_patch[];
2153 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2155 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2156 flushi(&valid_addr_bitmap_insn[0]);
2159 static void __init register_page_bootmem_info(void)
2161 #ifdef CONFIG_NEED_MULTIPLE_NODES
2164 for_each_online_node(i)
2165 if (NODE_DATA(i)->node_spanned_pages)
2166 register_page_bootmem_info_node(NODE_DATA(i));
2169 void __init mem_init(void)
2171 unsigned long addr, last;
2173 addr = PAGE_OFFSET + kern_base;
2174 last = PAGE_ALIGN(kern_size) + addr;
2175 while (addr < last) {
2176 set_bit(__pa(addr) >> ILOG2_4MB, sparc64_valid_addr_bitmap);
2180 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2181 patch_tlb_miss_handler_bitmap();
2183 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2185 register_page_bootmem_info();
2189 * Set up the zero page, mark it reserved, so that page count
2190 * is not manipulated when freeing the page from user ptes.
2192 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2193 if (mem_map_zero == NULL) {
2194 prom_printf("paging_init: Cannot alloc zero page.\n");
2197 mark_page_reserved(mem_map_zero);
2199 mem_init_print_info(NULL);
2201 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2202 cheetah_ecache_flush_init();
2205 void free_initmem(void)
2207 unsigned long addr, initend;
2210 /* If the physical memory maps were trimmed by kernel command
2211 * line options, don't even try freeing this initmem stuff up.
2212 * The kernel image could have been in the trimmed out region
2213 * and if so the freeing below will free invalid page structs.
2215 if (cmdline_memory_size)
2219 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2221 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2222 initend = (unsigned long)(__init_end) & PAGE_MASK;
2223 for (; addr < initend; addr += PAGE_SIZE) {
2227 ((unsigned long) __va(kern_base)) -
2228 ((unsigned long) KERNBASE));
2229 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2232 free_reserved_page(virt_to_page(page));
2236 #ifdef CONFIG_BLK_DEV_INITRD
2237 void free_initrd_mem(unsigned long start, unsigned long end)
2239 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2244 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2245 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2246 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2247 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2248 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2249 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2251 pgprot_t PAGE_KERNEL __read_mostly;
2252 EXPORT_SYMBOL(PAGE_KERNEL);
2254 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2255 pgprot_t PAGE_COPY __read_mostly;
2257 pgprot_t PAGE_SHARED __read_mostly;
2258 EXPORT_SYMBOL(PAGE_SHARED);
2260 unsigned long pg_iobits __read_mostly;
2262 unsigned long _PAGE_IE __read_mostly;
2263 EXPORT_SYMBOL(_PAGE_IE);
2265 unsigned long _PAGE_E __read_mostly;
2266 EXPORT_SYMBOL(_PAGE_E);
2268 unsigned long _PAGE_CACHE __read_mostly;
2269 EXPORT_SYMBOL(_PAGE_CACHE);
2271 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2272 unsigned long vmemmap_table[VMEMMAP_SIZE];
2274 static long __meminitdata addr_start, addr_end;
2275 static int __meminitdata node_start;
2277 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2280 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2281 unsigned long phys_end = (vend - VMEMMAP_BASE);
2282 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2283 unsigned long end = VMEMMAP_ALIGN(phys_end);
2284 unsigned long pte_base;
2286 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2287 _PAGE_CP_4U | _PAGE_CV_4U |
2288 _PAGE_P_4U | _PAGE_W_4U);
2289 if (tlb_type == hypervisor)
2290 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2291 _PAGE_CP_4V | _PAGE_CV_4V |
2292 _PAGE_P_4V | _PAGE_W_4V);
2294 for (; addr < end; addr += VMEMMAP_CHUNK) {
2295 unsigned long *vmem_pp =
2296 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2299 if (!(*vmem_pp & _PAGE_VALID)) {
2300 block = vmemmap_alloc_block(1UL << ILOG2_4MB, node);
2304 *vmem_pp = pte_base | __pa(block);
2306 /* check to see if we have contiguous blocks */
2307 if (addr_end != addr || node_start != node) {
2309 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2310 addr_start, addr_end-1, node_start);
2314 addr_end = addr + VMEMMAP_CHUNK;
2320 void __meminit vmemmap_populate_print_last(void)
2323 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2324 addr_start, addr_end-1, node_start);
2331 void vmemmap_free(unsigned long start, unsigned long end)
2335 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2337 static void prot_init_common(unsigned long page_none,
2338 unsigned long page_shared,
2339 unsigned long page_copy,
2340 unsigned long page_readonly,
2341 unsigned long page_exec_bit)
2343 PAGE_COPY = __pgprot(page_copy);
2344 PAGE_SHARED = __pgprot(page_shared);
2346 protection_map[0x0] = __pgprot(page_none);
2347 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2348 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2349 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2350 protection_map[0x4] = __pgprot(page_readonly);
2351 protection_map[0x5] = __pgprot(page_readonly);
2352 protection_map[0x6] = __pgprot(page_copy);
2353 protection_map[0x7] = __pgprot(page_copy);
2354 protection_map[0x8] = __pgprot(page_none);
2355 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2356 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2357 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2358 protection_map[0xc] = __pgprot(page_readonly);
2359 protection_map[0xd] = __pgprot(page_readonly);
2360 protection_map[0xe] = __pgprot(page_shared);
2361 protection_map[0xf] = __pgprot(page_shared);
2364 static void __init sun4u_pgprot_init(void)
2366 unsigned long page_none, page_shared, page_copy, page_readonly;
2367 unsigned long page_exec_bit;
2370 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2371 _PAGE_CACHE_4U | _PAGE_P_4U |
2372 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2374 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2375 _PAGE_CACHE_4U | _PAGE_P_4U |
2376 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2377 _PAGE_EXEC_4U | _PAGE_L_4U);
2379 _PAGE_IE = _PAGE_IE_4U;
2380 _PAGE_E = _PAGE_E_4U;
2381 _PAGE_CACHE = _PAGE_CACHE_4U;
2383 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2384 __ACCESS_BITS_4U | _PAGE_E_4U);
2386 #ifdef CONFIG_DEBUG_PAGEALLOC
2387 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2389 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2392 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2393 _PAGE_P_4U | _PAGE_W_4U);
2395 for (i = 1; i < 4; i++)
2396 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2398 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2399 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2400 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2403 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2404 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2405 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2406 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2407 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2408 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2409 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2411 page_exec_bit = _PAGE_EXEC_4U;
2413 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2417 static void __init sun4v_pgprot_init(void)
2419 unsigned long page_none, page_shared, page_copy, page_readonly;
2420 unsigned long page_exec_bit;
2423 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2424 _PAGE_CACHE_4V | _PAGE_P_4V |
2425 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2427 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2429 _PAGE_IE = _PAGE_IE_4V;
2430 _PAGE_E = _PAGE_E_4V;
2431 _PAGE_CACHE = _PAGE_CACHE_4V;
2433 #ifdef CONFIG_DEBUG_PAGEALLOC
2434 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2436 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2439 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2440 _PAGE_P_4V | _PAGE_W_4V);
2442 for (i = 1; i < 4; i++)
2443 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2445 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2446 __ACCESS_BITS_4V | _PAGE_E_4V);
2448 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2449 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2450 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2451 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2453 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2454 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2455 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2456 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2457 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2458 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2459 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2461 page_exec_bit = _PAGE_EXEC_4V;
2463 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2467 unsigned long pte_sz_bits(unsigned long sz)
2469 if (tlb_type == hypervisor) {
2473 return _PAGE_SZ8K_4V;
2475 return _PAGE_SZ64K_4V;
2477 return _PAGE_SZ512K_4V;
2478 case 4 * 1024 * 1024:
2479 return _PAGE_SZ4MB_4V;
2485 return _PAGE_SZ8K_4U;
2487 return _PAGE_SZ64K_4U;
2489 return _PAGE_SZ512K_4U;
2490 case 4 * 1024 * 1024:
2491 return _PAGE_SZ4MB_4U;
2496 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2500 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2501 pte_val(pte) |= (((unsigned long)space) << 32);
2502 pte_val(pte) |= pte_sz_bits(page_size);
2507 static unsigned long kern_large_tte(unsigned long paddr)
2511 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2512 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2513 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2514 if (tlb_type == hypervisor)
2515 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2516 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2517 _PAGE_EXEC_4V | _PAGE_W_4V);
2522 /* If not locked, zap it. */
2523 void __flush_tlb_all(void)
2525 unsigned long pstate;
2528 __asm__ __volatile__("flushw\n\t"
2529 "rdpr %%pstate, %0\n\t"
2530 "wrpr %0, %1, %%pstate"
2533 if (tlb_type == hypervisor) {
2534 sun4v_mmu_demap_all();
2535 } else if (tlb_type == spitfire) {
2536 for (i = 0; i < 64; i++) {
2537 /* Spitfire Errata #32 workaround */
2538 /* NOTE: Always runs on spitfire, so no
2539 * cheetah+ page size encodings.
2541 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2545 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2547 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2548 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2551 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2552 spitfire_put_dtlb_data(i, 0x0UL);
2555 /* Spitfire Errata #32 workaround */
2556 /* NOTE: Always runs on spitfire, so no
2557 * cheetah+ page size encodings.
2559 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2563 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2565 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2566 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2569 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2570 spitfire_put_itlb_data(i, 0x0UL);
2573 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2574 cheetah_flush_dtlb_all();
2575 cheetah_flush_itlb_all();
2577 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2581 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2582 unsigned long address)
2584 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2585 __GFP_REPEAT | __GFP_ZERO);
2589 pte = (pte_t *) page_address(page);
2594 pgtable_t pte_alloc_one(struct mm_struct *mm,
2595 unsigned long address)
2597 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2598 __GFP_REPEAT | __GFP_ZERO);
2601 if (!pgtable_page_ctor(page)) {
2602 free_hot_cold_page(page, 0);
2605 return (pte_t *) page_address(page);
2608 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2610 free_page((unsigned long)pte);
2613 static void __pte_free(pgtable_t pte)
2615 struct page *page = virt_to_page(pte);
2617 pgtable_page_dtor(page);
2621 void pte_free(struct mm_struct *mm, pgtable_t pte)
2626 void pgtable_free(void *table, bool is_page)
2631 kmem_cache_free(pgtable_cache, table);
2634 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2635 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2638 unsigned long pte, flags;
2639 struct mm_struct *mm;
2642 if (!pmd_large(entry) || !pmd_young(entry))
2645 pte = pmd_val(entry);
2647 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2648 if (!(pte & _PAGE_VALID))
2651 /* We are fabricating 8MB pages using 4MB real hw pages. */
2652 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2656 spin_lock_irqsave(&mm->context.lock, flags);
2658 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2659 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2662 spin_unlock_irqrestore(&mm->context.lock, flags);
2664 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2666 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2667 static void context_reload(void *__data)
2669 struct mm_struct *mm = __data;
2671 if (mm == current->mm)
2672 load_secondary_context(mm);
2675 void hugetlb_setup(struct pt_regs *regs)
2677 struct mm_struct *mm = current->mm;
2678 struct tsb_config *tp;
2680 if (in_atomic() || !mm) {
2681 const struct exception_table_entry *entry;
2683 entry = search_exception_tables(regs->tpc);
2685 regs->tpc = entry->fixup;
2686 regs->tnpc = regs->tpc + 4;
2689 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2690 die_if_kernel("HugeTSB in atomic", regs);
2693 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2694 if (likely(tp->tsb == NULL))
2695 tsb_grow(mm, MM_TSB_HUGE, 0);
2697 tsb_context_switch(mm);
2700 /* On UltraSPARC-III+ and later, configure the second half of
2701 * the Data-TLB for huge pages.
2703 if (tlb_type == cheetah_plus) {
2706 spin_lock(&ctx_alloc_lock);
2707 ctx = mm->context.sparc64_ctx_val;
2708 ctx &= ~CTX_PGSZ_MASK;
2709 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2710 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2712 if (ctx != mm->context.sparc64_ctx_val) {
2713 /* When changing the page size fields, we
2714 * must perform a context flush so that no
2715 * stale entries match. This flush must
2716 * occur with the original context register
2719 do_flush_tlb_mm(mm);
2721 /* Reload the context register of all processors
2722 * also executing in this address space.
2724 mm->context.sparc64_ctx_val = ctx;
2725 on_each_cpu(context_reload, mm, 0);
2727 spin_unlock(&ctx_alloc_lock);
2733 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2735 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2738 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2740 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2741 if (start < LOW_OBP_ADDRESS) {
2742 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2743 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2745 if (end > HI_OBP_ADDRESS) {
2746 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2747 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2750 flush_tsb_kernel_range(start, end);
2751 do_flush_tlb_kernel_range(start, end);