arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/vmalloc.h>
  14 #include <linux/pagemap.h>
  15 #include <linux/init.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/bootmem.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/kdebug.h>
  21 #include <linux/log2.h>
  22 #include <linux/gfp.h>
  23
  24 #include <asm/bitext.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/io.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/asi.h>
  36 #include <asm/msi.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/io-unit.h>
  39 #include <asm/cacheflush.h>
  40 #include <asm/tlbflush.h>
  41
  42 /* Now the cpu specific definitions. */
  43 #include <asm/viking.h>
  44 #include <asm/mxcc.h>
  45 #include <asm/ross.h>
  46 #include <asm/tsunami.h>
  47 #include <asm/swift.h>
  48 #include <asm/turbosparc.h>
  49 #include <asm/leon.h>
  50
  51 #include "srmmu.h"
  52
  53 enum mbus_module srmmu_modtype;
  54 static unsigned int hwbug_bitmask;
  55 int vac_cache_size;
  56 int vac_line_size;
  57
  58 struct ctx_list *ctx_list_pool;
  59 struct ctx_list ctx_free;
  60 struct ctx_list ctx_used;
  61
  62 extern struct resource sparc_iomap;
  63
  64 extern unsigned long last_valid_pfn;
  65
  66 static pgd_t *srmmu_swapper_pg_dir;
  67
  68 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
  69
  70 #ifdef CONFIG_SMP
  71 const struct sparc32_cachetlb_ops *local_ops;
  72
  73 #define FLUSH_BEGIN(mm)
  74 #define FLUSH_END
  75 #else
  76 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
  77 #define FLUSH_END       }
  78 #endif
  79
  80 int flush_page_for_dma_global = 1;
  81
  82 char *srmmu_name;
  83
  84 ctxd_t *srmmu_ctx_table_phys;
  85 static ctxd_t *srmmu_context_table;
  86
  87 int viking_mxcc_present;
  88 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  89
  90 static int is_hypersparc;
  91
  92 static int srmmu_cache_pagetables;
  93
  94 /* these will be initialized in srmmu_nocache_calcsize() */
  95 static unsigned long srmmu_nocache_size;
  96 static unsigned long srmmu_nocache_end;
  97
  98 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
  99 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 100
 101 /* The context table is a nocache user with the biggest alignment needs. */
 102 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 103
 104 void *srmmu_nocache_pool;
 105 void *srmmu_nocache_bitmap;
 106 static struct bit_map srmmu_nocache_map;
 107
 108 static inline int srmmu_pmd_none(pmd_t pmd)
 109 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 110
 111 /* XXX should we hyper_flush_whole_icache here - Anton */
 112 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 113 { set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 114
 115 void pmd_set(pmd_t *pmdp, pte_t *ptep)
 116 {
 117         unsigned long ptp;      /* Physical address, shifted right by 4 */
 118         int i;
 119
 120         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 121         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 122                 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 123                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 124         }
 125 }
 126
 127 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
 128 {
 129         unsigned long ptp;      /* Physical address, shifted right by 4 */
 130         int i;
 131
 132         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 133         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 134                 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 135                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 136         }
 137 }
 138
 139 /* Find an entry in the third-level page table.. */
 140 pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address)
 141 {
 142         void *pte;
 143
 144         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 145         return (pte_t *) pte +
 146             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 147 }
 148
 149 /*
 150  * size: bytes to allocate in the nocache area.
 151  * align: bytes, number to align at.
 152  * Returns the virtual address of the allocated area.
 153  */
 154 static unsigned long __srmmu_get_nocache(int size, int align)
 155 {
 156         int offset;
 157
 158         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 159                 printk("Size 0x%x too small for nocache request\n", size);
 160                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 161         }
 162         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 163                 printk("Size 0x%x unaligned int nocache request\n", size);
 164                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 165         }
 166         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 167
 168         offset = bit_map_string_get(&srmmu_nocache_map,
 169                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 170                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 171         if (offset == -1) {
 172                 printk("srmmu: out of nocache %d: %d/%d\n",
 173                     size, (int) srmmu_nocache_size,
 174                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 175                 return 0;
 176         }
 177
 178         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 179 }
 180
 181 unsigned long srmmu_get_nocache(int size, int align)
 182 {
 183         unsigned long tmp;
 184
 185         tmp = __srmmu_get_nocache(size, align);
 186
 187         if (tmp)
 188                 memset((void *)tmp, 0, size);
 189
 190         return tmp;
 191 }
 192
 193 void srmmu_free_nocache(unsigned long vaddr, int size)
 194 {
 195         int offset;
 196
 197         if (vaddr < SRMMU_NOCACHE_VADDR) {
 198                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 199                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 200                 BUG();
 201         }
 202         if (vaddr+size > srmmu_nocache_end) {
 203                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 204                     vaddr, srmmu_nocache_end);
 205                 BUG();
 206         }
 207         if (!is_power_of_2(size)) {
 208                 printk("Size 0x%x is not a power of 2\n", size);
 209                 BUG();
 210         }
 211         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 212                 printk("Size 0x%x is too small\n", size);
 213                 BUG();
 214         }
 215         if (vaddr & (size-1)) {
 216                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 217                 BUG();
 218         }
 219
 220         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 221         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 222
 223         bit_map_clear(&srmmu_nocache_map, offset, size);
 224 }
 225
 226 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
 227                                                  unsigned long end);
 228
 229 extern unsigned long probe_memory(void);        /* in fault.c */
 230
 231 /*
 232  * Reserve nocache dynamically proportionally to the amount of
 233  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 234  */
 235 static void srmmu_nocache_calcsize(void)
 236 {
 237         unsigned long sysmemavail = probe_memory() / 1024;
 238         int srmmu_nocache_npages;
 239
 240         srmmu_nocache_npages =
 241                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 242
 243  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 244         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 245         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 246                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 247
 248         /* anything above 1280 blows up */
 249         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 250                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 251
 252         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 253         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 254 }
 255
 256 static void __init srmmu_nocache_init(void)
 257 {
 258         unsigned int bitmap_bits;
 259         pgd_t *pgd;
 260         pmd_t *pmd;
 261         pte_t *pte;
 262         unsigned long paddr, vaddr;
 263         unsigned long pteval;
 264
 265         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 266
 267         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 268                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 269         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 270
 271         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 272         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 273
 274         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 275         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 276         init_mm.pgd = srmmu_swapper_pg_dir;
 277
 278         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 279
 280         paddr = __pa((unsigned long)srmmu_nocache_pool);
 281         vaddr = SRMMU_NOCACHE_VADDR;
 282
 283         while (vaddr < srmmu_nocache_end) {
 284                 pgd = pgd_offset_k(vaddr);
 285                 pmd = pmd_offset(__nocache_fix(pgd), vaddr);
 286                 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
 287
 288                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 289
 290                 if (srmmu_cache_pagetables)
 291                         pteval |= SRMMU_CACHE;
 292
 293                 set_pte(__nocache_fix(pte), __pte(pteval));
 294
 295                 vaddr += PAGE_SIZE;
 296                 paddr += PAGE_SIZE;
 297         }
 298
 299         flush_cache_all();
 300         flush_tlb_all();
 301 }
 302
 303 pgd_t *get_pgd_fast(void)
 304 {
 305         pgd_t *pgd = NULL;
 306
 307         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 308         if (pgd) {
 309                 pgd_t *init = pgd_offset_k(0);
 310                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 311                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 312                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 313         }
 314
 315         return pgd;
 316 }
 317
 318 /*
 319  * Hardware needs alignment to 256 only, but we align to whole page size
 320  * to reduce fragmentation problems due to the buddy principle.
 321  * XXX Provide actual fragmentation statistics in /proc.
 322  *
 323  * Alignments up to the page size are the same for physical and virtual
 324  * addresses of the nocache area.
 325  */
 326 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
 327 {
 328         unsigned long pte;
 329         struct page *page;
 330
 331         if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
 332                 return NULL;
 333         page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 334         pgtable_page_ctor(page);
 335         return page;
 336 }
 337
 338 void pte_free(struct mm_struct *mm, pgtable_t pte)
 339 {
 340         unsigned long p;
 341
 342         pgtable_page_dtor(pte);
 343         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 344         if (p == 0)
 345                 BUG();
 346         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 347         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 348         srmmu_free_nocache(p, PTE_SIZE);
 349 }
 350
 351 /*
 352  */
 353 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 354 {
 355         struct ctx_list *ctxp;
 356
 357         ctxp = ctx_free.next;
 358         if(ctxp != &ctx_free) {
 359                 remove_from_ctx_list(ctxp);
 360                 add_to_used_ctxlist(ctxp);
 361                 mm->context = ctxp->ctx_number;
 362                 ctxp->ctx_mm = mm;
 363                 return;
 364         }
 365         ctxp = ctx_used.next;
 366         if(ctxp->ctx_mm == old_mm)
 367                 ctxp = ctxp->next;
 368         if(ctxp == &ctx_used)
 369                 panic("out of mmu contexts");
 370         flush_cache_mm(ctxp->ctx_mm);
 371         flush_tlb_mm(ctxp->ctx_mm);
 372         remove_from_ctx_list(ctxp);
 373         add_to_used_ctxlist(ctxp);
 374         ctxp->ctx_mm->context = NO_CONTEXT;
 375         ctxp->ctx_mm = mm;
 376         mm->context = ctxp->ctx_number;
 377 }
 378
 379 static inline void free_context(int context)
 380 {
 381         struct ctx_list *ctx_old;
 382
 383         ctx_old = ctx_list_pool + context;
 384         remove_from_ctx_list(ctx_old);
 385         add_to_free_ctxlist(ctx_old);
 386 }
 387
 388
 389 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 390                struct task_struct *tsk)
 391 {
 392         if(mm->context == NO_CONTEXT) {
 393                 spin_lock(&srmmu_context_spinlock);
 394                 alloc_context(old_mm, mm);
 395                 spin_unlock(&srmmu_context_spinlock);
 396                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 397         }
 398
 399         if (sparc_cpu_model == sparc_leon)
 400                 leon_switch_mm();
 401
 402         if (is_hypersparc)
 403                 hyper_flush_whole_icache();
 404
 405         srmmu_set_context(mm->context);
 406 }
 407
 408 /* Low level IO area allocation on the SRMMU. */
 409 static inline void srmmu_mapioaddr(unsigned long physaddr,
 410     unsigned long virt_addr, int bus_type)
 411 {
 412         pgd_t *pgdp;
 413         pmd_t *pmdp;
 414         pte_t *ptep;
 415         unsigned long tmp;
 416
 417         physaddr &= PAGE_MASK;
 418         pgdp = pgd_offset_k(virt_addr);
 419         pmdp = pmd_offset(pgdp, virt_addr);
 420         ptep = pte_offset_kernel(pmdp, virt_addr);
 421         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 422
 423         /*
 424          * I need to test whether this is consistent over all
 425          * sun4m's.  The bus_type represents the upper 4 bits of
 426          * 36-bit physical address on the I/O space lines...
 427          */
 428         tmp |= (bus_type << 28);
 429         tmp |= SRMMU_PRIV;
 430         __flush_page_to_ram(virt_addr);
 431         set_pte(ptep, __pte(tmp));
 432 }
 433
 434 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 435                       unsigned long xva, unsigned int len)
 436 {
 437         while (len != 0) {
 438                 len -= PAGE_SIZE;
 439                 srmmu_mapioaddr(xpa, xva, bus);
 440                 xva += PAGE_SIZE;
 441                 xpa += PAGE_SIZE;
 442         }
 443         flush_tlb_all();
 444 }
 445
 446 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 447 {
 448         pgd_t *pgdp;
 449         pmd_t *pmdp;
 450         pte_t *ptep;
 451
 452         pgdp = pgd_offset_k(virt_addr);
 453         pmdp = pmd_offset(pgdp, virt_addr);
 454         ptep = pte_offset_kernel(pmdp, virt_addr);
 455
 456         /* No need to flush uncacheable page. */
 457         __pte_clear(ptep);
 458 }
 459
 460 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 461 {
 462         while (len != 0) {
 463                 len -= PAGE_SIZE;
 464                 srmmu_unmapioaddr(virt_addr);
 465                 virt_addr += PAGE_SIZE;
 466         }
 467         flush_tlb_all();
 468 }
 469
 470 /* tsunami.S */
 471 extern void tsunami_flush_cache_all(void);
 472 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 473 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 474 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 475 extern void tsunami_flush_page_to_ram(unsigned long page);
 476 extern void tsunami_flush_page_for_dma(unsigned long page);
 477 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 478 extern void tsunami_flush_tlb_all(void);
 479 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 480 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 481 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 482 extern void tsunami_setup_blockops(void);
 483
 484 /* swift.S */
 485 extern void swift_flush_cache_all(void);
 486 extern void swift_flush_cache_mm(struct mm_struct *mm);
 487 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 488                                     unsigned long start, unsigned long end);
 489 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 490 extern void swift_flush_page_to_ram(unsigned long page);
 491 extern void swift_flush_page_for_dma(unsigned long page);
 492 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 493 extern void swift_flush_tlb_all(void);
 494 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 495 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 496                                   unsigned long start, unsigned long end);
 497 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 498
 499 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 500 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 501 {
 502         int cctx, ctx1;
 503
 504         page &= PAGE_MASK;
 505         if ((ctx1 = vma->vm_mm->context) != -1) {
 506                 cctx = srmmu_get_context();
 507 /* Is context # ever different from current context? P3 */
 508                 if (cctx != ctx1) {
 509                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 510                         srmmu_set_context(ctx1);
 511                         swift_flush_page(page);
 512                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 513                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 514                         srmmu_set_context(cctx);
 515                 } else {
 516                          /* Rm. prot. bits from virt. c. */
 517                         /* swift_flush_cache_all(); */
 518                         /* swift_flush_cache_page(vma, page); */
 519                         swift_flush_page(page);
 520
 521                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 522                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 523                         /* same as above: srmmu_flush_tlb_page() */
 524                 }
 525         }
 526 }
 527 #endif
 528
 529 /*
 530  * The following are all MBUS based SRMMU modules, and therefore could
 531  * be found in a multiprocessor configuration.  On the whole, these
 532  * chips seems to be much more touchy about DVMA and page tables
 533  * with respect to cache coherency.
 534  */
 535
 536 /* viking.S */
 537 extern void viking_flush_cache_all(void);
 538 extern void viking_flush_cache_mm(struct mm_struct *mm);
 539 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
 540                                      unsigned long end);
 541 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 542 extern void viking_flush_page_to_ram(unsigned long page);
 543 extern void viking_flush_page_for_dma(unsigned long page);
 544 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
 545 extern void viking_flush_page(unsigned long page);
 546 extern void viking_mxcc_flush_page(unsigned long page);
 547 extern void viking_flush_tlb_all(void);
 548 extern void viking_flush_tlb_mm(struct mm_struct *mm);
 549 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 550                                    unsigned long end);
 551 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
 552                                   unsigned long page);
 553 extern void sun4dsmp_flush_tlb_all(void);
 554 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
 555 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 556                                    unsigned long end);
 557 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
 558                                   unsigned long page);
 559
 560 /* hypersparc.S */
 561 extern void hypersparc_flush_cache_all(void);
 562 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
 563 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 564 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 565 extern void hypersparc_flush_page_to_ram(unsigned long page);
 566 extern void hypersparc_flush_page_for_dma(unsigned long page);
 567 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 568 extern void hypersparc_flush_tlb_all(void);
 569 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
 570 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 571 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 572 extern void hypersparc_setup_blockops(void);
 573
 574 /*
 575  * NOTE: All of this startup code assumes the low 16mb (approx.) of
 576  *       kernel mappings are done with one single contiguous chunk of
 577  *       ram.  On small ram machines (classics mainly) we only get
 578  *       around 8mb mapped for us.
 579  */
 580
 581 static void __init early_pgtable_allocfail(char *type)
 582 {
 583         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 584         prom_halt();
 585 }
 586
 587 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
 588                                                         unsigned long end)
 589 {
 590         pgd_t *pgdp;
 591         pmd_t *pmdp;
 592         pte_t *ptep;
 593
 594         while(start < end) {
 595                 pgdp = pgd_offset_k(start);
 596                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
 597                         pmdp = (pmd_t *) __srmmu_get_nocache(
 598                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 599                         if (pmdp == NULL)
 600                                 early_pgtable_allocfail("pmd");
 601                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
 602                         pgd_set(__nocache_fix(pgdp), pmdp);
 603                 }
 604                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
 605                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
 606                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 607                         if (ptep == NULL)
 608                                 early_pgtable_allocfail("pte");
 609                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
 610                         pmd_set(__nocache_fix(pmdp), ptep);
 611                 }
 612                 if (start > (0xffffffffUL - PMD_SIZE))
 613                         break;
 614                 start = (start + PMD_SIZE) & PMD_MASK;
 615         }
 616 }
 617
 618 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
 619                                                   unsigned long end)
 620 {
 621         pgd_t *pgdp;
 622         pmd_t *pmdp;
 623         pte_t *ptep;
 624
 625         while(start < end) {
 626                 pgdp = pgd_offset_k(start);
 627                 if (pgd_none(*pgdp)) {
 628                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 629                         if (pmdp == NULL)
 630                                 early_pgtable_allocfail("pmd");
 631                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
 632                         pgd_set(pgdp, pmdp);
 633                 }
 634                 pmdp = pmd_offset(pgdp, start);
 635                 if(srmmu_pmd_none(*pmdp)) {
 636                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
 637                                                              PTE_SIZE);
 638                         if (ptep == NULL)
 639                                 early_pgtable_allocfail("pte");
 640                         memset(ptep, 0, PTE_SIZE);
 641                         pmd_set(pmdp, ptep);
 642                 }
 643                 if (start > (0xffffffffUL - PMD_SIZE))
 644                         break;
 645                 start = (start + PMD_SIZE) & PMD_MASK;
 646         }
 647 }
 648
 649 /*
 650  * This is much cleaner than poking around physical address space
 651  * looking at the prom's page table directly which is what most
 652  * other OS's do.  Yuck... this is much better.
 653  */
 654 static void __init srmmu_inherit_prom_mappings(unsigned long start,
 655                                                unsigned long end)
 656 {
 657         pgd_t *pgdp;
 658         pmd_t *pmdp;
 659         pte_t *ptep;
 660         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
 661         unsigned long prompte;
 662
 663         while(start <= end) {
 664                 if (start == 0)
 665                         break; /* probably wrap around */
 666                 if(start == 0xfef00000)
 667                         start = KADB_DEBUGGER_BEGVM;
 668                 if(!(prompte = srmmu_hwprobe(start))) {
 669                         start += PAGE_SIZE;
 670                         continue;
 671                 }
 672
 673                 /* A red snapper, see what it really is. */
 674                 what = 0;
 675
 676                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
 677                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
 678                                 what = 1;
 679                 }
 680
 681                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
 682                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
 683                            prompte)
 684                                 what = 2;
 685                 }
 686
 687                 pgdp = pgd_offset_k(start);
 688                 if(what == 2) {
 689                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
 690                         start += SRMMU_PGDIR_SIZE;
 691                         continue;
 692                 }
 693                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
 694                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 695                         if (pmdp == NULL)
 696                                 early_pgtable_allocfail("pmd");
 697                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
 698                         pgd_set(__nocache_fix(pgdp), pmdp);
 699                 }
 700                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
 701                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
 702                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
 703                                                              PTE_SIZE);
 704                         if (ptep == NULL)
 705                                 early_pgtable_allocfail("pte");
 706                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
 707                         pmd_set(__nocache_fix(pmdp), ptep);
 708                 }
 709                 if(what == 1) {
 710                         /*
 711                          * We bend the rule where all 16 PTPs in a pmd_t point
 712                          * inside the same PTE page, and we leak a perfectly
 713                          * good hardware PTE piece. Alternatives seem worse.
 714                          */
 715                         unsigned int x; /* Index of HW PMD in soft cluster */
 716                         x = (start >> PMD_SHIFT) & 15;
 717                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
 718                         start += SRMMU_REAL_PMD_SIZE;
 719                         continue;
 720                 }
 721                 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
 722                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
 723                 start += PAGE_SIZE;
 724         }
 725 }
 726
 727 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
 728
 729 /* Create a third-level SRMMU 16MB page mapping. */
 730 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
 731 {
 732         pgd_t *pgdp = pgd_offset_k(vaddr);
 733         unsigned long big_pte;
 734
 735         big_pte = KERNEL_PTE(phys_base >> 4);
 736         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
 737 }
 738
 739 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
 740 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
 741 {
 742         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
 743         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
 744         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
 745         /* Map "low" memory only */
 746         const unsigned long min_vaddr = PAGE_OFFSET;
 747         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
 748
 749         if (vstart < min_vaddr || vstart >= max_vaddr)
 750                 return vstart;
 751
 752         if (vend > max_vaddr || vend < min_vaddr)
 753                 vend = max_vaddr;
 754
 755         while(vstart < vend) {
 756                 do_large_mapping(vstart, pstart);
 757                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
 758         }
 759         return vstart;
 760 }
 761
 762 static inline void map_kernel(void)
 763 {
 764         int i;
 765
 766         if (phys_base > 0) {
 767                 do_large_mapping(PAGE_OFFSET, phys_base);
 768         }
 769
 770         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
 771                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
 772         }
 773 }
 774
 775 /* Paging initialization on the Sparc Reference MMU. */
 776 extern void sparc_context_init(int);
 777
 778 void (*poke_srmmu)(void) __cpuinitdata = NULL;
 779
 780 extern unsigned long bootmem_init(unsigned long *pages_avail);
 781
 782 void __init srmmu_paging_init(void)
 783 {
 784         int i;
 785         phandle cpunode;
 786         char node_str[128];
 787         pgd_t *pgd;
 788         pmd_t *pmd;
 789         pte_t *pte;
 790         unsigned long pages_avail;
 791
 792         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
 793
 794         if (sparc_cpu_model == sun4d)
 795                 num_contexts = 65536; /* We know it is Viking */
 796         else {
 797                 /* Find the number of contexts on the srmmu. */
 798                 cpunode = prom_getchild(prom_root_node);
 799                 num_contexts = 0;
 800                 while(cpunode != 0) {
 801                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
 802                         if(!strcmp(node_str, "cpu")) {
 803                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
 804                                 break;
 805                         }
 806                         cpunode = prom_getsibling(cpunode);
 807                 }
 808         }
 809
 810         if(!num_contexts) {
 811                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
 812                 prom_halt();
 813         }
 814
 815         pages_avail = 0;
 816         last_valid_pfn = bootmem_init(&pages_avail);
 817
 818         srmmu_nocache_calcsize();
 819         srmmu_nocache_init();
 820         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
 821         map_kernel();
 822
 823         /* ctx table has to be physically aligned to its size */
 824         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
 825         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
 826
 827         for(i = 0; i < num_contexts; i++)
 828                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
 829
 830         flush_cache_all();
 831         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
 832 #ifdef CONFIG_SMP
 833         /* Stop from hanging here... */
 834         local_ops->tlb_all();
 835 #else
 836         flush_tlb_all();
 837 #endif
 838         poke_srmmu();
 839
 840         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
 841         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
 842
 843         srmmu_allocate_ptable_skeleton(
 844                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
 845         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
 846
 847         pgd = pgd_offset_k(PKMAP_BASE);
 848         pmd = pmd_offset(pgd, PKMAP_BASE);
 849         pte = pte_offset_kernel(pmd, PKMAP_BASE);
 850         pkmap_page_table = pte;
 851
 852         flush_cache_all();
 853         flush_tlb_all();
 854
 855         sparc_context_init(num_contexts);
 856
 857         kmap_init();
 858
 859         {
 860                 unsigned long zones_size[MAX_NR_ZONES];
 861                 unsigned long zholes_size[MAX_NR_ZONES];
 862                 unsigned long npages;
 863                 int znum;
 864
 865                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
 866                         zones_size[znum] = zholes_size[znum] = 0;
 867
 868                 npages = max_low_pfn - pfn_base;
 869
 870                 zones_size[ZONE_DMA] = npages;
 871                 zholes_size[ZONE_DMA] = npages - pages_avail;
 872
 873                 npages = highend_pfn - max_low_pfn;
 874                 zones_size[ZONE_HIGHMEM] = npages;
 875                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
 876
 877                 free_area_init_node(0, zones_size, pfn_base, zholes_size);
 878         }
 879 }
 880
 881 void mmu_info(struct seq_file *m)
 882 {
 883         seq_printf(m,
 884                    "MMU type\t: %s\n"
 885                    "contexts\t: %d\n"
 886                    "nocache total\t: %ld\n"
 887                    "nocache used\t: %d\n",
 888                    srmmu_name,
 889                    num_contexts,
 890                    srmmu_nocache_size,
 891                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 892 }
 893
 894 void destroy_context(struct mm_struct *mm)
 895 {
 896
 897         if(mm->context != NO_CONTEXT) {
 898                 flush_cache_mm(mm);
 899                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
 900                 flush_tlb_mm(mm);
 901                 spin_lock(&srmmu_context_spinlock);
 902                 free_context(mm->context);
 903                 spin_unlock(&srmmu_context_spinlock);
 904                 mm->context = NO_CONTEXT;
 905         }
 906 }
 907
 908 /* Init various srmmu chip types. */
 909 static void __init srmmu_is_bad(void)
 910 {
 911         prom_printf("Could not determine SRMMU chip type.\n");
 912         prom_halt();
 913 }
 914
 915 static void __init init_vac_layout(void)
 916 {
 917         phandle nd;
 918         int cache_lines;
 919         char node_str[128];
 920 #ifdef CONFIG_SMP
 921         int cpu = 0;
 922         unsigned long max_size = 0;
 923         unsigned long min_line_size = 0x10000000;
 924 #endif
 925
 926         nd = prom_getchild(prom_root_node);
 927         while((nd = prom_getsibling(nd)) != 0) {
 928                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
 929                 if(!strcmp(node_str, "cpu")) {
 930                         vac_line_size = prom_getint(nd, "cache-line-size");
 931                         if (vac_line_size == -1) {
 932                                 prom_printf("can't determine cache-line-size, "
 933                                             "halting.\n");
 934                                 prom_halt();
 935                         }
 936                         cache_lines = prom_getint(nd, "cache-nlines");
 937                         if (cache_lines == -1) {
 938                                 prom_printf("can't determine cache-nlines, halting.\n");
 939                                 prom_halt();
 940                         }
 941
 942                         vac_cache_size = cache_lines * vac_line_size;
 943 #ifdef CONFIG_SMP
 944                         if(vac_cache_size > max_size)
 945                                 max_size = vac_cache_size;
 946                         if(vac_line_size < min_line_size)
 947                                 min_line_size = vac_line_size;
 948                         //FIXME: cpus not contiguous!!
 949                         cpu++;
 950                         if (cpu >= nr_cpu_ids || !cpu_online(cpu))
 951                                 break;
 952 #else
 953                         break;
 954 #endif
 955                 }
 956         }
 957         if(nd == 0) {
 958                 prom_printf("No CPU nodes found, halting.\n");
 959                 prom_halt();
 960         }
 961 #ifdef CONFIG_SMP
 962         vac_cache_size = max_size;
 963         vac_line_size = min_line_size;
 964 #endif
 965         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
 966                (int)vac_cache_size, (int)vac_line_size);
 967 }
 968
 969 static void __cpuinit poke_hypersparc(void)
 970 {
 971         volatile unsigned long clear;
 972         unsigned long mreg = srmmu_get_mmureg();
 973
 974         hyper_flush_unconditional_combined();
 975
 976         mreg &= ~(HYPERSPARC_CWENABLE);
 977         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
 978         mreg |= (HYPERSPARC_CMODE);
 979
 980         srmmu_set_mmureg(mreg);
 981
 982 #if 0 /* XXX I think this is bad news... -DaveM */
 983         hyper_clear_all_tags();
 984 #endif
 985
 986         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
 987         hyper_flush_whole_icache();
 988         clear = srmmu_get_faddr();
 989         clear = srmmu_get_fstatus();
 990 }
 991
 992 static const struct sparc32_cachetlb_ops hypersparc_ops = {
 993         .cache_all      = hypersparc_flush_cache_all,
 994         .cache_mm       = hypersparc_flush_cache_mm,
 995         .cache_page     = hypersparc_flush_cache_page,
 996         .cache_range    = hypersparc_flush_cache_range,
 997         .tlb_all        = hypersparc_flush_tlb_all,
 998         .tlb_mm         = hypersparc_flush_tlb_mm,
 999         .tlb_page       = hypersparc_flush_tlb_page,
1000         .tlb_range      = hypersparc_flush_tlb_range,
1001         .page_to_ram    = hypersparc_flush_page_to_ram,
1002         .sig_insns      = hypersparc_flush_sig_insns,
1003         .page_for_dma   = hypersparc_flush_page_for_dma,
1004 };
1005
1006 static void __init init_hypersparc(void)
1007 {
1008         srmmu_name = "ROSS HyperSparc";
1009         srmmu_modtype = HyperSparc;
1010
1011         init_vac_layout();
1012
1013         is_hypersparc = 1;
1014         sparc32_cachetlb_ops = &hypersparc_ops;
1015
1016         poke_srmmu = poke_hypersparc;
1017
1018         hypersparc_setup_blockops();
1019 }
1020
1021 static void __cpuinit poke_swift(void)
1022 {
1023         unsigned long mreg;
1024
1025         /* Clear any crap from the cache or else... */
1026         swift_flush_cache_all();
1027
1028         /* Enable I & D caches */
1029         mreg = srmmu_get_mmureg();
1030         mreg |= (SWIFT_IE | SWIFT_DE);
1031         /*
1032          * The Swift branch folding logic is completely broken.  At
1033          * trap time, if things are just right, if can mistakenly
1034          * think that a trap is coming from kernel mode when in fact
1035          * it is coming from user mode (it mis-executes the branch in
1036          * the trap code).  So you see things like crashme completely
1037          * hosing your machine which is completely unacceptable.  Turn
1038          * this shit off... nice job Fujitsu.
1039          */
1040         mreg &= ~(SWIFT_BF);
1041         srmmu_set_mmureg(mreg);
1042 }
1043
1044 static const struct sparc32_cachetlb_ops swift_ops = {
1045         .cache_all      = swift_flush_cache_all,
1046         .cache_mm       = swift_flush_cache_mm,
1047         .cache_page     = swift_flush_cache_page,
1048         .cache_range    = swift_flush_cache_range,
1049         .tlb_all        = swift_flush_tlb_all,
1050         .tlb_mm         = swift_flush_tlb_mm,
1051         .tlb_page       = swift_flush_tlb_page,
1052         .tlb_range      = swift_flush_tlb_range,
1053         .page_to_ram    = swift_flush_page_to_ram,
1054         .sig_insns      = swift_flush_sig_insns,
1055         .page_for_dma   = swift_flush_page_for_dma,
1056 };
1057
1058 #define SWIFT_MASKID_ADDR  0x10003018
1059 static void __init init_swift(void)
1060 {
1061         unsigned long swift_rev;
1062
1063         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1064                              "srl %0, 0x18, %0\n\t" :
1065                              "=r" (swift_rev) :
1066                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1067         srmmu_name = "Fujitsu Swift";
1068         switch(swift_rev) {
1069         case 0x11:
1070         case 0x20:
1071         case 0x23:
1072         case 0x30:
1073                 srmmu_modtype = Swift_lots_o_bugs;
1074                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1075                 /*
1076                  * Gee george, I wonder why Sun is so hush hush about
1077                  * this hardware bug... really braindamage stuff going
1078                  * on here.  However I think we can find a way to avoid
1079                  * all of the workaround overhead under Linux.  Basically,
1080                  * any page fault can cause kernel pages to become user
1081                  * accessible (the mmu gets confused and clears some of
1082                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1083                  * horrible eh?  But wait, after extensive testing it appears
1084                  * that if you use pgd_t level large kernel pte's (like the
1085                  * 4MB pages on the Pentium) the bug does not get tripped
1086                  * at all.  This avoids almost all of the major overhead.
1087                  * Welcome to a world where your vendor tells you to,
1088                  * "apply this kernel patch" instead of "sorry for the
1089                  * broken hardware, send it back and we'll give you
1090                  * properly functioning parts"
1091                  */
1092                 break;
1093         case 0x25:
1094         case 0x31:
1095                 srmmu_modtype = Swift_bad_c;
1096                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1097                 /*
1098                  * You see Sun allude to this hardware bug but never
1099                  * admit things directly, they'll say things like,
1100                  * "the Swift chip cache problems" or similar.
1101                  */
1102                 break;
1103         default:
1104                 srmmu_modtype = Swift_ok;
1105                 break;
1106         }
1107
1108         sparc32_cachetlb_ops = &swift_ops;
1109         flush_page_for_dma_global = 0;
1110
1111         /*
1112          * Are you now convinced that the Swift is one of the
1113          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1114          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1115          * you examined the microcode of the Swift you'd find
1116          * XXX's all over the place.
1117          */
1118         poke_srmmu = poke_swift;
1119 }
1120
1121 static void turbosparc_flush_cache_all(void)
1122 {
1123         flush_user_windows();
1124         turbosparc_idflash_clear();
1125 }
1126
1127 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1128 {
1129         FLUSH_BEGIN(mm)
1130         flush_user_windows();
1131         turbosparc_idflash_clear();
1132         FLUSH_END
1133 }
1134
1135 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1136 {
1137         FLUSH_BEGIN(vma->vm_mm)
1138         flush_user_windows();
1139         turbosparc_idflash_clear();
1140         FLUSH_END
1141 }
1142
1143 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1144 {
1145         FLUSH_BEGIN(vma->vm_mm)
1146         flush_user_windows();
1147         if (vma->vm_flags & VM_EXEC)
1148                 turbosparc_flush_icache();
1149         turbosparc_flush_dcache();
1150         FLUSH_END
1151 }
1152
1153 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1154 static void turbosparc_flush_page_to_ram(unsigned long page)
1155 {
1156 #ifdef TURBOSPARC_WRITEBACK
1157         volatile unsigned long clear;
1158
1159         if (srmmu_hwprobe(page))
1160                 turbosparc_flush_page_cache(page);
1161         clear = srmmu_get_fstatus();
1162 #endif
1163 }
1164
1165 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1166 {
1167 }
1168
1169 static void turbosparc_flush_page_for_dma(unsigned long page)
1170 {
1171         turbosparc_flush_dcache();
1172 }
1173
1174 static void turbosparc_flush_tlb_all(void)
1175 {
1176         srmmu_flush_whole_tlb();
1177 }
1178
1179 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1180 {
1181         FLUSH_BEGIN(mm)
1182         srmmu_flush_whole_tlb();
1183         FLUSH_END
1184 }
1185
1186 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1187 {
1188         FLUSH_BEGIN(vma->vm_mm)
1189         srmmu_flush_whole_tlb();
1190         FLUSH_END
1191 }
1192
1193 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1194 {
1195         FLUSH_BEGIN(vma->vm_mm)
1196         srmmu_flush_whole_tlb();
1197         FLUSH_END
1198 }
1199
1200
1201 static void __cpuinit poke_turbosparc(void)
1202 {
1203         unsigned long mreg = srmmu_get_mmureg();
1204         unsigned long ccreg;
1205
1206         /* Clear any crap from the cache or else... */
1207         turbosparc_flush_cache_all();
1208         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1209         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1210         srmmu_set_mmureg(mreg);
1211
1212         ccreg = turbosparc_get_ccreg();
1213
1214 #ifdef TURBOSPARC_WRITEBACK
1215         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1216         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1217                         /* Write-back D-cache, emulate VLSI
1218                          * abortion number three, not number one */
1219 #else
1220         /* For now let's play safe, optimize later */
1221         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1222                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1223         ccreg &= ~(TURBOSPARC_uS2);
1224                         /* Emulate VLSI abortion number three, not number one */
1225 #endif
1226
1227         switch (ccreg & 7) {
1228         case 0: /* No SE cache */
1229         case 7: /* Test mode */
1230                 break;
1231         default:
1232                 ccreg |= (TURBOSPARC_SCENABLE);
1233         }
1234         turbosparc_set_ccreg (ccreg);
1235
1236         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1237         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1238         srmmu_set_mmureg(mreg);
1239 }
1240
1241 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1242         .cache_all      = turbosparc_flush_cache_all,
1243         .cache_mm       = turbosparc_flush_cache_mm,
1244         .cache_page     = turbosparc_flush_cache_page,
1245         .cache_range    = turbosparc_flush_cache_range,
1246         .tlb_all        = turbosparc_flush_tlb_all,
1247         .tlb_mm         = turbosparc_flush_tlb_mm,
1248         .tlb_page       = turbosparc_flush_tlb_page,
1249         .tlb_range      = turbosparc_flush_tlb_range,
1250         .page_to_ram    = turbosparc_flush_page_to_ram,
1251         .sig_insns      = turbosparc_flush_sig_insns,
1252         .page_for_dma   = turbosparc_flush_page_for_dma,
1253 };
1254
1255 static void __init init_turbosparc(void)
1256 {
1257         srmmu_name = "Fujitsu TurboSparc";
1258         srmmu_modtype = TurboSparc;
1259         sparc32_cachetlb_ops = &turbosparc_ops;
1260         poke_srmmu = poke_turbosparc;
1261 }
1262
1263 static void __cpuinit poke_tsunami(void)
1264 {
1265         unsigned long mreg = srmmu_get_mmureg();
1266
1267         tsunami_flush_icache();
1268         tsunami_flush_dcache();
1269         mreg &= ~TSUNAMI_ITD;
1270         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1271         srmmu_set_mmureg(mreg);
1272 }
1273
1274 static const struct sparc32_cachetlb_ops tsunami_ops = {
1275         .cache_all      = tsunami_flush_cache_all,
1276         .cache_mm       = tsunami_flush_cache_mm,
1277         .cache_page     = tsunami_flush_cache_page,
1278         .cache_range    = tsunami_flush_cache_range,
1279         .tlb_all        = tsunami_flush_tlb_all,
1280         .tlb_mm         = tsunami_flush_tlb_mm,
1281         .tlb_page       = tsunami_flush_tlb_page,
1282         .tlb_range      = tsunami_flush_tlb_range,
1283         .page_to_ram    = tsunami_flush_page_to_ram,
1284         .sig_insns      = tsunami_flush_sig_insns,
1285         .page_for_dma   = tsunami_flush_page_for_dma,
1286 };
1287
1288 static void __init init_tsunami(void)
1289 {
1290         /*
1291          * Tsunami's pretty sane, Sun and TI actually got it
1292          * somewhat right this time.  Fujitsu should have
1293          * taken some lessons from them.
1294          */
1295
1296         srmmu_name = "TI Tsunami";
1297         srmmu_modtype = Tsunami;
1298         sparc32_cachetlb_ops = &tsunami_ops;
1299         poke_srmmu = poke_tsunami;
1300
1301         tsunami_setup_blockops();
1302 }
1303
1304 static void __cpuinit poke_viking(void)
1305 {
1306         unsigned long mreg = srmmu_get_mmureg();
1307         static int smp_catch;
1308
1309         if (viking_mxcc_present) {
1310                 unsigned long mxcc_control = mxcc_get_creg();
1311
1312                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1313                 mxcc_control &= ~(MXCC_CTL_RRC);
1314                 mxcc_set_creg(mxcc_control);
1315
1316                 /*
1317                  * We don't need memory parity checks.
1318                  * XXX This is a mess, have to dig out later. ecd.
1319                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1320                  */
1321
1322                 /* We do cache ptables on MXCC. */
1323                 mreg |= VIKING_TCENABLE;
1324         } else {
1325                 unsigned long bpreg;
1326
1327                 mreg &= ~(VIKING_TCENABLE);
1328                 if(smp_catch++) {
1329                         /* Must disable mixed-cmd mode here for other cpu's. */
1330                         bpreg = viking_get_bpreg();
1331                         bpreg &= ~(VIKING_ACTION_MIX);
1332                         viking_set_bpreg(bpreg);
1333
1334                         /* Just in case PROM does something funny. */
1335                         msi_set_sync();
1336                 }
1337         }
1338
1339         mreg |= VIKING_SPENABLE;
1340         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1341         mreg |= VIKING_SBENABLE;
1342         mreg &= ~(VIKING_ACENABLE);
1343         srmmu_set_mmureg(mreg);
1344 }
1345
1346 static struct sparc32_cachetlb_ops viking_ops = {
1347         .cache_all      = viking_flush_cache_all,
1348         .cache_mm       = viking_flush_cache_mm,
1349         .cache_page     = viking_flush_cache_page,
1350         .cache_range    = viking_flush_cache_range,
1351         .tlb_all        = viking_flush_tlb_all,
1352         .tlb_mm         = viking_flush_tlb_mm,
1353         .tlb_page       = viking_flush_tlb_page,
1354         .tlb_range      = viking_flush_tlb_range,
1355         .page_to_ram    = viking_flush_page_to_ram,
1356         .sig_insns      = viking_flush_sig_insns,
1357         .page_for_dma   = viking_flush_page_for_dma,
1358 };
1359
1360 #ifdef CONFIG_SMP
1361 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1362  * perform the local TLB flush and all the other cpus will see it.
1363  * But, unfortunately, there is a bug in the sun4d XBUS backplane
1364  * that requires that we add some synchronization to these flushes.
1365  *
1366  * The bug is that the fifo which keeps track of all the pending TLB
1367  * broadcasts in the system is an entry or two too small, so if we
1368  * have too many going at once we'll overflow that fifo and lose a TLB
1369  * flush resulting in corruption.
1370  *
1371  * Our workaround is to take a global spinlock around the TLB flushes,
1372  * which guarentees we won't ever have too many pending.  It's a big
1373  * hammer, but a semaphore like system to make sure we only have N TLB
1374  * flushes going at once will require SMP locking anyways so there's
1375  * no real value in trying any harder than this.
1376  */
1377 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = {
1378         .cache_all      = viking_flush_cache_all,
1379         .cache_mm       = viking_flush_cache_mm,
1380         .cache_page     = viking_flush_cache_page,
1381         .cache_range    = viking_flush_cache_range,
1382         .tlb_all        = sun4dsmp_flush_tlb_all,
1383         .tlb_mm         = sun4dsmp_flush_tlb_mm,
1384         .tlb_page       = sun4dsmp_flush_tlb_page,
1385         .tlb_range      = sun4dsmp_flush_tlb_range,
1386         .page_to_ram    = viking_flush_page_to_ram,
1387         .sig_insns      = viking_flush_sig_insns,
1388         .page_for_dma   = viking_flush_page_for_dma,
1389 };
1390 #endif
1391
1392 static void __init init_viking(void)
1393 {
1394         unsigned long mreg = srmmu_get_mmureg();
1395
1396         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1397         if(mreg & VIKING_MMODE) {
1398                 srmmu_name = "TI Viking";
1399                 viking_mxcc_present = 0;
1400                 msi_set_sync();
1401
1402                 /*
1403                  * We need this to make sure old viking takes no hits
1404                  * on it's cache for dma snoops to workaround the
1405                  * "load from non-cacheable memory" interrupt bug.
1406                  * This is only necessary because of the new way in
1407                  * which we use the IOMMU.
1408                  */
1409                 viking_ops.page_for_dma = viking_flush_page;
1410 #ifdef CONFIG_SMP
1411                 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1412 #endif
1413                 flush_page_for_dma_global = 0;
1414         } else {
1415                 srmmu_name = "TI Viking/MXCC";
1416                 viking_mxcc_present = 1;
1417                 srmmu_cache_pagetables = 1;
1418         }
1419
1420         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1421                 &viking_ops;
1422 #ifdef CONFIG_SMP
1423         if (sparc_cpu_model == sun4d)
1424                 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1425                         &viking_sun4d_smp_ops;
1426 #endif
1427
1428         poke_srmmu = poke_viking;
1429 }
1430
1431 /* Probe for the srmmu chip version. */
1432 static void __init get_srmmu_type(void)
1433 {
1434         unsigned long mreg, psr;
1435         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1436
1437         srmmu_modtype = SRMMU_INVAL_MOD;
1438         hwbug_bitmask = 0;
1439
1440         mreg = srmmu_get_mmureg(); psr = get_psr();
1441         mod_typ = (mreg & 0xf0000000) >> 28;
1442         mod_rev = (mreg & 0x0f000000) >> 24;
1443         psr_typ = (psr >> 28) & 0xf;
1444         psr_vers = (psr >> 24) & 0xf;
1445
1446         /* First, check for sparc-leon. */
1447         if (sparc_cpu_model == sparc_leon) {
1448                 init_leon();
1449                 return;
1450         }
1451
1452         /* Second, check for HyperSparc or Cypress. */
1453         if(mod_typ == 1) {
1454                 switch(mod_rev) {
1455                 case 7:
1456                         /* UP or MP Hypersparc */
1457                         init_hypersparc();
1458                         break;
1459                 case 0:
1460                 case 2:
1461                 case 10:
1462                 case 11:
1463                 case 12:
1464                 case 13:
1465                 case 14:
1466                 case 15:
1467                 default:
1468                         prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1469                         prom_halt();
1470                         break;
1471                 }
1472                 return;
1473         }
1474
1475         /*
1476          * Now Fujitsu TurboSparc. It might happen that it is
1477          * in Swift emulation mode, so we will check later...
1478          */
1479         if (psr_typ == 0 && psr_vers == 5) {
1480                 init_turbosparc();
1481                 return;
1482         }
1483
1484         /* Next check for Fujitsu Swift. */
1485         if(psr_typ == 0 && psr_vers == 4) {
1486                 phandle cpunode;
1487                 char node_str[128];
1488
1489                 /* Look if it is not a TurboSparc emulating Swift... */
1490                 cpunode = prom_getchild(prom_root_node);
1491                 while((cpunode = prom_getsibling(cpunode)) != 0) {
1492                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1493                         if(!strcmp(node_str, "cpu")) {
1494                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1495                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1496                                         init_turbosparc();
1497                                         return;
1498                                 }
1499                                 break;
1500                         }
1501                 }
1502
1503                 init_swift();
1504                 return;
1505         }
1506
1507         /* Now the Viking family of srmmu. */
1508         if(psr_typ == 4 &&
1509            ((psr_vers == 0) ||
1510             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1511                 init_viking();
1512                 return;
1513         }
1514
1515         /* Finally the Tsunami. */
1516         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1517                 init_tsunami();
1518                 return;
1519         }
1520
1521         /* Oh well */
1522         srmmu_is_bad();
1523 }
1524
1525 #ifdef CONFIG_SMP
1526 /* Local cross-calls. */
1527 static void smp_flush_page_for_dma(unsigned long page)
1528 {
1529         xc1((smpfunc_t) local_ops->page_for_dma, page);
1530         local_ops->page_for_dma(page);
1531 }
1532
1533 static void smp_flush_cache_all(void)
1534 {
1535         xc0((smpfunc_t) local_ops->cache_all);
1536         local_ops->cache_all();
1537 }
1538
1539 static void smp_flush_tlb_all(void)
1540 {
1541         xc0((smpfunc_t) local_ops->tlb_all);
1542         local_ops->tlb_all();
1543 }
1544
1545 static void smp_flush_cache_mm(struct mm_struct *mm)
1546 {
1547         if (mm->context != NO_CONTEXT) {
1548                 cpumask_t cpu_mask;
1549                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1550                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1551                 if (!cpumask_empty(&cpu_mask))
1552                         xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1553                 local_ops->cache_mm(mm);
1554         }
1555 }
1556
1557 static void smp_flush_tlb_mm(struct mm_struct *mm)
1558 {
1559         if (mm->context != NO_CONTEXT) {
1560                 cpumask_t cpu_mask;
1561                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1562                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1563                 if (!cpumask_empty(&cpu_mask)) {
1564                         xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1565                         if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1566                                 cpumask_copy(mm_cpumask(mm),
1567                                              cpumask_of(smp_processor_id()));
1568                 }
1569                 local_ops->tlb_mm(mm);
1570         }
1571 }
1572
1573 static void smp_flush_cache_range(struct vm_area_struct *vma,
1574                                   unsigned long start,
1575                                   unsigned long end)
1576 {
1577         struct mm_struct *mm = vma->vm_mm;
1578
1579         if (mm->context != NO_CONTEXT) {
1580                 cpumask_t cpu_mask;
1581                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1582                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1583                 if (!cpumask_empty(&cpu_mask))
1584                         xc3((smpfunc_t) local_ops->cache_range,
1585                             (unsigned long) vma, start, end);
1586                 local_ops->cache_range(vma, start, end);
1587         }
1588 }
1589
1590 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1591                                 unsigned long start,
1592                                 unsigned long end)
1593 {
1594         struct mm_struct *mm = vma->vm_mm;
1595
1596         if (mm->context != NO_CONTEXT) {
1597                 cpumask_t cpu_mask;
1598                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1599                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1600                 if (!cpumask_empty(&cpu_mask))
1601                         xc3((smpfunc_t) local_ops->tlb_range,
1602                             (unsigned long) vma, start, end);
1603                 local_ops->tlb_range(vma, start, end);
1604         }
1605 }
1606
1607 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1608 {
1609         struct mm_struct *mm = vma->vm_mm;
1610
1611         if (mm->context != NO_CONTEXT) {
1612                 cpumask_t cpu_mask;
1613                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1614                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1615                 if (!cpumask_empty(&cpu_mask))
1616                         xc2((smpfunc_t) local_ops->cache_page,
1617                             (unsigned long) vma, page);
1618                 local_ops->cache_page(vma, page);
1619         }
1620 }
1621
1622 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1623 {
1624         struct mm_struct *mm = vma->vm_mm;
1625
1626         if (mm->context != NO_CONTEXT) {
1627                 cpumask_t cpu_mask;
1628                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1629                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1630                 if (!cpumask_empty(&cpu_mask))
1631                         xc2((smpfunc_t) local_ops->tlb_page,
1632                             (unsigned long) vma, page);
1633                 local_ops->tlb_page(vma, page);
1634         }
1635 }
1636
1637 static void smp_flush_page_to_ram(unsigned long page)
1638 {
1639         /* Current theory is that those who call this are the one's
1640          * who have just dirtied their cache with the pages contents
1641          * in kernel space, therefore we only run this on local cpu.
1642          *
1643          * XXX This experiment failed, research further... -DaveM
1644          */
1645 #if 1
1646         xc1((smpfunc_t) local_ops->page_to_ram, page);
1647 #endif
1648         local_ops->page_to_ram(page);
1649 }
1650
1651 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1652 {
1653         cpumask_t cpu_mask;
1654         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1655         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1656         if (!cpumask_empty(&cpu_mask))
1657                 xc2((smpfunc_t) local_ops->sig_insns,
1658                     (unsigned long) mm, insn_addr);
1659         local_ops->sig_insns(mm, insn_addr);
1660 }
1661
1662 static struct sparc32_cachetlb_ops smp_cachetlb_ops = {
1663         .cache_all      = smp_flush_cache_all,
1664         .cache_mm       = smp_flush_cache_mm,
1665         .cache_page     = smp_flush_cache_page,
1666         .cache_range    = smp_flush_cache_range,
1667         .tlb_all        = smp_flush_tlb_all,
1668         .tlb_mm         = smp_flush_tlb_mm,
1669         .tlb_page       = smp_flush_tlb_page,
1670         .tlb_range      = smp_flush_tlb_range,
1671         .page_to_ram    = smp_flush_page_to_ram,
1672         .sig_insns      = smp_flush_sig_insns,
1673         .page_for_dma   = smp_flush_page_for_dma,
1674 };
1675 #endif
1676
1677 /* Load up routines and constants for sun4m and sun4d mmu */
1678 void __init load_mmu(void)
1679 {
1680         extern void ld_mmu_iommu(void);
1681         extern void ld_mmu_iounit(void);
1682
1683         /* Functions */
1684         get_srmmu_type();
1685
1686 #ifdef CONFIG_SMP
1687         /* El switcheroo... */
1688         local_ops = sparc32_cachetlb_ops;
1689
1690         if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1691                 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1692                 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1693                 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1694                 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1695         }
1696
1697         if (poke_srmmu == poke_viking) {
1698                 /* Avoid unnecessary cross calls. */
1699                 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1700                 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1701                 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1702                 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1703
1704                 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1705                 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1706                 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1707         }
1708
1709         /* It really is const after this point. */
1710         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1711                 &smp_cachetlb_ops;
1712 #endif
1713
1714         if (sparc_cpu_model == sun4d)
1715                 ld_mmu_iounit();
1716         else
1717                 ld_mmu_iommu();
1718 #ifdef CONFIG_SMP
1719         if (sparc_cpu_model == sun4d)
1720                 sun4d_init_smp();
1721         else if (sparc_cpu_model == sparc_leon)
1722                 leon_init_smp();
1723         else
1724                 sun4m_init_smp();
1725 #endif
1726 }