arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/vmalloc.h>
  14 #include <linux/pagemap.h>
  15 #include <linux/init.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/bootmem.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/kdebug.h>
  21 #include <linux/log2.h>
  22 #include <linux/gfp.h>
  23
  24 #include <asm/bitext.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/io.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/asi.h>
  36 #include <asm/msi.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/io-unit.h>
  39 #include <asm/cacheflush.h>
  40 #include <asm/tlbflush.h>
  41
  42 /* Now the cpu specific definitions. */
  43 #include <asm/viking.h>
  44 #include <asm/mxcc.h>
  45 #include <asm/ross.h>
  46 #include <asm/tsunami.h>
  47 #include <asm/swift.h>
  48 #include <asm/turbosparc.h>
  49 #include <asm/leon.h>
  50
  51 #include <asm/btfixup.h>
  52
  53 enum mbus_module srmmu_modtype;
  54 static unsigned int hwbug_bitmask;
  55 int vac_cache_size;
  56 int vac_line_size;
  57
  58 struct ctx_list *ctx_list_pool;
  59 struct ctx_list ctx_free;
  60 struct ctx_list ctx_used;
  61
  62 extern struct resource sparc_iomap;
  63
  64 extern unsigned long last_valid_pfn;
  65
  66 static pgd_t *srmmu_swapper_pg_dir;
  67
  68 #ifdef CONFIG_SMP
  69 #define FLUSH_BEGIN(mm)
  70 #define FLUSH_END
  71 #else
  72 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  73 #define FLUSH_END       }
  74 #endif
  75
  76 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  77 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  78
  79 int flush_page_for_dma_global = 1;
  80
  81 #ifdef CONFIG_SMP
  82 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  83 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  84 #endif
  85
  86 char *srmmu_name;
  87
  88 ctxd_t *srmmu_ctx_table_phys;
  89 static ctxd_t *srmmu_context_table;
  90
  91 int viking_mxcc_present;
  92 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  93
  94 static int is_hypersparc;
  95
  96 static int srmmu_cache_pagetables;
  97
  98 /* these will be initialized in srmmu_nocache_calcsize() */
  99 static unsigned long srmmu_nocache_size;
 100 static unsigned long srmmu_nocache_end;
 101
 102 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 103 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 104
 105 /* The context table is a nocache user with the biggest alignment needs. */
 106 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 107
 108 void *srmmu_nocache_pool;
 109 void *srmmu_nocache_bitmap;
 110 static struct bit_map srmmu_nocache_map;
 111
 112 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 113 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 114
 115
 116 static inline int srmmu_pte_none(pte_t pte)
 117 { return !(pte_val(pte) & 0xFFFFFFF); }
 118
 119 static inline int srmmu_pte_present(pte_t pte)
 120 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 121
 122 static inline int srmmu_pmd_none(pmd_t pmd)
 123 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 124
 125 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 126 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 127
 128 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 129 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 130
 131 static inline pte_t srmmu_pte_mkold(pte_t pte)
 132 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 133
 134 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 135 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 136
 137 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 138 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 139
 140 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 141 { return __pte(pte_val(pte) | SRMMU_REF);}
 142
 143 /*
 144  * Conversion functions: convert a page and protection to a page entry,
 145  * and a page entry and page directory to the page they refer to.
 146  */
 147 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 148 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 149
 150 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 151 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 152
 153 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 154 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 155
 156 /* XXX should we hyper_flush_whole_icache here - Anton */
 157 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 158 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 159
 160 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 161 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 162
 163 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 164 {
 165         unsigned long ptp;      /* Physical address, shifted right by 4 */
 166         int i;
 167
 168         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 169         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 170                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 171                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 172         }
 173 }
 174
 175 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 176 {
 177         unsigned long ptp;      /* Physical address, shifted right by 4 */
 178         int i;
 179
 180         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 181         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 182                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 183                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 184         }
 185 }
 186
 187 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 188 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 189
 190 /* to find an entry in a top-level page table... */
 191 static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 192 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 193
 194 /* Find an entry in the second-level page table.. */
 195 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 196 {
 197         return (pmd_t *) srmmu_pgd_page(*dir) +
 198             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 199 }
 200
 201 /* Find an entry in the third-level page table.. */
 202 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 203 {
 204         void *pte;
 205
 206         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 207         return (pte_t *) pte +
 208             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 209 }
 210
 211 static unsigned long srmmu_swp_type(swp_entry_t entry)
 212 {
 213         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 214 }
 215
 216 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 217 {
 218         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 219 }
 220
 221 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 222 {
 223         return (swp_entry_t) {
 224                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 225                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 226 }
 227
 228 /*
 229  * size: bytes to allocate in the nocache area.
 230  * align: bytes, number to align at.
 231  * Returns the virtual address of the allocated area.
 232  */
 233 static unsigned long __srmmu_get_nocache(int size, int align)
 234 {
 235         int offset;
 236
 237         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 238                 printk("Size 0x%x too small for nocache request\n", size);
 239                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 240         }
 241         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 242                 printk("Size 0x%x unaligned int nocache request\n", size);
 243                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 244         }
 245         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 246
 247         offset = bit_map_string_get(&srmmu_nocache_map,
 248                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 249                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 250         if (offset == -1) {
 251                 printk("srmmu: out of nocache %d: %d/%d\n",
 252                     size, (int) srmmu_nocache_size,
 253                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 254                 return 0;
 255         }
 256
 257         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 258 }
 259
 260 static unsigned long srmmu_get_nocache(int size, int align)
 261 {
 262         unsigned long tmp;
 263
 264         tmp = __srmmu_get_nocache(size, align);
 265
 266         if (tmp)
 267                 memset((void *)tmp, 0, size);
 268
 269         return tmp;
 270 }
 271
 272 static void srmmu_free_nocache(unsigned long vaddr, int size)
 273 {
 274         int offset;
 275
 276         if (vaddr < SRMMU_NOCACHE_VADDR) {
 277                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 278                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 279                 BUG();
 280         }
 281         if (vaddr+size > srmmu_nocache_end) {
 282                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 283                     vaddr, srmmu_nocache_end);
 284                 BUG();
 285         }
 286         if (!is_power_of_2(size)) {
 287                 printk("Size 0x%x is not a power of 2\n", size);
 288                 BUG();
 289         }
 290         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 291                 printk("Size 0x%x is too small\n", size);
 292                 BUG();
 293         }
 294         if (vaddr & (size-1)) {
 295                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 296                 BUG();
 297         }
 298
 299         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 300         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 301
 302         bit_map_clear(&srmmu_nocache_map, offset, size);
 303 }
 304
 305 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
 306                                                  unsigned long end);
 307
 308 extern unsigned long probe_memory(void);        /* in fault.c */
 309
 310 /*
 311  * Reserve nocache dynamically proportionally to the amount of
 312  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 313  */
 314 static void srmmu_nocache_calcsize(void)
 315 {
 316         unsigned long sysmemavail = probe_memory() / 1024;
 317         int srmmu_nocache_npages;
 318
 319         srmmu_nocache_npages =
 320                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 321
 322  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 323         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 324         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 325                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 326
 327         /* anything above 1280 blows up */
 328         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 329                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 330
 331         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 332         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 333 }
 334
 335 static void __init srmmu_nocache_init(void)
 336 {
 337         unsigned int bitmap_bits;
 338         pgd_t *pgd;
 339         pmd_t *pmd;
 340         pte_t *pte;
 341         unsigned long paddr, vaddr;
 342         unsigned long pteval;
 343
 344         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 345
 346         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 347                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 348         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 349
 350         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 351         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 352
 353         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 354         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 355         init_mm.pgd = srmmu_swapper_pg_dir;
 356
 357         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 358
 359         paddr = __pa((unsigned long)srmmu_nocache_pool);
 360         vaddr = SRMMU_NOCACHE_VADDR;
 361
 362         while (vaddr < srmmu_nocache_end) {
 363                 pgd = pgd_offset_k(vaddr);
 364                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 365                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 366
 367                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 368
 369                 if (srmmu_cache_pagetables)
 370                         pteval |= SRMMU_CACHE;
 371
 372                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 373
 374                 vaddr += PAGE_SIZE;
 375                 paddr += PAGE_SIZE;
 376         }
 377
 378         flush_cache_all();
 379         flush_tlb_all();
 380 }
 381
 382 static inline pgd_t *srmmu_get_pgd_fast(void)
 383 {
 384         pgd_t *pgd = NULL;
 385
 386         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 387         if (pgd) {
 388                 pgd_t *init = pgd_offset_k(0);
 389                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 390                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 391                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 392         }
 393
 394         return pgd;
 395 }
 396
 397 static void srmmu_free_pgd_fast(pgd_t *pgd)
 398 {
 399         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 400 }
 401
 402 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 403 {
 404         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 405 }
 406
 407 static void srmmu_pmd_free(pmd_t * pmd)
 408 {
 409         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 410 }
 411
 412 /*
 413  * Hardware needs alignment to 256 only, but we align to whole page size
 414  * to reduce fragmentation problems due to the buddy principle.
 415  * XXX Provide actual fragmentation statistics in /proc.
 416  *
 417  * Alignments up to the page size are the same for physical and virtual
 418  * addresses of the nocache area.
 419  */
 420 static pte_t *
 421 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 422 {
 423         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 424 }
 425
 426 static pgtable_t
 427 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 428 {
 429         unsigned long pte;
 430         struct page *page;
 431
 432         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 433                 return NULL;
 434         page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 435         pgtable_page_ctor(page);
 436         return page;
 437 }
 438
 439 static void srmmu_free_pte_fast(pte_t *pte)
 440 {
 441         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 442 }
 443
 444 static void srmmu_pte_free(pgtable_t pte)
 445 {
 446         unsigned long p;
 447
 448         pgtable_page_dtor(pte);
 449         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 450         if (p == 0)
 451                 BUG();
 452         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 453         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 454         srmmu_free_nocache(p, PTE_SIZE);
 455 }
 456
 457 /*
 458  */
 459 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 460 {
 461         struct ctx_list *ctxp;
 462
 463         ctxp = ctx_free.next;
 464         if(ctxp != &ctx_free) {
 465                 remove_from_ctx_list(ctxp);
 466                 add_to_used_ctxlist(ctxp);
 467                 mm->context = ctxp->ctx_number;
 468                 ctxp->ctx_mm = mm;
 469                 return;
 470         }
 471         ctxp = ctx_used.next;
 472         if(ctxp->ctx_mm == old_mm)
 473                 ctxp = ctxp->next;
 474         if(ctxp == &ctx_used)
 475                 panic("out of mmu contexts");
 476         flush_cache_mm(ctxp->ctx_mm);
 477         flush_tlb_mm(ctxp->ctx_mm);
 478         remove_from_ctx_list(ctxp);
 479         add_to_used_ctxlist(ctxp);
 480         ctxp->ctx_mm->context = NO_CONTEXT;
 481         ctxp->ctx_mm = mm;
 482         mm->context = ctxp->ctx_number;
 483 }
 484
 485 static inline void free_context(int context)
 486 {
 487         struct ctx_list *ctx_old;
 488
 489         ctx_old = ctx_list_pool + context;
 490         remove_from_ctx_list(ctx_old);
 491         add_to_free_ctxlist(ctx_old);
 492 }
 493
 494
 495 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 496                struct task_struct *tsk)
 497 {
 498         if(mm->context == NO_CONTEXT) {
 499                 spin_lock(&srmmu_context_spinlock);
 500                 alloc_context(old_mm, mm);
 501                 spin_unlock(&srmmu_context_spinlock);
 502                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 503         }
 504
 505         if (sparc_cpu_model == sparc_leon)
 506                 leon_switch_mm();
 507
 508         if (is_hypersparc)
 509                 hyper_flush_whole_icache();
 510
 511         srmmu_set_context(mm->context);
 512 }
 513
 514 /* Low level IO area allocation on the SRMMU. */
 515 static inline void srmmu_mapioaddr(unsigned long physaddr,
 516     unsigned long virt_addr, int bus_type)
 517 {
 518         pgd_t *pgdp;
 519         pmd_t *pmdp;
 520         pte_t *ptep;
 521         unsigned long tmp;
 522
 523         physaddr &= PAGE_MASK;
 524         pgdp = pgd_offset_k(virt_addr);
 525         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 526         ptep = srmmu_pte_offset(pmdp, virt_addr);
 527         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 528
 529         /*
 530          * I need to test whether this is consistent over all
 531          * sun4m's.  The bus_type represents the upper 4 bits of
 532          * 36-bit physical address on the I/O space lines...
 533          */
 534         tmp |= (bus_type << 28);
 535         tmp |= SRMMU_PRIV;
 536         __flush_page_to_ram(virt_addr);
 537         srmmu_set_pte(ptep, __pte(tmp));
 538 }
 539
 540 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 541     unsigned long xva, unsigned int len)
 542 {
 543         while (len != 0) {
 544                 len -= PAGE_SIZE;
 545                 srmmu_mapioaddr(xpa, xva, bus);
 546                 xva += PAGE_SIZE;
 547                 xpa += PAGE_SIZE;
 548         }
 549         flush_tlb_all();
 550 }
 551
 552 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 553 {
 554         pgd_t *pgdp;
 555         pmd_t *pmdp;
 556         pte_t *ptep;
 557
 558         pgdp = pgd_offset_k(virt_addr);
 559         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 560         ptep = srmmu_pte_offset(pmdp, virt_addr);
 561
 562         /* No need to flush uncacheable page. */
 563         __pte_clear(ptep);
 564 }
 565
 566 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 567 {
 568         while (len != 0) {
 569                 len -= PAGE_SIZE;
 570                 srmmu_unmapioaddr(virt_addr);
 571                 virt_addr += PAGE_SIZE;
 572         }
 573         flush_tlb_all();
 574 }
 575
 576 /*
 577  * On the SRMMU we do not have the problems with limited tlb entries
 578  * for mapping kernel pages, so we just take things from the free page
 579  * pool.  As a side effect we are putting a little too much pressure
 580  * on the gfp() subsystem.  This setup also makes the logic of the
 581  * iommu mapping code a lot easier as we can transparently handle
 582  * mappings on the kernel stack without any special code.
 583  */
 584 struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
 585 {
 586         struct thread_info *ret;
 587
 588         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 589                                                      THREAD_INFO_ORDER);
 590 #ifdef CONFIG_DEBUG_STACK_USAGE
 591         if (ret)
 592                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 593 #endif /* DEBUG_STACK_USAGE */
 594
 595         return ret;
 596 }
 597
 598 void free_thread_info(struct thread_info *ti)
 599 {
 600         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 601 }
 602
 603 /* tsunami.S */
 604 extern void tsunami_flush_cache_all(void);
 605 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 606 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 607 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 608 extern void tsunami_flush_page_to_ram(unsigned long page);
 609 extern void tsunami_flush_page_for_dma(unsigned long page);
 610 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 611 extern void tsunami_flush_tlb_all(void);
 612 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 613 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 614 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 615 extern void tsunami_setup_blockops(void);
 616
 617 /*
 618  * Workaround, until we find what's going on with Swift. When low on memory,
 619  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 620  * out it is already in page tables/ fault again on the same instruction.
 621  * I really don't understand it, have checked it and contexts
 622  * are right, flush_tlb_all is done as well, and it faults again...
 623  * Strange. -jj
 624  *
 625  * The following code is a deadwood that may be necessary when
 626  * we start to make precise page flushes again. --zaitcev
 627  */
 628 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
 629 {
 630 #if 0
 631         static unsigned long last;
 632         unsigned int val;
 633         /* unsigned int n; */
 634
 635         if (address == last) {
 636                 val = srmmu_hwprobe(address);
 637                 if (val != 0 && pte_val(*ptep) != val) {
 638                         printk("swift_update_mmu_cache: "
 639                             "addr %lx put %08x probed %08x from %pf\n",
 640                             address, pte_val(*ptep), val,
 641                             __builtin_return_address(0));
 642                         srmmu_flush_whole_tlb();
 643                 }
 644         }
 645         last = address;
 646 #endif
 647 }
 648
 649 /* swift.S */
 650 extern void swift_flush_cache_all(void);
 651 extern void swift_flush_cache_mm(struct mm_struct *mm);
 652 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 653                                     unsigned long start, unsigned long end);
 654 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 655 extern void swift_flush_page_to_ram(unsigned long page);
 656 extern void swift_flush_page_for_dma(unsigned long page);
 657 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 658 extern void swift_flush_tlb_all(void);
 659 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 660 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 661                                   unsigned long start, unsigned long end);
 662 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 663
 664 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 665 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 666 {
 667         int cctx, ctx1;
 668
 669         page &= PAGE_MASK;
 670         if ((ctx1 = vma->vm_mm->context) != -1) {
 671                 cctx = srmmu_get_context();
 672 /* Is context # ever different from current context? P3 */
 673                 if (cctx != ctx1) {
 674                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 675                         srmmu_set_context(ctx1);
 676                         swift_flush_page(page);
 677                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 678                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 679                         srmmu_set_context(cctx);
 680                 } else {
 681                          /* Rm. prot. bits from virt. c. */
 682                         /* swift_flush_cache_all(); */
 683                         /* swift_flush_cache_page(vma, page); */
 684                         swift_flush_page(page);
 685
 686                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 687                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 688                         /* same as above: srmmu_flush_tlb_page() */
 689                 }
 690         }
 691 }
 692 #endif
 693
 694 /*
 695  * The following are all MBUS based SRMMU modules, and therefore could
 696  * be found in a multiprocessor configuration.  On the whole, these
 697  * chips seems to be much more touchy about DVMA and page tables
 698  * with respect to cache coherency.
 699  */
 700
 701 /* Cypress flushes. */
 702 static void cypress_flush_cache_all(void)
 703 {
 704         volatile unsigned long cypress_sucks;
 705         unsigned long faddr, tagval;
 706
 707         flush_user_windows();
 708         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 709                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 710                                      "=r" (tagval) :
 711                                      "r" (faddr), "r" (0x40000),
 712                                      "i" (ASI_M_DATAC_TAG));
 713
 714                 /* If modified and valid, kick it. */
 715                 if((tagval & 0x60) == 0x60)
 716                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 717         }
 718 }
 719
 720 static void cypress_flush_cache_mm(struct mm_struct *mm)
 721 {
 722         register unsigned long a, b, c, d, e, f, g;
 723         unsigned long flags, faddr;
 724         int octx;
 725
 726         FLUSH_BEGIN(mm)
 727         flush_user_windows();
 728         local_irq_save(flags);
 729         octx = srmmu_get_context();
 730         srmmu_set_context(mm->context);
 731         a = 0x20; b = 0x40; c = 0x60;
 732         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 733
 734         faddr = (0x10000 - 0x100);
 735         goto inside;
 736         do {
 737                 faddr -= 0x100;
 738         inside:
 739                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 740                                      "sta %%g0, [%0 + %2] %1\n\t"
 741                                      "sta %%g0, [%0 + %3] %1\n\t"
 742                                      "sta %%g0, [%0 + %4] %1\n\t"
 743                                      "sta %%g0, [%0 + %5] %1\n\t"
 744                                      "sta %%g0, [%0 + %6] %1\n\t"
 745                                      "sta %%g0, [%0 + %7] %1\n\t"
 746                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 747                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 748                                      "r" (a), "r" (b), "r" (c), "r" (d),
 749                                      "r" (e), "r" (f), "r" (g));
 750         } while(faddr);
 751         srmmu_set_context(octx);
 752         local_irq_restore(flags);
 753         FLUSH_END
 754 }
 755
 756 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 757 {
 758         struct mm_struct *mm = vma->vm_mm;
 759         register unsigned long a, b, c, d, e, f, g;
 760         unsigned long flags, faddr;
 761         int octx;
 762
 763         FLUSH_BEGIN(mm)
 764         flush_user_windows();
 765         local_irq_save(flags);
 766         octx = srmmu_get_context();
 767         srmmu_set_context(mm->context);
 768         a = 0x20; b = 0x40; c = 0x60;
 769         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 770
 771         start &= SRMMU_REAL_PMD_MASK;
 772         while(start < end) {
 773                 faddr = (start + (0x10000 - 0x100));
 774                 goto inside;
 775                 do {
 776                         faddr -= 0x100;
 777                 inside:
 778                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 779                                              "sta %%g0, [%0 + %2] %1\n\t"
 780                                              "sta %%g0, [%0 + %3] %1\n\t"
 781                                              "sta %%g0, [%0 + %4] %1\n\t"
 782                                              "sta %%g0, [%0 + %5] %1\n\t"
 783                                              "sta %%g0, [%0 + %6] %1\n\t"
 784                                              "sta %%g0, [%0 + %7] %1\n\t"
 785                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 786                                              "r" (faddr),
 787                                              "i" (ASI_M_FLUSH_SEG),
 788                                              "r" (a), "r" (b), "r" (c), "r" (d),
 789                                              "r" (e), "r" (f), "r" (g));
 790                 } while (faddr != start);
 791                 start += SRMMU_REAL_PMD_SIZE;
 792         }
 793         srmmu_set_context(octx);
 794         local_irq_restore(flags);
 795         FLUSH_END
 796 }
 797
 798 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 799 {
 800         register unsigned long a, b, c, d, e, f, g;
 801         struct mm_struct *mm = vma->vm_mm;
 802         unsigned long flags, line;
 803         int octx;
 804
 805         FLUSH_BEGIN(mm)
 806         flush_user_windows();
 807         local_irq_save(flags);
 808         octx = srmmu_get_context();
 809         srmmu_set_context(mm->context);
 810         a = 0x20; b = 0x40; c = 0x60;
 811         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 812
 813         page &= PAGE_MASK;
 814         line = (page + PAGE_SIZE) - 0x100;
 815         goto inside;
 816         do {
 817                 line -= 0x100;
 818         inside:
 819                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 820                                              "sta %%g0, [%0 + %2] %1\n\t"
 821                                              "sta %%g0, [%0 + %3] %1\n\t"
 822                                              "sta %%g0, [%0 + %4] %1\n\t"
 823                                              "sta %%g0, [%0 + %5] %1\n\t"
 824                                              "sta %%g0, [%0 + %6] %1\n\t"
 825                                              "sta %%g0, [%0 + %7] %1\n\t"
 826                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 827                                              "r" (line),
 828                                              "i" (ASI_M_FLUSH_PAGE),
 829                                              "r" (a), "r" (b), "r" (c), "r" (d),
 830                                              "r" (e), "r" (f), "r" (g));
 831         } while(line != page);
 832         srmmu_set_context(octx);
 833         local_irq_restore(flags);
 834         FLUSH_END
 835 }
 836
 837 /* Cypress is copy-back, at least that is how we configure it. */
 838 static void cypress_flush_page_to_ram(unsigned long page)
 839 {
 840         register unsigned long a, b, c, d, e, f, g;
 841         unsigned long line;
 842
 843         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 844         page &= PAGE_MASK;
 845         line = (page + PAGE_SIZE) - 0x100;
 846         goto inside;
 847         do {
 848                 line -= 0x100;
 849         inside:
 850                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 851                                      "sta %%g0, [%0 + %2] %1\n\t"
 852                                      "sta %%g0, [%0 + %3] %1\n\t"
 853                                      "sta %%g0, [%0 + %4] %1\n\t"
 854                                      "sta %%g0, [%0 + %5] %1\n\t"
 855                                      "sta %%g0, [%0 + %6] %1\n\t"
 856                                      "sta %%g0, [%0 + %7] %1\n\t"
 857                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 858                                      "r" (line),
 859                                      "i" (ASI_M_FLUSH_PAGE),
 860                                      "r" (a), "r" (b), "r" (c), "r" (d),
 861                                      "r" (e), "r" (f), "r" (g));
 862         } while(line != page);
 863 }
 864
 865 /* Cypress is also IO cache coherent. */
 866 static void cypress_flush_page_for_dma(unsigned long page)
 867 {
 868 }
 869
 870 /* Cypress has unified L2 VIPT, from which both instructions and data
 871  * are stored.  It does not have an onboard icache of any sort, therefore
 872  * no flush is necessary.
 873  */
 874 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 875 {
 876 }
 877
 878 static void cypress_flush_tlb_all(void)
 879 {
 880         srmmu_flush_whole_tlb();
 881 }
 882
 883 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 884 {
 885         FLUSH_BEGIN(mm)
 886         __asm__ __volatile__(
 887         "lda    [%0] %3, %%g5\n\t"
 888         "sta    %2, [%0] %3\n\t"
 889         "sta    %%g0, [%1] %4\n\t"
 890         "sta    %%g5, [%0] %3\n"
 891         : /* no outputs */
 892         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 893           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 894         : "g5");
 895         FLUSH_END
 896 }
 897
 898 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 899 {
 900         struct mm_struct *mm = vma->vm_mm;
 901         unsigned long size;
 902
 903         FLUSH_BEGIN(mm)
 904         start &= SRMMU_PGDIR_MASK;
 905         size = SRMMU_PGDIR_ALIGN(end) - start;
 906         __asm__ __volatile__(
 907                 "lda    [%0] %5, %%g5\n\t"
 908                 "sta    %1, [%0] %5\n"
 909                 "1:\n\t"
 910                 "subcc  %3, %4, %3\n\t"
 911                 "bne    1b\n\t"
 912                 " sta   %%g0, [%2 + %3] %6\n\t"
 913                 "sta    %%g5, [%0] %5\n"
 914         : /* no outputs */
 915         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 916           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 917           "i" (ASI_M_FLUSH_PROBE)
 918         : "g5", "cc");
 919         FLUSH_END
 920 }
 921
 922 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 923 {
 924         struct mm_struct *mm = vma->vm_mm;
 925
 926         FLUSH_BEGIN(mm)
 927         __asm__ __volatile__(
 928         "lda    [%0] %3, %%g5\n\t"
 929         "sta    %1, [%0] %3\n\t"
 930         "sta    %%g0, [%2] %4\n\t"
 931         "sta    %%g5, [%0] %3\n"
 932         : /* no outputs */
 933         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 934           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 935         : "g5");
 936         FLUSH_END
 937 }
 938
 939 /* viking.S */
 940 extern void viking_flush_cache_all(void);
 941 extern void viking_flush_cache_mm(struct mm_struct *mm);
 942 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
 943                                      unsigned long end);
 944 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 945 extern void viking_flush_page_to_ram(unsigned long page);
 946 extern void viking_flush_page_for_dma(unsigned long page);
 947 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
 948 extern void viking_flush_page(unsigned long page);
 949 extern void viking_mxcc_flush_page(unsigned long page);
 950 extern void viking_flush_tlb_all(void);
 951 extern void viking_flush_tlb_mm(struct mm_struct *mm);
 952 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 953                                    unsigned long end);
 954 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
 955                                   unsigned long page);
 956 extern void sun4dsmp_flush_tlb_all(void);
 957 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
 958 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 959                                    unsigned long end);
 960 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
 961                                   unsigned long page);
 962
 963 /* hypersparc.S */
 964 extern void hypersparc_flush_cache_all(void);
 965 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
 966 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 967 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 968 extern void hypersparc_flush_page_to_ram(unsigned long page);
 969 extern void hypersparc_flush_page_for_dma(unsigned long page);
 970 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 971 extern void hypersparc_flush_tlb_all(void);
 972 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
 973 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 974 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 975 extern void hypersparc_setup_blockops(void);
 976
 977 /*
 978  * NOTE: All of this startup code assumes the low 16mb (approx.) of
 979  *       kernel mappings are done with one single contiguous chunk of
 980  *       ram.  On small ram machines (classics mainly) we only get
 981  *       around 8mb mapped for us.
 982  */
 983
 984 static void __init early_pgtable_allocfail(char *type)
 985 {
 986         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
 987         prom_halt();
 988 }
 989
 990 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
 991                                                         unsigned long end)
 992 {
 993         pgd_t *pgdp;
 994         pmd_t *pmdp;
 995         pte_t *ptep;
 996
 997         while(start < end) {
 998                 pgdp = pgd_offset_k(start);
 999                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1000                         pmdp = (pmd_t *) __srmmu_get_nocache(
1001                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1002                         if (pmdp == NULL)
1003                                 early_pgtable_allocfail("pmd");
1004                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1005                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1006                 }
1007                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1008                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1009                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1010                         if (ptep == NULL)
1011                                 early_pgtable_allocfail("pte");
1012                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1013                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1014                 }
1015                 if (start > (0xffffffffUL - PMD_SIZE))
1016                         break;
1017                 start = (start + PMD_SIZE) & PMD_MASK;
1018         }
1019 }
1020
1021 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
1022                                                   unsigned long end)
1023 {
1024         pgd_t *pgdp;
1025         pmd_t *pmdp;
1026         pte_t *ptep;
1027
1028         while(start < end) {
1029                 pgdp = pgd_offset_k(start);
1030                 if (pgd_none(*pgdp)) {
1031                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1032                         if (pmdp == NULL)
1033                                 early_pgtable_allocfail("pmd");
1034                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1035                         srmmu_pgd_set(pgdp, pmdp);
1036                 }
1037                 pmdp = srmmu_pmd_offset(pgdp, start);
1038                 if(srmmu_pmd_none(*pmdp)) {
1039                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1040                                                              PTE_SIZE);
1041                         if (ptep == NULL)
1042                                 early_pgtable_allocfail("pte");
1043                         memset(ptep, 0, PTE_SIZE);
1044                         srmmu_pmd_set(pmdp, ptep);
1045                 }
1046                 if (start > (0xffffffffUL - PMD_SIZE))
1047                         break;
1048                 start = (start + PMD_SIZE) & PMD_MASK;
1049         }
1050 }
1051
1052 /*
1053  * This is much cleaner than poking around physical address space
1054  * looking at the prom's page table directly which is what most
1055  * other OS's do.  Yuck... this is much better.
1056  */
1057 static void __init srmmu_inherit_prom_mappings(unsigned long start,
1058                                                unsigned long end)
1059 {
1060         pgd_t *pgdp;
1061         pmd_t *pmdp;
1062         pte_t *ptep;
1063         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1064         unsigned long prompte;
1065
1066         while(start <= end) {
1067                 if (start == 0)
1068                         break; /* probably wrap around */
1069                 if(start == 0xfef00000)
1070                         start = KADB_DEBUGGER_BEGVM;
1071                 if(!(prompte = srmmu_hwprobe(start))) {
1072                         start += PAGE_SIZE;
1073                         continue;
1074                 }
1075
1076                 /* A red snapper, see what it really is. */
1077                 what = 0;
1078
1079                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1080                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1081                                 what = 1;
1082                 }
1083
1084                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1085                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1086                            prompte)
1087                                 what = 2;
1088                 }
1089
1090                 pgdp = pgd_offset_k(start);
1091                 if(what == 2) {
1092                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1093                         start += SRMMU_PGDIR_SIZE;
1094                         continue;
1095                 }
1096                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1097                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1098                         if (pmdp == NULL)
1099                                 early_pgtable_allocfail("pmd");
1100                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1101                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1102                 }
1103                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1104                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1105                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1106                                                              PTE_SIZE);
1107                         if (ptep == NULL)
1108                                 early_pgtable_allocfail("pte");
1109                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1110                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1111                 }
1112                 if(what == 1) {
1113                         /*
1114                          * We bend the rule where all 16 PTPs in a pmd_t point
1115                          * inside the same PTE page, and we leak a perfectly
1116                          * good hardware PTE piece. Alternatives seem worse.
1117                          */
1118                         unsigned int x; /* Index of HW PMD in soft cluster */
1119                         x = (start >> PMD_SHIFT) & 15;
1120                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1121                         start += SRMMU_REAL_PMD_SIZE;
1122                         continue;
1123                 }
1124                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1125                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1126                 start += PAGE_SIZE;
1127         }
1128 }
1129
1130 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1131
1132 /* Create a third-level SRMMU 16MB page mapping. */
1133 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1134 {
1135         pgd_t *pgdp = pgd_offset_k(vaddr);
1136         unsigned long big_pte;
1137
1138         big_pte = KERNEL_PTE(phys_base >> 4);
1139         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1140 }
1141
1142 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1143 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1144 {
1145         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1146         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1147         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1148         /* Map "low" memory only */
1149         const unsigned long min_vaddr = PAGE_OFFSET;
1150         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1151
1152         if (vstart < min_vaddr || vstart >= max_vaddr)
1153                 return vstart;
1154
1155         if (vend > max_vaddr || vend < min_vaddr)
1156                 vend = max_vaddr;
1157
1158         while(vstart < vend) {
1159                 do_large_mapping(vstart, pstart);
1160                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1161         }
1162         return vstart;
1163 }
1164
1165 static inline void memprobe_error(char *msg)
1166 {
1167         prom_printf(msg);
1168         prom_printf("Halting now...\n");
1169         prom_halt();
1170 }
1171
1172 static inline void map_kernel(void)
1173 {
1174         int i;
1175
1176         if (phys_base > 0) {
1177                 do_large_mapping(PAGE_OFFSET, phys_base);
1178         }
1179
1180         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1181                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1182         }
1183 }
1184
1185 /* Paging initialization on the Sparc Reference MMU. */
1186 extern void sparc_context_init(int);
1187
1188 void (*poke_srmmu)(void) __cpuinitdata = NULL;
1189
1190 extern unsigned long bootmem_init(unsigned long *pages_avail);
1191
1192 void __init srmmu_paging_init(void)
1193 {
1194         int i;
1195         phandle cpunode;
1196         char node_str[128];
1197         pgd_t *pgd;
1198         pmd_t *pmd;
1199         pte_t *pte;
1200         unsigned long pages_avail;
1201
1202         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1203
1204         if (sparc_cpu_model == sun4d)
1205                 num_contexts = 65536; /* We know it is Viking */
1206         else {
1207                 /* Find the number of contexts on the srmmu. */
1208                 cpunode = prom_getchild(prom_root_node);
1209                 num_contexts = 0;
1210                 while(cpunode != 0) {
1211                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1212                         if(!strcmp(node_str, "cpu")) {
1213                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1214                                 break;
1215                         }
1216                         cpunode = prom_getsibling(cpunode);
1217                 }
1218         }
1219
1220         if(!num_contexts) {
1221                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1222                 prom_halt();
1223         }
1224
1225         pages_avail = 0;
1226         last_valid_pfn = bootmem_init(&pages_avail);
1227
1228         srmmu_nocache_calcsize();
1229         srmmu_nocache_init();
1230         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1231         map_kernel();
1232
1233         /* ctx table has to be physically aligned to its size */
1234         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1235         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1236
1237         for(i = 0; i < num_contexts; i++)
1238                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1239
1240         flush_cache_all();
1241         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1242 #ifdef CONFIG_SMP
1243         /* Stop from hanging here... */
1244         local_flush_tlb_all();
1245 #else
1246         flush_tlb_all();
1247 #endif
1248         poke_srmmu();
1249
1250         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1251         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1252
1253         srmmu_allocate_ptable_skeleton(
1254                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1255         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1256
1257         pgd = pgd_offset_k(PKMAP_BASE);
1258         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1259         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1260         pkmap_page_table = pte;
1261
1262         flush_cache_all();
1263         flush_tlb_all();
1264
1265         sparc_context_init(num_contexts);
1266
1267         kmap_init();
1268
1269         {
1270                 unsigned long zones_size[MAX_NR_ZONES];
1271                 unsigned long zholes_size[MAX_NR_ZONES];
1272                 unsigned long npages;
1273                 int znum;
1274
1275                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1276                         zones_size[znum] = zholes_size[znum] = 0;
1277
1278                 npages = max_low_pfn - pfn_base;
1279
1280                 zones_size[ZONE_DMA] = npages;
1281                 zholes_size[ZONE_DMA] = npages - pages_avail;
1282
1283                 npages = highend_pfn - max_low_pfn;
1284                 zones_size[ZONE_HIGHMEM] = npages;
1285                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1286
1287                 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1288         }
1289 }
1290
1291 static void srmmu_mmu_info(struct seq_file *m)
1292 {
1293         seq_printf(m,
1294                    "MMU type\t: %s\n"
1295                    "contexts\t: %d\n"
1296                    "nocache total\t: %ld\n"
1297                    "nocache used\t: %d\n",
1298                    srmmu_name,
1299                    num_contexts,
1300                    srmmu_nocache_size,
1301                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1302 }
1303
1304 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1305 {
1306 }
1307
1308 static void srmmu_destroy_context(struct mm_struct *mm)
1309 {
1310
1311         if(mm->context != NO_CONTEXT) {
1312                 flush_cache_mm(mm);
1313                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1314                 flush_tlb_mm(mm);
1315                 spin_lock(&srmmu_context_spinlock);
1316                 free_context(mm->context);
1317                 spin_unlock(&srmmu_context_spinlock);
1318                 mm->context = NO_CONTEXT;
1319         }
1320 }
1321
1322 /* Init various srmmu chip types. */
1323 static void __init srmmu_is_bad(void)
1324 {
1325         prom_printf("Could not determine SRMMU chip type.\n");
1326         prom_halt();
1327 }
1328
1329 static void __init init_vac_layout(void)
1330 {
1331         phandle nd;
1332         int cache_lines;
1333         char node_str[128];
1334 #ifdef CONFIG_SMP
1335         int cpu = 0;
1336         unsigned long max_size = 0;
1337         unsigned long min_line_size = 0x10000000;
1338 #endif
1339
1340         nd = prom_getchild(prom_root_node);
1341         while((nd = prom_getsibling(nd)) != 0) {
1342                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1343                 if(!strcmp(node_str, "cpu")) {
1344                         vac_line_size = prom_getint(nd, "cache-line-size");
1345                         if (vac_line_size == -1) {
1346                                 prom_printf("can't determine cache-line-size, "
1347                                             "halting.\n");
1348                                 prom_halt();
1349                         }
1350                         cache_lines = prom_getint(nd, "cache-nlines");
1351                         if (cache_lines == -1) {
1352                                 prom_printf("can't determine cache-nlines, halting.\n");
1353                                 prom_halt();
1354                         }
1355
1356                         vac_cache_size = cache_lines * vac_line_size;
1357 #ifdef CONFIG_SMP
1358                         if(vac_cache_size > max_size)
1359                                 max_size = vac_cache_size;
1360                         if(vac_line_size < min_line_size)
1361                                 min_line_size = vac_line_size;
1362                         //FIXME: cpus not contiguous!!
1363                         cpu++;
1364                         if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1365                                 break;
1366 #else
1367                         break;
1368 #endif
1369                 }
1370         }
1371         if(nd == 0) {
1372                 prom_printf("No CPU nodes found, halting.\n");
1373                 prom_halt();
1374         }
1375 #ifdef CONFIG_SMP
1376         vac_cache_size = max_size;
1377         vac_line_size = min_line_size;
1378 #endif
1379         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1380                (int)vac_cache_size, (int)vac_line_size);
1381 }
1382
1383 static void __cpuinit poke_hypersparc(void)
1384 {
1385         volatile unsigned long clear;
1386         unsigned long mreg = srmmu_get_mmureg();
1387
1388         hyper_flush_unconditional_combined();
1389
1390         mreg &= ~(HYPERSPARC_CWENABLE);
1391         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1392         mreg |= (HYPERSPARC_CMODE);
1393
1394         srmmu_set_mmureg(mreg);
1395
1396 #if 0 /* XXX I think this is bad news... -DaveM */
1397         hyper_clear_all_tags();
1398 #endif
1399
1400         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1401         hyper_flush_whole_icache();
1402         clear = srmmu_get_faddr();
1403         clear = srmmu_get_fstatus();
1404 }
1405
1406 static void __init init_hypersparc(void)
1407 {
1408         srmmu_name = "ROSS HyperSparc";
1409         srmmu_modtype = HyperSparc;
1410
1411         init_vac_layout();
1412
1413         is_hypersparc = 1;
1414
1415         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1416         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1417         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1418         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1419
1420         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1421         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1422         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1423         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1424
1425         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1426         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1427         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1428
1429
1430         poke_srmmu = poke_hypersparc;
1431
1432         hypersparc_setup_blockops();
1433 }
1434
1435 static void __cpuinit poke_cypress(void)
1436 {
1437         unsigned long mreg = srmmu_get_mmureg();
1438         unsigned long faddr, tagval;
1439         volatile unsigned long cypress_sucks;
1440         volatile unsigned long clear;
1441
1442         clear = srmmu_get_faddr();
1443         clear = srmmu_get_fstatus();
1444
1445         if (!(mreg & CYPRESS_CENABLE)) {
1446                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1447                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1448                                              "sta %%g0, [%0] %2\n\t" : :
1449                                              "r" (faddr), "r" (0x40000),
1450                                              "i" (ASI_M_DATAC_TAG));
1451                 }
1452         } else {
1453                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1454                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1455                                              "=r" (tagval) :
1456                                              "r" (faddr), "r" (0x40000),
1457                                              "i" (ASI_M_DATAC_TAG));
1458
1459                         /* If modified and valid, kick it. */
1460                         if((tagval & 0x60) == 0x60)
1461                                 cypress_sucks = *(unsigned long *)
1462                                                         (0xf0020000 + faddr);
1463                 }
1464         }
1465
1466         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1467         clear = srmmu_get_faddr();
1468         clear = srmmu_get_fstatus();
1469
1470         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1471         srmmu_set_mmureg(mreg);
1472 }
1473
1474 static void __init init_cypress_common(void)
1475 {
1476         init_vac_layout();
1477
1478         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1479         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1480         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1481         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1482
1483         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1484         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1485         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1486         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1487
1488
1489         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1490         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1491         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1492
1493         poke_srmmu = poke_cypress;
1494 }
1495
1496 static void __init init_cypress_604(void)
1497 {
1498         srmmu_name = "ROSS Cypress-604(UP)";
1499         srmmu_modtype = Cypress;
1500         init_cypress_common();
1501 }
1502
1503 static void __init init_cypress_605(unsigned long mrev)
1504 {
1505         srmmu_name = "ROSS Cypress-605(MP)";
1506         if(mrev == 0xe) {
1507                 srmmu_modtype = Cypress_vE;
1508                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1509         } else {
1510                 if(mrev == 0xd) {
1511                         srmmu_modtype = Cypress_vD;
1512                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1513                 } else {
1514                         srmmu_modtype = Cypress;
1515                 }
1516         }
1517         init_cypress_common();
1518 }
1519
1520 static void __cpuinit poke_swift(void)
1521 {
1522         unsigned long mreg;
1523
1524         /* Clear any crap from the cache or else... */
1525         swift_flush_cache_all();
1526
1527         /* Enable I & D caches */
1528         mreg = srmmu_get_mmureg();
1529         mreg |= (SWIFT_IE | SWIFT_DE);
1530         /*
1531          * The Swift branch folding logic is completely broken.  At
1532          * trap time, if things are just right, if can mistakenly
1533          * think that a trap is coming from kernel mode when in fact
1534          * it is coming from user mode (it mis-executes the branch in
1535          * the trap code).  So you see things like crashme completely
1536          * hosing your machine which is completely unacceptable.  Turn
1537          * this shit off... nice job Fujitsu.
1538          */
1539         mreg &= ~(SWIFT_BF);
1540         srmmu_set_mmureg(mreg);
1541 }
1542
1543 #define SWIFT_MASKID_ADDR  0x10003018
1544 static void __init init_swift(void)
1545 {
1546         unsigned long swift_rev;
1547
1548         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1549                              "srl %0, 0x18, %0\n\t" :
1550                              "=r" (swift_rev) :
1551                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1552         srmmu_name = "Fujitsu Swift";
1553         switch(swift_rev) {
1554         case 0x11:
1555         case 0x20:
1556         case 0x23:
1557         case 0x30:
1558                 srmmu_modtype = Swift_lots_o_bugs;
1559                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1560                 /*
1561                  * Gee george, I wonder why Sun is so hush hush about
1562                  * this hardware bug... really braindamage stuff going
1563                  * on here.  However I think we can find a way to avoid
1564                  * all of the workaround overhead under Linux.  Basically,
1565                  * any page fault can cause kernel pages to become user
1566                  * accessible (the mmu gets confused and clears some of
1567                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1568                  * horrible eh?  But wait, after extensive testing it appears
1569                  * that if you use pgd_t level large kernel pte's (like the
1570                  * 4MB pages on the Pentium) the bug does not get tripped
1571                  * at all.  This avoids almost all of the major overhead.
1572                  * Welcome to a world where your vendor tells you to,
1573                  * "apply this kernel patch" instead of "sorry for the
1574                  * broken hardware, send it back and we'll give you
1575                  * properly functioning parts"
1576                  */
1577                 break;
1578         case 0x25:
1579         case 0x31:
1580                 srmmu_modtype = Swift_bad_c;
1581                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1582                 /*
1583                  * You see Sun allude to this hardware bug but never
1584                  * admit things directly, they'll say things like,
1585                  * "the Swift chip cache problems" or similar.
1586                  */
1587                 break;
1588         default:
1589                 srmmu_modtype = Swift_ok;
1590                 break;
1591         }
1592
1593         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1594         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1595         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1596         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1597
1598
1599         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1600         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1601         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1602         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1603
1604         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1605         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1606         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1607
1608         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1609
1610         flush_page_for_dma_global = 0;
1611
1612         /*
1613          * Are you now convinced that the Swift is one of the
1614          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1615          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1616          * you examined the microcode of the Swift you'd find
1617          * XXX's all over the place.
1618          */
1619         poke_srmmu = poke_swift;
1620 }
1621
1622 static void turbosparc_flush_cache_all(void)
1623 {
1624         flush_user_windows();
1625         turbosparc_idflash_clear();
1626 }
1627
1628 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1629 {
1630         FLUSH_BEGIN(mm)
1631         flush_user_windows();
1632         turbosparc_idflash_clear();
1633         FLUSH_END
1634 }
1635
1636 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1637 {
1638         FLUSH_BEGIN(vma->vm_mm)
1639         flush_user_windows();
1640         turbosparc_idflash_clear();
1641         FLUSH_END
1642 }
1643
1644 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1645 {
1646         FLUSH_BEGIN(vma->vm_mm)
1647         flush_user_windows();
1648         if (vma->vm_flags & VM_EXEC)
1649                 turbosparc_flush_icache();
1650         turbosparc_flush_dcache();
1651         FLUSH_END
1652 }
1653
1654 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1655 static void turbosparc_flush_page_to_ram(unsigned long page)
1656 {
1657 #ifdef TURBOSPARC_WRITEBACK
1658         volatile unsigned long clear;
1659
1660         if (srmmu_hwprobe(page))
1661                 turbosparc_flush_page_cache(page);
1662         clear = srmmu_get_fstatus();
1663 #endif
1664 }
1665
1666 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1667 {
1668 }
1669
1670 static void turbosparc_flush_page_for_dma(unsigned long page)
1671 {
1672         turbosparc_flush_dcache();
1673 }
1674
1675 static void turbosparc_flush_tlb_all(void)
1676 {
1677         srmmu_flush_whole_tlb();
1678 }
1679
1680 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1681 {
1682         FLUSH_BEGIN(mm)
1683         srmmu_flush_whole_tlb();
1684         FLUSH_END
1685 }
1686
1687 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1688 {
1689         FLUSH_BEGIN(vma->vm_mm)
1690         srmmu_flush_whole_tlb();
1691         FLUSH_END
1692 }
1693
1694 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1695 {
1696         FLUSH_BEGIN(vma->vm_mm)
1697         srmmu_flush_whole_tlb();
1698         FLUSH_END
1699 }
1700
1701
1702 static void __cpuinit poke_turbosparc(void)
1703 {
1704         unsigned long mreg = srmmu_get_mmureg();
1705         unsigned long ccreg;
1706
1707         /* Clear any crap from the cache or else... */
1708         turbosparc_flush_cache_all();
1709         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1710         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1711         srmmu_set_mmureg(mreg);
1712
1713         ccreg = turbosparc_get_ccreg();
1714
1715 #ifdef TURBOSPARC_WRITEBACK
1716         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1717         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1718                         /* Write-back D-cache, emulate VLSI
1719                          * abortion number three, not number one */
1720 #else
1721         /* For now let's play safe, optimize later */
1722         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1723                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1724         ccreg &= ~(TURBOSPARC_uS2);
1725                         /* Emulate VLSI abortion number three, not number one */
1726 #endif
1727
1728         switch (ccreg & 7) {
1729         case 0: /* No SE cache */
1730         case 7: /* Test mode */
1731                 break;
1732         default:
1733                 ccreg |= (TURBOSPARC_SCENABLE);
1734         }
1735         turbosparc_set_ccreg (ccreg);
1736
1737         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1738         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1739         srmmu_set_mmureg(mreg);
1740 }
1741
1742 static void __init init_turbosparc(void)
1743 {
1744         srmmu_name = "Fujitsu TurboSparc";
1745         srmmu_modtype = TurboSparc;
1746
1747         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1748         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1749         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1750         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1751
1752         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1753         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1754         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1755         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1756
1757         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1758
1759         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1760         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1761
1762         poke_srmmu = poke_turbosparc;
1763 }
1764
1765 static void __cpuinit poke_tsunami(void)
1766 {
1767         unsigned long mreg = srmmu_get_mmureg();
1768
1769         tsunami_flush_icache();
1770         tsunami_flush_dcache();
1771         mreg &= ~TSUNAMI_ITD;
1772         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1773         srmmu_set_mmureg(mreg);
1774 }
1775
1776 static void __init init_tsunami(void)
1777 {
1778         /*
1779          * Tsunami's pretty sane, Sun and TI actually got it
1780          * somewhat right this time.  Fujitsu should have
1781          * taken some lessons from them.
1782          */
1783
1784         srmmu_name = "TI Tsunami";
1785         srmmu_modtype = Tsunami;
1786
1787         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1788         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1789         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1790         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1791
1792
1793         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1794         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1795         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1796         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1797
1798         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1799         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1800         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1801
1802         poke_srmmu = poke_tsunami;
1803
1804         tsunami_setup_blockops();
1805 }
1806
1807 static void __cpuinit poke_viking(void)
1808 {
1809         unsigned long mreg = srmmu_get_mmureg();
1810         static int smp_catch;
1811
1812         if(viking_mxcc_present) {
1813                 unsigned long mxcc_control = mxcc_get_creg();
1814
1815                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1816                 mxcc_control &= ~(MXCC_CTL_RRC);
1817                 mxcc_set_creg(mxcc_control);
1818
1819                 /*
1820                  * We don't need memory parity checks.
1821                  * XXX This is a mess, have to dig out later. ecd.
1822                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1823                  */
1824
1825                 /* We do cache ptables on MXCC. */
1826                 mreg |= VIKING_TCENABLE;
1827         } else {
1828                 unsigned long bpreg;
1829
1830                 mreg &= ~(VIKING_TCENABLE);
1831                 if(smp_catch++) {
1832                         /* Must disable mixed-cmd mode here for other cpu's. */
1833                         bpreg = viking_get_bpreg();
1834                         bpreg &= ~(VIKING_ACTION_MIX);
1835                         viking_set_bpreg(bpreg);
1836
1837                         /* Just in case PROM does something funny. */
1838                         msi_set_sync();
1839                 }
1840         }
1841
1842         mreg |= VIKING_SPENABLE;
1843         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1844         mreg |= VIKING_SBENABLE;
1845         mreg &= ~(VIKING_ACENABLE);
1846         srmmu_set_mmureg(mreg);
1847 }
1848
1849 static void __init init_viking(void)
1850 {
1851         unsigned long mreg = srmmu_get_mmureg();
1852
1853         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1854         if(mreg & VIKING_MMODE) {
1855                 srmmu_name = "TI Viking";
1856                 viking_mxcc_present = 0;
1857                 msi_set_sync();
1858
1859                 /*
1860                  * We need this to make sure old viking takes no hits
1861                  * on it's cache for dma snoops to workaround the
1862                  * "load from non-cacheable memory" interrupt bug.
1863                  * This is only necessary because of the new way in
1864                  * which we use the IOMMU.
1865                  */
1866                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1867
1868                 flush_page_for_dma_global = 0;
1869         } else {
1870                 srmmu_name = "TI Viking/MXCC";
1871                 viking_mxcc_present = 1;
1872
1873                 srmmu_cache_pagetables = 1;
1874
1875                 /* MXCC vikings lack the DMA snooping bug. */
1876                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1877         }
1878
1879         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1880         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1881         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1882         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1883
1884 #ifdef CONFIG_SMP
1885         if (sparc_cpu_model == sun4d) {
1886                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1887                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1888                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1889                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1890         } else
1891 #endif
1892         {
1893                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1894                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1895                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1896                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1897         }
1898
1899         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1900         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1901
1902         poke_srmmu = poke_viking;
1903 }
1904
1905 #ifdef CONFIG_SPARC_LEON
1906
1907 void __init poke_leonsparc(void)
1908 {
1909 }
1910
1911 void __init init_leon(void)
1912 {
1913
1914         srmmu_name = "LEON";
1915
1916         BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
1917                         BTFIXUPCALL_NORM);
1918         BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
1919                         BTFIXUPCALL_NORM);
1920         BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
1921                         BTFIXUPCALL_NORM);
1922         BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
1923                         BTFIXUPCALL_NORM);
1924         BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
1925                         BTFIXUPCALL_NORM);
1926
1927         BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1928         BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1929         BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1930         BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1931
1932         BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
1933                         BTFIXUPCALL_NOP);
1934         BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
1935
1936         poke_srmmu = poke_leonsparc;
1937
1938         srmmu_cache_pagetables = 0;
1939
1940         leon_flush_during_switch = leon_flush_needed();
1941 }
1942 #endif
1943
1944 /* Probe for the srmmu chip version. */
1945 static void __init get_srmmu_type(void)
1946 {
1947         unsigned long mreg, psr;
1948         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1949
1950         srmmu_modtype = SRMMU_INVAL_MOD;
1951         hwbug_bitmask = 0;
1952
1953         mreg = srmmu_get_mmureg(); psr = get_psr();
1954         mod_typ = (mreg & 0xf0000000) >> 28;
1955         mod_rev = (mreg & 0x0f000000) >> 24;
1956         psr_typ = (psr >> 28) & 0xf;
1957         psr_vers = (psr >> 24) & 0xf;
1958
1959         /* First, check for sparc-leon. */
1960         if (sparc_cpu_model == sparc_leon) {
1961                 init_leon();
1962                 return;
1963         }
1964
1965         /* Second, check for HyperSparc or Cypress. */
1966         if(mod_typ == 1) {
1967                 switch(mod_rev) {
1968                 case 7:
1969                         /* UP or MP Hypersparc */
1970                         init_hypersparc();
1971                         break;
1972                 case 0:
1973                 case 2:
1974                         /* Uniprocessor Cypress */
1975                         init_cypress_604();
1976                         break;
1977                 case 10:
1978                 case 11:
1979                 case 12:
1980                         /* _REALLY OLD_ Cypress MP chips... */
1981                 case 13:
1982                 case 14:
1983                 case 15:
1984                         /* MP Cypress mmu/cache-controller */
1985                         init_cypress_605(mod_rev);
1986                         break;
1987                 default:
1988                         /* Some other Cypress revision, assume a 605. */
1989                         init_cypress_605(mod_rev);
1990                         break;
1991                 }
1992                 return;
1993         }
1994
1995         /*
1996          * Now Fujitsu TurboSparc. It might happen that it is
1997          * in Swift emulation mode, so we will check later...
1998          */
1999         if (psr_typ == 0 && psr_vers == 5) {
2000                 init_turbosparc();
2001                 return;
2002         }
2003
2004         /* Next check for Fujitsu Swift. */
2005         if(psr_typ == 0 && psr_vers == 4) {
2006                 phandle cpunode;
2007                 char node_str[128];
2008
2009                 /* Look if it is not a TurboSparc emulating Swift... */
2010                 cpunode = prom_getchild(prom_root_node);
2011                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2012                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2013                         if(!strcmp(node_str, "cpu")) {
2014                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2015                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2016                                         init_turbosparc();
2017                                         return;
2018                                 }
2019                                 break;
2020                         }
2021                 }
2022
2023                 init_swift();
2024                 return;
2025         }
2026
2027         /* Now the Viking family of srmmu. */
2028         if(psr_typ == 4 &&
2029            ((psr_vers == 0) ||
2030             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2031                 init_viking();
2032                 return;
2033         }
2034
2035         /* Finally the Tsunami. */
2036         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2037                 init_tsunami();
2038                 return;
2039         }
2040
2041         /* Oh well */
2042         srmmu_is_bad();
2043 }
2044
2045 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2046         tsetup_mmu_patchme, rtrap_mmu_patchme;
2047
2048 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2049         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2050
2051 #ifdef CONFIG_SMP
2052 /* Local cross-calls. */
2053 static void smp_flush_page_for_dma(unsigned long page)
2054 {
2055         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2056         local_flush_page_for_dma(page);
2057 }
2058
2059 #endif
2060
2061 /* Load up routines and constants for sun4m and sun4d mmu */
2062 void __init load_mmu(void)
2063 {
2064         extern void ld_mmu_iommu(void);
2065         extern void ld_mmu_iounit(void);
2066         extern void ___xchg32_sun4md(void);
2067
2068         /* Functions */
2069 #ifndef CONFIG_SMP
2070         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2071 #endif
2072
2073         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2074
2075         BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
2076
2077         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2078
2079         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2080         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2081         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2082         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2083         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2084         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2085
2086         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2087         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2088         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2089
2090         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2091         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2092         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2093         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2094         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2095         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2096         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2097         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2098
2099         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2100         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2101         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2102         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2103         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2104         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2105         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2106         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2107         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2108         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2109         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2110         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2111
2112         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2113         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2114
2115         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2116         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2117         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2118
2119         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2120
2121         get_srmmu_type();
2122
2123 #ifdef CONFIG_SMP
2124         /* El switcheroo... */
2125
2126         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2127         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2128         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2129         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2130         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2131         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2132         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2133         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2134         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2135         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2136         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2137
2138         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2139         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2140         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2141         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2142         if (sparc_cpu_model != sun4d &&
2143             sparc_cpu_model != sparc_leon) {
2144                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2145                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2146                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2147                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2148         }
2149         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2150         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2151         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2152
2153         if (poke_srmmu == poke_viking) {
2154                 /* Avoid unnecessary cross calls. */
2155                 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2156                 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2157                 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2158                 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2159                 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2160                 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2161                 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2162         }
2163 #endif
2164
2165         if (sparc_cpu_model == sun4d)
2166                 ld_mmu_iounit();
2167         else
2168                 ld_mmu_iommu();
2169 #ifdef CONFIG_SMP
2170         if (sparc_cpu_model == sun4d)
2171                 sun4d_init_smp();
2172         else if (sparc_cpu_model == sparc_leon)
2173                 leon_init_smp();
2174         else
2175                 sun4m_init_smp();
2176 #endif
2177         btfixup();
2178 }