2 * srmmu.c: SRMMU specific routines for memory management.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
11 #include <linux/seq_file.h>
12 #include <linux/spinlock.h>
13 #include <linux/bootmem.h>
14 #include <linux/pagemap.h>
15 #include <linux/vmalloc.h>
16 #include <linux/kdebug.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/log2.h>
20 #include <linux/gfp.h>
24 #include <asm/mmu_context.h>
25 #include <asm/cacheflush.h>
26 #include <asm/tlbflush.h>
27 #include <asm/io-unit.h>
28 #include <asm/pgalloc.h>
29 #include <asm/pgtable.h>
30 #include <asm/bitext.h>
31 #include <asm/vaddrs.h>
32 #include <asm/cache.h>
33 #include <asm/traps.h>
34 #include <asm/oplib.h>
42 /* Now the cpu specific definitions. */
43 #include <asm/turbosparc.h>
44 #include <asm/tsunami.h>
45 #include <asm/viking.h>
46 #include <asm/swift.h>
53 enum mbus_module srmmu_modtype;
54 static unsigned int hwbug_bitmask;
58 extern struct resource sparc_iomap;
60 extern unsigned long last_valid_pfn;
62 static pgd_t *srmmu_swapper_pg_dir;
64 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
67 const struct sparc32_cachetlb_ops *local_ops;
69 #define FLUSH_BEGIN(mm)
72 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
76 int flush_page_for_dma_global = 1;
80 ctxd_t *srmmu_ctx_table_phys;
81 static ctxd_t *srmmu_context_table;
83 int viking_mxcc_present;
84 static DEFINE_SPINLOCK(srmmu_context_spinlock);
86 static int is_hypersparc;
88 static int srmmu_cache_pagetables;
90 /* these will be initialized in srmmu_nocache_calcsize() */
91 static unsigned long srmmu_nocache_size;
92 static unsigned long srmmu_nocache_end;
94 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
95 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
97 /* The context table is a nocache user with the biggest alignment needs. */
98 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
100 void *srmmu_nocache_pool;
101 void *srmmu_nocache_bitmap;
102 static struct bit_map srmmu_nocache_map;
104 static inline int srmmu_pmd_none(pmd_t pmd)
105 { return !(pmd_val(pmd) & 0xFFFFFFF); }
107 /* XXX should we hyper_flush_whole_icache here - Anton */
108 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
109 { set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
111 void pmd_set(pmd_t *pmdp, pte_t *ptep)
113 unsigned long ptp; /* Physical address, shifted right by 4 */
116 ptp = __nocache_pa((unsigned long) ptep) >> 4;
117 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
118 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
119 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
123 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
125 unsigned long ptp; /* Physical address, shifted right by 4 */
128 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */
129 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
130 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
131 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
135 /* Find an entry in the third-level page table.. */
136 pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address)
140 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
141 return (pte_t *) pte +
142 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
146 * size: bytes to allocate in the nocache area.
147 * align: bytes, number to align at.
148 * Returns the virtual address of the allocated area.
150 static void *__srmmu_get_nocache(int size, int align)
155 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
156 printk(KERN_ERR "Size 0x%x too small for nocache request\n",
158 size = SRMMU_NOCACHE_BITMAP_SHIFT;
160 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT - 1)) {
161 printk(KERN_ERR "Size 0x%x unaligned int nocache request\n",
163 size += SRMMU_NOCACHE_BITMAP_SHIFT - 1;
165 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
167 offset = bit_map_string_get(&srmmu_nocache_map,
168 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
169 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
171 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
172 size, (int) srmmu_nocache_size,
173 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
177 addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
181 void *srmmu_get_nocache(int size, int align)
185 tmp = __srmmu_get_nocache(size, align);
188 memset(tmp, 0, size);
193 void srmmu_free_nocache(void *addr, int size)
198 vaddr = (unsigned long)addr;
199 if (vaddr < SRMMU_NOCACHE_VADDR) {
200 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
201 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
204 if (vaddr + size > srmmu_nocache_end) {
205 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
206 vaddr, srmmu_nocache_end);
209 if (!is_power_of_2(size)) {
210 printk("Size 0x%x is not a power of 2\n", size);
213 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
214 printk("Size 0x%x is too small\n", size);
217 if (vaddr & (size - 1)) {
218 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
222 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
223 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
225 bit_map_clear(&srmmu_nocache_map, offset, size);
228 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
231 /* Return how much physical memory we have. */
232 static unsigned long __init probe_memory(void)
234 unsigned long total = 0;
237 for (i = 0; sp_banks[i].num_bytes; i++)
238 total += sp_banks[i].num_bytes;
244 * Reserve nocache dynamically proportionally to the amount of
245 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
247 static void __init srmmu_nocache_calcsize(void)
249 unsigned long sysmemavail = probe_memory() / 1024;
250 int srmmu_nocache_npages;
252 srmmu_nocache_npages =
253 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
255 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
256 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
257 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
258 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
260 /* anything above 1280 blows up */
261 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
262 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
264 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
265 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
268 static void __init srmmu_nocache_init(void)
270 unsigned int bitmap_bits;
274 unsigned long paddr, vaddr;
275 unsigned long pteval;
277 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
279 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
280 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
281 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
283 srmmu_nocache_bitmap =
284 __alloc_bootmem(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
285 SMP_CACHE_BYTES, 0UL);
286 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
288 srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
289 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
290 init_mm.pgd = srmmu_swapper_pg_dir;
292 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
294 paddr = __pa((unsigned long)srmmu_nocache_pool);
295 vaddr = SRMMU_NOCACHE_VADDR;
297 while (vaddr < srmmu_nocache_end) {
298 pgd = pgd_offset_k(vaddr);
299 pmd = pmd_offset(__nocache_fix(pgd), vaddr);
300 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
302 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
304 if (srmmu_cache_pagetables)
305 pteval |= SRMMU_CACHE;
307 set_pte(__nocache_fix(pte), __pte(pteval));
317 pgd_t *get_pgd_fast(void)
321 pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
323 pgd_t *init = pgd_offset_k(0);
324 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
325 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
326 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
333 * Hardware needs alignment to 256 only, but we align to whole page size
334 * to reduce fragmentation problems due to the buddy principle.
335 * XXX Provide actual fragmentation statistics in /proc.
337 * Alignments up to the page size are the same for physical and virtual
338 * addresses of the nocache area.
340 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
345 if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
347 page = pfn_to_page(__nocache_pa(pte) >> PAGE_SHIFT);
348 if (!pgtable_page_ctor(page)) {
355 void pte_free(struct mm_struct *mm, pgtable_t pte)
359 pgtable_page_dtor(pte);
360 p = (unsigned long)page_address(pte); /* Cached address (for test) */
363 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */
365 /* free non cached virtual address*/
366 srmmu_free_nocache(__nocache_va(p), PTE_SIZE);
369 /* context handling - a dynamically sized pool is used */
370 #define NO_CONTEXT -1
373 struct ctx_list *next;
374 struct ctx_list *prev;
375 unsigned int ctx_number;
376 struct mm_struct *ctx_mm;
379 static struct ctx_list *ctx_list_pool;
380 static struct ctx_list ctx_free;
381 static struct ctx_list ctx_used;
383 /* At boot time we determine the number of contexts */
384 static int num_contexts;
386 static inline void remove_from_ctx_list(struct ctx_list *entry)
388 entry->next->prev = entry->prev;
389 entry->prev->next = entry->next;
392 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
395 (entry->prev = head->prev)->next = entry;
398 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
399 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
402 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
404 struct ctx_list *ctxp;
406 ctxp = ctx_free.next;
407 if (ctxp != &ctx_free) {
408 remove_from_ctx_list(ctxp);
409 add_to_used_ctxlist(ctxp);
410 mm->context = ctxp->ctx_number;
414 ctxp = ctx_used.next;
415 if (ctxp->ctx_mm == old_mm)
417 if (ctxp == &ctx_used)
418 panic("out of mmu contexts");
419 flush_cache_mm(ctxp->ctx_mm);
420 flush_tlb_mm(ctxp->ctx_mm);
421 remove_from_ctx_list(ctxp);
422 add_to_used_ctxlist(ctxp);
423 ctxp->ctx_mm->context = NO_CONTEXT;
425 mm->context = ctxp->ctx_number;
428 static inline void free_context(int context)
430 struct ctx_list *ctx_old;
432 ctx_old = ctx_list_pool + context;
433 remove_from_ctx_list(ctx_old);
434 add_to_free_ctxlist(ctx_old);
437 static void __init sparc_context_init(int numctx)
442 size = numctx * sizeof(struct ctx_list);
443 ctx_list_pool = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
445 for (ctx = 0; ctx < numctx; ctx++) {
446 struct ctx_list *clist;
448 clist = (ctx_list_pool + ctx);
449 clist->ctx_number = ctx;
450 clist->ctx_mm = NULL;
452 ctx_free.next = ctx_free.prev = &ctx_free;
453 ctx_used.next = ctx_used.prev = &ctx_used;
454 for (ctx = 0; ctx < numctx; ctx++)
455 add_to_free_ctxlist(ctx_list_pool + ctx);
458 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
459 struct task_struct *tsk)
461 if (mm->context == NO_CONTEXT) {
462 spin_lock(&srmmu_context_spinlock);
463 alloc_context(old_mm, mm);
464 spin_unlock(&srmmu_context_spinlock);
465 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
468 if (sparc_cpu_model == sparc_leon)
472 hyper_flush_whole_icache();
474 srmmu_set_context(mm->context);
477 /* Low level IO area allocation on the SRMMU. */
478 static inline void srmmu_mapioaddr(unsigned long physaddr,
479 unsigned long virt_addr, int bus_type)
486 physaddr &= PAGE_MASK;
487 pgdp = pgd_offset_k(virt_addr);
488 pmdp = pmd_offset(pgdp, virt_addr);
489 ptep = pte_offset_kernel(pmdp, virt_addr);
490 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
492 /* I need to test whether this is consistent over all
493 * sun4m's. The bus_type represents the upper 4 bits of
494 * 36-bit physical address on the I/O space lines...
496 tmp |= (bus_type << 28);
498 __flush_page_to_ram(virt_addr);
499 set_pte(ptep, __pte(tmp));
502 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
503 unsigned long xva, unsigned int len)
507 srmmu_mapioaddr(xpa, xva, bus);
514 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
520 pgdp = pgd_offset_k(virt_addr);
521 pmdp = pmd_offset(pgdp, virt_addr);
522 ptep = pte_offset_kernel(pmdp, virt_addr);
524 /* No need to flush uncacheable page. */
528 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
532 srmmu_unmapioaddr(virt_addr);
533 virt_addr += PAGE_SIZE;
539 extern void tsunami_flush_cache_all(void);
540 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
541 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
542 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
543 extern void tsunami_flush_page_to_ram(unsigned long page);
544 extern void tsunami_flush_page_for_dma(unsigned long page);
545 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
546 extern void tsunami_flush_tlb_all(void);
547 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
548 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
549 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
550 extern void tsunami_setup_blockops(void);
553 extern void swift_flush_cache_all(void);
554 extern void swift_flush_cache_mm(struct mm_struct *mm);
555 extern void swift_flush_cache_range(struct vm_area_struct *vma,
556 unsigned long start, unsigned long end);
557 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
558 extern void swift_flush_page_to_ram(unsigned long page);
559 extern void swift_flush_page_for_dma(unsigned long page);
560 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
561 extern void swift_flush_tlb_all(void);
562 extern void swift_flush_tlb_mm(struct mm_struct *mm);
563 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
564 unsigned long start, unsigned long end);
565 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
567 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
568 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
573 if ((ctx1 = vma->vm_mm->context) != -1) {
574 cctx = srmmu_get_context();
575 /* Is context # ever different from current context? P3 */
577 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
578 srmmu_set_context(ctx1);
579 swift_flush_page(page);
580 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
581 "r" (page), "i" (ASI_M_FLUSH_PROBE));
582 srmmu_set_context(cctx);
584 /* Rm. prot. bits from virt. c. */
585 /* swift_flush_cache_all(); */
586 /* swift_flush_cache_page(vma, page); */
587 swift_flush_page(page);
589 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
590 "r" (page), "i" (ASI_M_FLUSH_PROBE));
591 /* same as above: srmmu_flush_tlb_page() */
598 * The following are all MBUS based SRMMU modules, and therefore could
599 * be found in a multiprocessor configuration. On the whole, these
600 * chips seems to be much more touchy about DVMA and page tables
601 * with respect to cache coherency.
605 extern void viking_flush_cache_all(void);
606 extern void viking_flush_cache_mm(struct mm_struct *mm);
607 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
609 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
610 extern void viking_flush_page_to_ram(unsigned long page);
611 extern void viking_flush_page_for_dma(unsigned long page);
612 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
613 extern void viking_flush_page(unsigned long page);
614 extern void viking_mxcc_flush_page(unsigned long page);
615 extern void viking_flush_tlb_all(void);
616 extern void viking_flush_tlb_mm(struct mm_struct *mm);
617 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
619 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
621 extern void sun4dsmp_flush_tlb_all(void);
622 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
623 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
625 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
629 extern void hypersparc_flush_cache_all(void);
630 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
631 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
632 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
633 extern void hypersparc_flush_page_to_ram(unsigned long page);
634 extern void hypersparc_flush_page_for_dma(unsigned long page);
635 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
636 extern void hypersparc_flush_tlb_all(void);
637 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
638 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
639 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
640 extern void hypersparc_setup_blockops(void);
643 * NOTE: All of this startup code assumes the low 16mb (approx.) of
644 * kernel mappings are done with one single contiguous chunk of
645 * ram. On small ram machines (classics mainly) we only get
646 * around 8mb mapped for us.
649 static void __init early_pgtable_allocfail(char *type)
651 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
655 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
662 while (start < end) {
663 pgdp = pgd_offset_k(start);
664 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
665 pmdp = __srmmu_get_nocache(
666 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
668 early_pgtable_allocfail("pmd");
669 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
670 pgd_set(__nocache_fix(pgdp), pmdp);
672 pmdp = pmd_offset(__nocache_fix(pgdp), start);
673 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
674 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
676 early_pgtable_allocfail("pte");
677 memset(__nocache_fix(ptep), 0, PTE_SIZE);
678 pmd_set(__nocache_fix(pmdp), ptep);
680 if (start > (0xffffffffUL - PMD_SIZE))
682 start = (start + PMD_SIZE) & PMD_MASK;
686 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
693 while (start < end) {
694 pgdp = pgd_offset_k(start);
695 if (pgd_none(*pgdp)) {
696 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
698 early_pgtable_allocfail("pmd");
699 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
702 pmdp = pmd_offset(pgdp, start);
703 if (srmmu_pmd_none(*pmdp)) {
704 ptep = __srmmu_get_nocache(PTE_SIZE,
707 early_pgtable_allocfail("pte");
708 memset(ptep, 0, PTE_SIZE);
711 if (start > (0xffffffffUL - PMD_SIZE))
713 start = (start + PMD_SIZE) & PMD_MASK;
717 /* These flush types are not available on all chips... */
718 static inline unsigned long srmmu_probe(unsigned long vaddr)
720 unsigned long retval;
722 if (sparc_cpu_model != sparc_leon) {
725 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
727 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
729 retval = leon_swprobe(vaddr, 0);
735 * This is much cleaner than poking around physical address space
736 * looking at the prom's page table directly which is what most
737 * other OS's do. Yuck... this is much better.
739 static void __init srmmu_inherit_prom_mappings(unsigned long start,
742 unsigned long probed;
747 int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
749 while (start <= end) {
751 break; /* probably wrap around */
752 if (start == 0xfef00000)
753 start = KADB_DEBUGGER_BEGVM;
754 probed = srmmu_probe(start);
756 /* continue probing until we find an entry */
761 /* A red snapper, see what it really is. */
763 addr = start - PAGE_SIZE;
765 if (!(start & ~(SRMMU_REAL_PMD_MASK))) {
766 if (srmmu_probe(addr + SRMMU_REAL_PMD_SIZE) == probed)
770 if (!(start & ~(SRMMU_PGDIR_MASK))) {
771 if (srmmu_probe(addr + SRMMU_PGDIR_SIZE) == probed)
775 pgdp = pgd_offset_k(start);
777 *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed);
778 start += SRMMU_PGDIR_SIZE;
781 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
782 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
783 SRMMU_PMD_TABLE_SIZE);
785 early_pgtable_allocfail("pmd");
786 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
787 pgd_set(__nocache_fix(pgdp), pmdp);
789 pmdp = pmd_offset(__nocache_fix(pgdp), start);
790 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
791 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
793 early_pgtable_allocfail("pte");
794 memset(__nocache_fix(ptep), 0, PTE_SIZE);
795 pmd_set(__nocache_fix(pmdp), ptep);
798 /* We bend the rule where all 16 PTPs in a pmd_t point
799 * inside the same PTE page, and we leak a perfectly
800 * good hardware PTE piece. Alternatives seem worse.
802 unsigned int x; /* Index of HW PMD in soft cluster */
804 x = (start >> PMD_SHIFT) & 15;
805 val = &pmdp->pmdv[x];
806 *(unsigned long *)__nocache_fix(val) = probed;
807 start += SRMMU_REAL_PMD_SIZE;
810 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
811 *(pte_t *)__nocache_fix(ptep) = __pte(probed);
816 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
818 /* Create a third-level SRMMU 16MB page mapping. */
819 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
821 pgd_t *pgdp = pgd_offset_k(vaddr);
822 unsigned long big_pte;
824 big_pte = KERNEL_PTE(phys_base >> 4);
825 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
828 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
829 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
831 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
832 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
833 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
834 /* Map "low" memory only */
835 const unsigned long min_vaddr = PAGE_OFFSET;
836 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
838 if (vstart < min_vaddr || vstart >= max_vaddr)
841 if (vend > max_vaddr || vend < min_vaddr)
844 while (vstart < vend) {
845 do_large_mapping(vstart, pstart);
846 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
851 static void __init map_kernel(void)
856 do_large_mapping(PAGE_OFFSET, phys_base);
859 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
860 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
864 void (*poke_srmmu)(void) = NULL;
866 extern unsigned long bootmem_init(unsigned long *pages_avail);
868 void __init srmmu_paging_init(void)
876 unsigned long pages_avail;
878 init_mm.context = (unsigned long) NO_CONTEXT;
879 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
881 if (sparc_cpu_model == sun4d)
882 num_contexts = 65536; /* We know it is Viking */
884 /* Find the number of contexts on the srmmu. */
885 cpunode = prom_getchild(prom_root_node);
887 while (cpunode != 0) {
888 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
889 if (!strcmp(node_str, "cpu")) {
890 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
893 cpunode = prom_getsibling(cpunode);
898 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
903 last_valid_pfn = bootmem_init(&pages_avail);
905 srmmu_nocache_calcsize();
906 srmmu_nocache_init();
907 srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
910 /* ctx table has to be physically aligned to its size */
911 srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
912 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
914 for (i = 0; i < num_contexts; i++)
915 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
918 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
920 /* Stop from hanging here... */
921 local_ops->tlb_all();
927 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
928 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
930 srmmu_allocate_ptable_skeleton(
931 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
932 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
934 pgd = pgd_offset_k(PKMAP_BASE);
935 pmd = pmd_offset(pgd, PKMAP_BASE);
936 pte = pte_offset_kernel(pmd, PKMAP_BASE);
937 pkmap_page_table = pte;
942 sparc_context_init(num_contexts);
947 unsigned long zones_size[MAX_NR_ZONES];
948 unsigned long zholes_size[MAX_NR_ZONES];
949 unsigned long npages;
952 for (znum = 0; znum < MAX_NR_ZONES; znum++)
953 zones_size[znum] = zholes_size[znum] = 0;
955 npages = max_low_pfn - pfn_base;
957 zones_size[ZONE_DMA] = npages;
958 zholes_size[ZONE_DMA] = npages - pages_avail;
960 npages = highend_pfn - max_low_pfn;
961 zones_size[ZONE_HIGHMEM] = npages;
962 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
964 free_area_init_node(0, zones_size, pfn_base, zholes_size);
968 void mmu_info(struct seq_file *m)
973 "nocache total\t: %ld\n"
974 "nocache used\t: %d\n",
978 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
981 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
983 mm->context = NO_CONTEXT;
987 void destroy_context(struct mm_struct *mm)
990 if (mm->context != NO_CONTEXT) {
992 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
994 spin_lock(&srmmu_context_spinlock);
995 free_context(mm->context);
996 spin_unlock(&srmmu_context_spinlock);
997 mm->context = NO_CONTEXT;
1001 /* Init various srmmu chip types. */
1002 static void __init srmmu_is_bad(void)
1004 prom_printf("Could not determine SRMMU chip type.\n");
1008 static void __init init_vac_layout(void)
1015 unsigned long max_size = 0;
1016 unsigned long min_line_size = 0x10000000;
1019 nd = prom_getchild(prom_root_node);
1020 while ((nd = prom_getsibling(nd)) != 0) {
1021 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1022 if (!strcmp(node_str, "cpu")) {
1023 vac_line_size = prom_getint(nd, "cache-line-size");
1024 if (vac_line_size == -1) {
1025 prom_printf("can't determine cache-line-size, halting.\n");
1028 cache_lines = prom_getint(nd, "cache-nlines");
1029 if (cache_lines == -1) {
1030 prom_printf("can't determine cache-nlines, halting.\n");
1034 vac_cache_size = cache_lines * vac_line_size;
1036 if (vac_cache_size > max_size)
1037 max_size = vac_cache_size;
1038 if (vac_line_size < min_line_size)
1039 min_line_size = vac_line_size;
1040 //FIXME: cpus not contiguous!!
1042 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1050 prom_printf("No CPU nodes found, halting.\n");
1054 vac_cache_size = max_size;
1055 vac_line_size = min_line_size;
1057 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1058 (int)vac_cache_size, (int)vac_line_size);
1061 static void poke_hypersparc(void)
1063 volatile unsigned long clear;
1064 unsigned long mreg = srmmu_get_mmureg();
1066 hyper_flush_unconditional_combined();
1068 mreg &= ~(HYPERSPARC_CWENABLE);
1069 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1070 mreg |= (HYPERSPARC_CMODE);
1072 srmmu_set_mmureg(mreg);
1074 #if 0 /* XXX I think this is bad news... -DaveM */
1075 hyper_clear_all_tags();
1078 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1079 hyper_flush_whole_icache();
1080 clear = srmmu_get_faddr();
1081 clear = srmmu_get_fstatus();
1084 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1085 .cache_all = hypersparc_flush_cache_all,
1086 .cache_mm = hypersparc_flush_cache_mm,
1087 .cache_page = hypersparc_flush_cache_page,
1088 .cache_range = hypersparc_flush_cache_range,
1089 .tlb_all = hypersparc_flush_tlb_all,
1090 .tlb_mm = hypersparc_flush_tlb_mm,
1091 .tlb_page = hypersparc_flush_tlb_page,
1092 .tlb_range = hypersparc_flush_tlb_range,
1093 .page_to_ram = hypersparc_flush_page_to_ram,
1094 .sig_insns = hypersparc_flush_sig_insns,
1095 .page_for_dma = hypersparc_flush_page_for_dma,
1098 static void __init init_hypersparc(void)
1100 srmmu_name = "ROSS HyperSparc";
1101 srmmu_modtype = HyperSparc;
1106 sparc32_cachetlb_ops = &hypersparc_ops;
1108 poke_srmmu = poke_hypersparc;
1110 hypersparc_setup_blockops();
1113 static void poke_swift(void)
1117 /* Clear any crap from the cache or else... */
1118 swift_flush_cache_all();
1120 /* Enable I & D caches */
1121 mreg = srmmu_get_mmureg();
1122 mreg |= (SWIFT_IE | SWIFT_DE);
1124 * The Swift branch folding logic is completely broken. At
1125 * trap time, if things are just right, if can mistakenly
1126 * think that a trap is coming from kernel mode when in fact
1127 * it is coming from user mode (it mis-executes the branch in
1128 * the trap code). So you see things like crashme completely
1129 * hosing your machine which is completely unacceptable. Turn
1130 * this shit off... nice job Fujitsu.
1132 mreg &= ~(SWIFT_BF);
1133 srmmu_set_mmureg(mreg);
1136 static const struct sparc32_cachetlb_ops swift_ops = {
1137 .cache_all = swift_flush_cache_all,
1138 .cache_mm = swift_flush_cache_mm,
1139 .cache_page = swift_flush_cache_page,
1140 .cache_range = swift_flush_cache_range,
1141 .tlb_all = swift_flush_tlb_all,
1142 .tlb_mm = swift_flush_tlb_mm,
1143 .tlb_page = swift_flush_tlb_page,
1144 .tlb_range = swift_flush_tlb_range,
1145 .page_to_ram = swift_flush_page_to_ram,
1146 .sig_insns = swift_flush_sig_insns,
1147 .page_for_dma = swift_flush_page_for_dma,
1150 #define SWIFT_MASKID_ADDR 0x10003018
1151 static void __init init_swift(void)
1153 unsigned long swift_rev;
1155 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1156 "srl %0, 0x18, %0\n\t" :
1158 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1159 srmmu_name = "Fujitsu Swift";
1160 switch (swift_rev) {
1165 srmmu_modtype = Swift_lots_o_bugs;
1166 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1168 * Gee george, I wonder why Sun is so hush hush about
1169 * this hardware bug... really braindamage stuff going
1170 * on here. However I think we can find a way to avoid
1171 * all of the workaround overhead under Linux. Basically,
1172 * any page fault can cause kernel pages to become user
1173 * accessible (the mmu gets confused and clears some of
1174 * the ACC bits in kernel ptes). Aha, sounds pretty
1175 * horrible eh? But wait, after extensive testing it appears
1176 * that if you use pgd_t level large kernel pte's (like the
1177 * 4MB pages on the Pentium) the bug does not get tripped
1178 * at all. This avoids almost all of the major overhead.
1179 * Welcome to a world where your vendor tells you to,
1180 * "apply this kernel patch" instead of "sorry for the
1181 * broken hardware, send it back and we'll give you
1182 * properly functioning parts"
1187 srmmu_modtype = Swift_bad_c;
1188 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1190 * You see Sun allude to this hardware bug but never
1191 * admit things directly, they'll say things like,
1192 * "the Swift chip cache problems" or similar.
1196 srmmu_modtype = Swift_ok;
1200 sparc32_cachetlb_ops = &swift_ops;
1201 flush_page_for_dma_global = 0;
1204 * Are you now convinced that the Swift is one of the
1205 * biggest VLSI abortions of all time? Bravo Fujitsu!
1206 * Fujitsu, the !#?!%$'d up processor people. I bet if
1207 * you examined the microcode of the Swift you'd find
1208 * XXX's all over the place.
1210 poke_srmmu = poke_swift;
1213 static void turbosparc_flush_cache_all(void)
1215 flush_user_windows();
1216 turbosparc_idflash_clear();
1219 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1222 flush_user_windows();
1223 turbosparc_idflash_clear();
1227 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1229 FLUSH_BEGIN(vma->vm_mm)
1230 flush_user_windows();
1231 turbosparc_idflash_clear();
1235 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1237 FLUSH_BEGIN(vma->vm_mm)
1238 flush_user_windows();
1239 if (vma->vm_flags & VM_EXEC)
1240 turbosparc_flush_icache();
1241 turbosparc_flush_dcache();
1245 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1246 static void turbosparc_flush_page_to_ram(unsigned long page)
1248 #ifdef TURBOSPARC_WRITEBACK
1249 volatile unsigned long clear;
1251 if (srmmu_probe(page))
1252 turbosparc_flush_page_cache(page);
1253 clear = srmmu_get_fstatus();
1257 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1261 static void turbosparc_flush_page_for_dma(unsigned long page)
1263 turbosparc_flush_dcache();
1266 static void turbosparc_flush_tlb_all(void)
1268 srmmu_flush_whole_tlb();
1271 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1274 srmmu_flush_whole_tlb();
1278 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1280 FLUSH_BEGIN(vma->vm_mm)
1281 srmmu_flush_whole_tlb();
1285 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1287 FLUSH_BEGIN(vma->vm_mm)
1288 srmmu_flush_whole_tlb();
1293 static void poke_turbosparc(void)
1295 unsigned long mreg = srmmu_get_mmureg();
1296 unsigned long ccreg;
1298 /* Clear any crap from the cache or else... */
1299 turbosparc_flush_cache_all();
1300 /* Temporarily disable I & D caches */
1301 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1302 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1303 srmmu_set_mmureg(mreg);
1305 ccreg = turbosparc_get_ccreg();
1307 #ifdef TURBOSPARC_WRITEBACK
1308 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1309 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1310 /* Write-back D-cache, emulate VLSI
1311 * abortion number three, not number one */
1313 /* For now let's play safe, optimize later */
1314 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1315 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1316 ccreg &= ~(TURBOSPARC_uS2);
1317 /* Emulate VLSI abortion number three, not number one */
1320 switch (ccreg & 7) {
1321 case 0: /* No SE cache */
1322 case 7: /* Test mode */
1325 ccreg |= (TURBOSPARC_SCENABLE);
1327 turbosparc_set_ccreg(ccreg);
1329 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1330 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1331 srmmu_set_mmureg(mreg);
1334 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1335 .cache_all = turbosparc_flush_cache_all,
1336 .cache_mm = turbosparc_flush_cache_mm,
1337 .cache_page = turbosparc_flush_cache_page,
1338 .cache_range = turbosparc_flush_cache_range,
1339 .tlb_all = turbosparc_flush_tlb_all,
1340 .tlb_mm = turbosparc_flush_tlb_mm,
1341 .tlb_page = turbosparc_flush_tlb_page,
1342 .tlb_range = turbosparc_flush_tlb_range,
1343 .page_to_ram = turbosparc_flush_page_to_ram,
1344 .sig_insns = turbosparc_flush_sig_insns,
1345 .page_for_dma = turbosparc_flush_page_for_dma,
1348 static void __init init_turbosparc(void)
1350 srmmu_name = "Fujitsu TurboSparc";
1351 srmmu_modtype = TurboSparc;
1352 sparc32_cachetlb_ops = &turbosparc_ops;
1353 poke_srmmu = poke_turbosparc;
1356 static void poke_tsunami(void)
1358 unsigned long mreg = srmmu_get_mmureg();
1360 tsunami_flush_icache();
1361 tsunami_flush_dcache();
1362 mreg &= ~TSUNAMI_ITD;
1363 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1364 srmmu_set_mmureg(mreg);
1367 static const struct sparc32_cachetlb_ops tsunami_ops = {
1368 .cache_all = tsunami_flush_cache_all,
1369 .cache_mm = tsunami_flush_cache_mm,
1370 .cache_page = tsunami_flush_cache_page,
1371 .cache_range = tsunami_flush_cache_range,
1372 .tlb_all = tsunami_flush_tlb_all,
1373 .tlb_mm = tsunami_flush_tlb_mm,
1374 .tlb_page = tsunami_flush_tlb_page,
1375 .tlb_range = tsunami_flush_tlb_range,
1376 .page_to_ram = tsunami_flush_page_to_ram,
1377 .sig_insns = tsunami_flush_sig_insns,
1378 .page_for_dma = tsunami_flush_page_for_dma,
1381 static void __init init_tsunami(void)
1384 * Tsunami's pretty sane, Sun and TI actually got it
1385 * somewhat right this time. Fujitsu should have
1386 * taken some lessons from them.
1389 srmmu_name = "TI Tsunami";
1390 srmmu_modtype = Tsunami;
1391 sparc32_cachetlb_ops = &tsunami_ops;
1392 poke_srmmu = poke_tsunami;
1394 tsunami_setup_blockops();
1397 static void poke_viking(void)
1399 unsigned long mreg = srmmu_get_mmureg();
1400 static int smp_catch;
1402 if (viking_mxcc_present) {
1403 unsigned long mxcc_control = mxcc_get_creg();
1405 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1406 mxcc_control &= ~(MXCC_CTL_RRC);
1407 mxcc_set_creg(mxcc_control);
1410 * We don't need memory parity checks.
1411 * XXX This is a mess, have to dig out later. ecd.
1412 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1415 /* We do cache ptables on MXCC. */
1416 mreg |= VIKING_TCENABLE;
1418 unsigned long bpreg;
1420 mreg &= ~(VIKING_TCENABLE);
1422 /* Must disable mixed-cmd mode here for other cpu's. */
1423 bpreg = viking_get_bpreg();
1424 bpreg &= ~(VIKING_ACTION_MIX);
1425 viking_set_bpreg(bpreg);
1427 /* Just in case PROM does something funny. */
1432 mreg |= VIKING_SPENABLE;
1433 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1434 mreg |= VIKING_SBENABLE;
1435 mreg &= ~(VIKING_ACENABLE);
1436 srmmu_set_mmureg(mreg);
1439 static struct sparc32_cachetlb_ops viking_ops = {
1440 .cache_all = viking_flush_cache_all,
1441 .cache_mm = viking_flush_cache_mm,
1442 .cache_page = viking_flush_cache_page,
1443 .cache_range = viking_flush_cache_range,
1444 .tlb_all = viking_flush_tlb_all,
1445 .tlb_mm = viking_flush_tlb_mm,
1446 .tlb_page = viking_flush_tlb_page,
1447 .tlb_range = viking_flush_tlb_range,
1448 .page_to_ram = viking_flush_page_to_ram,
1449 .sig_insns = viking_flush_sig_insns,
1450 .page_for_dma = viking_flush_page_for_dma,
1454 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1455 * perform the local TLB flush and all the other cpus will see it.
1456 * But, unfortunately, there is a bug in the sun4d XBUS backplane
1457 * that requires that we add some synchronization to these flushes.
1459 * The bug is that the fifo which keeps track of all the pending TLB
1460 * broadcasts in the system is an entry or two too small, so if we
1461 * have too many going at once we'll overflow that fifo and lose a TLB
1462 * flush resulting in corruption.
1464 * Our workaround is to take a global spinlock around the TLB flushes,
1465 * which guarentees we won't ever have too many pending. It's a big
1466 * hammer, but a semaphore like system to make sure we only have N TLB
1467 * flushes going at once will require SMP locking anyways so there's
1468 * no real value in trying any harder than this.
1470 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = {
1471 .cache_all = viking_flush_cache_all,
1472 .cache_mm = viking_flush_cache_mm,
1473 .cache_page = viking_flush_cache_page,
1474 .cache_range = viking_flush_cache_range,
1475 .tlb_all = sun4dsmp_flush_tlb_all,
1476 .tlb_mm = sun4dsmp_flush_tlb_mm,
1477 .tlb_page = sun4dsmp_flush_tlb_page,
1478 .tlb_range = sun4dsmp_flush_tlb_range,
1479 .page_to_ram = viking_flush_page_to_ram,
1480 .sig_insns = viking_flush_sig_insns,
1481 .page_for_dma = viking_flush_page_for_dma,
1485 static void __init init_viking(void)
1487 unsigned long mreg = srmmu_get_mmureg();
1489 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1490 if (mreg & VIKING_MMODE) {
1491 srmmu_name = "TI Viking";
1492 viking_mxcc_present = 0;
1496 * We need this to make sure old viking takes no hits
1497 * on it's cache for dma snoops to workaround the
1498 * "load from non-cacheable memory" interrupt bug.
1499 * This is only necessary because of the new way in
1500 * which we use the IOMMU.
1502 viking_ops.page_for_dma = viking_flush_page;
1504 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1506 flush_page_for_dma_global = 0;
1508 srmmu_name = "TI Viking/MXCC";
1509 viking_mxcc_present = 1;
1510 srmmu_cache_pagetables = 1;
1513 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1516 if (sparc_cpu_model == sun4d)
1517 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1518 &viking_sun4d_smp_ops;
1521 poke_srmmu = poke_viking;
1524 /* Probe for the srmmu chip version. */
1525 static void __init get_srmmu_type(void)
1527 unsigned long mreg, psr;
1528 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1530 srmmu_modtype = SRMMU_INVAL_MOD;
1533 mreg = srmmu_get_mmureg(); psr = get_psr();
1534 mod_typ = (mreg & 0xf0000000) >> 28;
1535 mod_rev = (mreg & 0x0f000000) >> 24;
1536 psr_typ = (psr >> 28) & 0xf;
1537 psr_vers = (psr >> 24) & 0xf;
1539 /* First, check for sparc-leon. */
1540 if (sparc_cpu_model == sparc_leon) {
1545 /* Second, check for HyperSparc or Cypress. */
1549 /* UP or MP Hypersparc */
1561 prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1568 /* Now Fujitsu TurboSparc. It might happen that it is
1569 * in Swift emulation mode, so we will check later...
1571 if (psr_typ == 0 && psr_vers == 5) {
1576 /* Next check for Fujitsu Swift. */
1577 if (psr_typ == 0 && psr_vers == 4) {
1581 /* Look if it is not a TurboSparc emulating Swift... */
1582 cpunode = prom_getchild(prom_root_node);
1583 while ((cpunode = prom_getsibling(cpunode)) != 0) {
1584 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1585 if (!strcmp(node_str, "cpu")) {
1586 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1587 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1599 /* Now the Viking family of srmmu. */
1602 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1607 /* Finally the Tsunami. */
1608 if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1618 /* Local cross-calls. */
1619 static void smp_flush_page_for_dma(unsigned long page)
1621 xc1((smpfunc_t) local_ops->page_for_dma, page);
1622 local_ops->page_for_dma(page);
1625 static void smp_flush_cache_all(void)
1627 xc0((smpfunc_t) local_ops->cache_all);
1628 local_ops->cache_all();
1631 static void smp_flush_tlb_all(void)
1633 xc0((smpfunc_t) local_ops->tlb_all);
1634 local_ops->tlb_all();
1637 static void smp_flush_cache_mm(struct mm_struct *mm)
1639 if (mm->context != NO_CONTEXT) {
1641 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1642 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1643 if (!cpumask_empty(&cpu_mask))
1644 xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1645 local_ops->cache_mm(mm);
1649 static void smp_flush_tlb_mm(struct mm_struct *mm)
1651 if (mm->context != NO_CONTEXT) {
1653 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1654 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1655 if (!cpumask_empty(&cpu_mask)) {
1656 xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1657 if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1658 cpumask_copy(mm_cpumask(mm),
1659 cpumask_of(smp_processor_id()));
1661 local_ops->tlb_mm(mm);
1665 static void smp_flush_cache_range(struct vm_area_struct *vma,
1666 unsigned long start,
1669 struct mm_struct *mm = vma->vm_mm;
1671 if (mm->context != NO_CONTEXT) {
1673 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1674 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1675 if (!cpumask_empty(&cpu_mask))
1676 xc3((smpfunc_t) local_ops->cache_range,
1677 (unsigned long) vma, start, end);
1678 local_ops->cache_range(vma, start, end);
1682 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1683 unsigned long start,
1686 struct mm_struct *mm = vma->vm_mm;
1688 if (mm->context != NO_CONTEXT) {
1690 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1691 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1692 if (!cpumask_empty(&cpu_mask))
1693 xc3((smpfunc_t) local_ops->tlb_range,
1694 (unsigned long) vma, start, end);
1695 local_ops->tlb_range(vma, start, end);
1699 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1701 struct mm_struct *mm = vma->vm_mm;
1703 if (mm->context != NO_CONTEXT) {
1705 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1706 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1707 if (!cpumask_empty(&cpu_mask))
1708 xc2((smpfunc_t) local_ops->cache_page,
1709 (unsigned long) vma, page);
1710 local_ops->cache_page(vma, page);
1714 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1716 struct mm_struct *mm = vma->vm_mm;
1718 if (mm->context != NO_CONTEXT) {
1720 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1721 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1722 if (!cpumask_empty(&cpu_mask))
1723 xc2((smpfunc_t) local_ops->tlb_page,
1724 (unsigned long) vma, page);
1725 local_ops->tlb_page(vma, page);
1729 static void smp_flush_page_to_ram(unsigned long page)
1731 /* Current theory is that those who call this are the one's
1732 * who have just dirtied their cache with the pages contents
1733 * in kernel space, therefore we only run this on local cpu.
1735 * XXX This experiment failed, research further... -DaveM
1738 xc1((smpfunc_t) local_ops->page_to_ram, page);
1740 local_ops->page_to_ram(page);
1743 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1746 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1747 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1748 if (!cpumask_empty(&cpu_mask))
1749 xc2((smpfunc_t) local_ops->sig_insns,
1750 (unsigned long) mm, insn_addr);
1751 local_ops->sig_insns(mm, insn_addr);
1754 static struct sparc32_cachetlb_ops smp_cachetlb_ops = {
1755 .cache_all = smp_flush_cache_all,
1756 .cache_mm = smp_flush_cache_mm,
1757 .cache_page = smp_flush_cache_page,
1758 .cache_range = smp_flush_cache_range,
1759 .tlb_all = smp_flush_tlb_all,
1760 .tlb_mm = smp_flush_tlb_mm,
1761 .tlb_page = smp_flush_tlb_page,
1762 .tlb_range = smp_flush_tlb_range,
1763 .page_to_ram = smp_flush_page_to_ram,
1764 .sig_insns = smp_flush_sig_insns,
1765 .page_for_dma = smp_flush_page_for_dma,
1769 /* Load up routines and constants for sun4m and sun4d mmu */
1770 void __init load_mmu(void)
1772 extern void ld_mmu_iommu(void);
1773 extern void ld_mmu_iounit(void);
1779 /* El switcheroo... */
1780 local_ops = sparc32_cachetlb_ops;
1782 if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1783 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1784 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1785 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1786 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1789 if (poke_srmmu == poke_viking) {
1790 /* Avoid unnecessary cross calls. */
1791 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1792 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1793 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1794 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1796 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1797 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1798 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1801 /* It really is const after this point. */
1802 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1806 if (sparc_cpu_model == sun4d)
1811 if (sparc_cpu_model == sun4d)
1813 else if (sparc_cpu_model == sparc_leon)