1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
10 #include <linux/config.h>
11 #include <linux/errno.h>
16 #include <asm/ptrace.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
24 #include <asm/sfafsr.h>
28 #define NR_SYSCALLS 300 /* Each OS is different... */
33 /* This is trivial with the new code... */
36 sethi %hi(TSTATE_PEF), %g4
42 andcc %g5, FPRS_FEF, %g0
46 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
49 109: or %g7, %lo(109b), %g7
51 ba,a,pt %xcc, rtrap_clr_l6
53 1: TRAP_LOAD_THREAD_REG
54 ldub [%g6 + TI_FPSAVED], %g5
55 wr %g0, FPRS_FEF, %fprs
56 andcc %g5, FPRS_FEF, %g0
59 ldx [%g6 + TI_GSR], %g7
60 1: andcc %g5, FPRS_DL, %g0
63 andcc %g5, FPRS_DU, %g0
94 b,pt %xcc, fpdis_exit2
96 1: mov SECONDARY_CONTEXT, %g3
97 add %g6, TI_FPREGS + 0x80, %g1
100 ldxa [%g3] ASI_DMMU, %g5
101 sethi %hi(sparc64_kern_sec_context), %g2
102 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
103 stxa %g2, [%g3] ASI_DMMU
105 add %g6, TI_FPREGS + 0xc0, %g2
109 ldda [%g1] ASI_BLK_S, %f32
110 ldda [%g2] ASI_BLK_S, %f48
122 b,pt %xcc, fpdis_exit
124 2: andcc %g5, FPRS_DU, %g0
127 mov SECONDARY_CONTEXT, %g3
129 ldxa [%g3] ASI_DMMU, %g5
130 add %g6, TI_FPREGS, %g1
131 sethi %hi(sparc64_kern_sec_context), %g2
132 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
133 stxa %g2, [%g3] ASI_DMMU
135 add %g6, TI_FPREGS + 0x40, %g2
136 faddd %f32, %f34, %f36
137 fmuld %f32, %f34, %f38
139 ldda [%g1] ASI_BLK_S, %f0
140 ldda [%g2] ASI_BLK_S, %f16
142 faddd %f32, %f34, %f40
143 fmuld %f32, %f34, %f42
144 faddd %f32, %f34, %f44
145 fmuld %f32, %f34, %f46
146 faddd %f32, %f34, %f48
147 fmuld %f32, %f34, %f50
148 faddd %f32, %f34, %f52
149 fmuld %f32, %f34, %f54
150 faddd %f32, %f34, %f56
151 fmuld %f32, %f34, %f58
152 faddd %f32, %f34, %f60
153 fmuld %f32, %f34, %f62
154 ba,pt %xcc, fpdis_exit
156 3: mov SECONDARY_CONTEXT, %g3
157 add %g6, TI_FPREGS, %g1
158 ldxa [%g3] ASI_DMMU, %g5
159 sethi %hi(sparc64_kern_sec_context), %g2
160 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
161 stxa %g2, [%g3] ASI_DMMU
165 ldda [%g1] ASI_BLK_S, %f0
166 ldda [%g1 + %g2] ASI_BLK_S, %f16
168 ldda [%g1] ASI_BLK_S, %f32
169 ldda [%g1 + %g2] ASI_BLK_S, %f48
172 stxa %g5, [%g3] ASI_DMMU
176 ldx [%g6 + TI_XFSR], %fsr
178 or %g3, %g4, %g3 ! anal...
180 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
186 add %sp, PTREGS_OFF, %o0
190 .globl do_fpother_check_fitos
192 do_fpother_check_fitos:
194 sethi %hi(fp_other_bounce - 4), %g7
195 or %g7, %lo(fp_other_bounce - 4), %g7
197 /* NOTE: Need to preserve %g7 until we fully commit
198 * to the fitos fixup.
200 stx %fsr, [%g6 + TI_XFSR]
202 andcc %g3, TSTATE_PRIV, %g0
203 bne,pn %xcc, do_fptrap_after_fsr
205 ldx [%g6 + TI_XFSR], %g3
208 cmp %g1, 2 ! Unfinished FP-OP
209 bne,pn %xcc, do_fptrap_after_fsr
210 sethi %hi(1 << 23), %g1 ! Inexact
212 bne,pn %xcc, do_fptrap_after_fsr
214 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
215 #define FITOS_MASK 0xc1f83fe0
216 #define FITOS_COMPARE 0x81a01880
217 sethi %hi(FITOS_MASK), %g1
218 or %g1, %lo(FITOS_MASK), %g1
220 sethi %hi(FITOS_COMPARE), %g2
221 or %g2, %lo(FITOS_COMPARE), %g2
223 bne,pn %xcc, do_fptrap_after_fsr
225 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
226 sethi %hi(fitos_table_1), %g1
228 or %g1, %lo(fitos_table_1), %g1
231 ba,pt %xcc, fitos_emul_continue
268 sethi %hi(fitos_table_2), %g1
270 or %g1, %lo(fitos_table_2), %g1
274 ba,pt %xcc, fitos_emul_fini
311 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
317 stx %fsr, [%g6 + TI_XFSR]
319 ldub [%g6 + TI_FPSAVED], %g3
322 stb %g3, [%g6 + TI_FPSAVED]
324 stx %g3, [%g6 + TI_GSR]
325 mov SECONDARY_CONTEXT, %g3
326 ldxa [%g3] ASI_DMMU, %g5
327 sethi %hi(sparc64_kern_sec_context), %g2
328 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
329 stxa %g2, [%g3] ASI_DMMU
331 add %g6, TI_FPREGS, %g2
332 andcc %g1, FPRS_DL, %g0
335 stda %f0, [%g2] ASI_BLK_S
336 stda %f16, [%g2 + %g3] ASI_BLK_S
337 andcc %g1, FPRS_DU, %g0
340 stda %f32, [%g2] ASI_BLK_S
341 stda %f48, [%g2 + %g3] ASI_BLK_S
342 5: mov SECONDARY_CONTEXT, %g1
344 stxa %g5, [%g1] ASI_DMMU
349 /* The registers for cross calls will be:
351 * DATA 0: [low 32-bits] Address of function to call, jmp to this
352 * [high 32-bits] MMU Context Argument 0, place in %g5
353 * DATA 1: Address Argument 1, place in %g1
354 * DATA 2: Address Argument 2, place in %g7
356 * With this method we can do most of the cross-call tlb/cache
357 * flushing very quickly.
364 ldxa [%g3 + %g0] ASI_INTR_R, %g3
365 sethi %hi(KERNBASE), %g4
367 bgeu,pn %xcc, do_ivec_xcall
369 stxa %g0, [%g0] ASI_INTR_RECEIVE
372 sethi %hi(ivector_table), %g2
374 or %g2, %lo(ivector_table), %g2
376 ldub [%g3 + 0x04], %g4 /* pil */
383 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
384 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
385 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
386 wr %g2, 0x0, %set_softint
390 ldxa [%g1 + %g0] ASI_INTR_R, %g1
394 ldxa [%g7 + %g0] ASI_INTR_R, %g7
395 stxa %g0, [%g0] ASI_INTR_RECEIVE
404 .globl save_alternate_globals
405 save_alternate_globals: /* %o0 = save_area */
407 andn %o5, PSTATE_IE, %o1
408 wrpr %o1, PSTATE_AG, %pstate
409 stx %g0, [%o0 + 0x00]
410 stx %g1, [%o0 + 0x08]
411 stx %g2, [%o0 + 0x10]
412 stx %g3, [%o0 + 0x18]
413 stx %g4, [%o0 + 0x20]
414 stx %g5, [%o0 + 0x28]
415 stx %g6, [%o0 + 0x30]
416 stx %g7, [%o0 + 0x38]
417 wrpr %o1, PSTATE_IG, %pstate
418 stx %g0, [%o0 + 0x40]
419 stx %g1, [%o0 + 0x48]
420 stx %g2, [%o0 + 0x50]
421 stx %g3, [%o0 + 0x58]
422 stx %g4, [%o0 + 0x60]
423 stx %g5, [%o0 + 0x68]
424 stx %g6, [%o0 + 0x70]
425 stx %g7, [%o0 + 0x78]
426 wrpr %o1, PSTATE_MG, %pstate
427 stx %g0, [%o0 + 0x80]
428 stx %g1, [%o0 + 0x88]
429 stx %g2, [%o0 + 0x90]
430 stx %g3, [%o0 + 0x98]
431 stx %g4, [%o0 + 0xa0]
432 stx %g5, [%o0 + 0xa8]
433 stx %g6, [%o0 + 0xb0]
434 stx %g7, [%o0 + 0xb8]
435 wrpr %o5, 0x0, %pstate
439 .globl restore_alternate_globals
440 restore_alternate_globals: /* %o0 = save_area */
442 andn %o5, PSTATE_IE, %o1
443 wrpr %o1, PSTATE_AG, %pstate
444 ldx [%o0 + 0x00], %g0
445 ldx [%o0 + 0x08], %g1
446 ldx [%o0 + 0x10], %g2
447 ldx [%o0 + 0x18], %g3
448 ldx [%o0 + 0x20], %g4
449 ldx [%o0 + 0x28], %g5
450 ldx [%o0 + 0x30], %g6
451 ldx [%o0 + 0x38], %g7
452 wrpr %o1, PSTATE_IG, %pstate
453 ldx [%o0 + 0x40], %g0
454 ldx [%o0 + 0x48], %g1
455 ldx [%o0 + 0x50], %g2
456 ldx [%o0 + 0x58], %g3
457 ldx [%o0 + 0x60], %g4
458 ldx [%o0 + 0x68], %g5
459 ldx [%o0 + 0x70], %g6
460 ldx [%o0 + 0x78], %g7
461 wrpr %o1, PSTATE_MG, %pstate
462 ldx [%o0 + 0x80], %g0
463 ldx [%o0 + 0x88], %g1
464 ldx [%o0 + 0x90], %g2
465 ldx [%o0 + 0x98], %g3
466 ldx [%o0 + 0xa0], %g4
467 ldx [%o0 + 0xa8], %g5
468 ldx [%o0 + 0xb0], %g6
469 ldx [%o0 + 0xb8], %g7
470 wrpr %o5, 0x0, %pstate
476 ldx [%o0 + PT_V9_TSTATE], %o1
480 stx %o1, [%o0 + PT_V9_G1]
482 ldx [%o0 + PT_V9_TSTATE], %o1
483 ldx [%o0 + PT_V9_G1], %o2
484 or %g0, %ulo(TSTATE_ICC), %o3
491 stx %o1, [%o0 + PT_V9_TSTATE]
494 utrap_trap: /* %g3=handler,%g4=level */
496 ldx [%g6 + TI_UTRAPS], %g1
497 brnz,pt %g1, invoke_utrap
504 add %sp, PTREGS_OFF, %o0
514 andn %l6, TSTATE_CWP, %l6
515 wrpr %l6, %l7, %tstate
521 /* We need to carefully read the error status, ACK
522 * the errors, prevent recursive traps, and pass the
523 * information on to C code for logging.
525 * We pass the AFAR in as-is, and we encode the status
526 * information as described in asm-sparc64/sfafsr.h
528 .globl __spitfire_access_error
529 __spitfire_access_error:
530 /* Disable ESTATE error reporting so that we do not
531 * take recursive traps and RED state the processor.
533 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
537 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
539 /* __spitfire_cee_trap branches here with AFSR in %g4 and
540 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
541 * ESTATE Error Enable register.
543 __spitfire_cee_trap_continue:
544 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
547 and %g3, 0x1ff, %g3 ! Paranoia
548 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
554 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
558 /* Read in the UDB error register state, clearing the
559 * sticky error bits as-needed. We only clear them if
560 * the UE bit is set. Likewise, __spitfire_cee_trap
561 * below will only do so if the CE bit is set.
563 * NOTE: UltraSparc-I/II have high and low UDB error
564 * registers, corresponding to the two UDB units
565 * present on those chips. UltraSparc-IIi only
566 * has a single UDB, called "SDB" in the manual.
567 * For IIi the upper UDB register always reads
568 * as zero so for our purposes things will just
569 * work with the checks below.
571 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
572 and %g3, 0x3ff, %g7 ! Paranoia
573 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
575 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
578 stxa %g3, [%g0] ASI_UDB_ERROR_W
582 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
583 and %g3, 0x3ff, %g7 ! Paranoia
584 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
586 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
590 stxa %g3, [%g7] ASI_UDB_ERROR_W
593 1: /* Ok, now that we've latched the error state,
594 * clear the sticky bits in the AFSR.
596 stxa %g4, [%g0] ASI_AFSR
611 1: ba,pt %xcc, etrap_irq
616 call spitfire_access_error
617 add %sp, PTREGS_OFF, %o0
621 /* This is the trap handler entry point for ECC correctable
622 * errors. They are corrected, but we listen for the trap
623 * so that the event can be logged.
625 * Disrupting errors are either:
626 * 1) single-bit ECC errors during UDB reads to system
628 * 2) data parity errors during write-back events
630 * As far as I can make out from the manual, the CEE trap
631 * is only for correctable errors during memory read
632 * accesses by the front-end of the processor.
634 * The code below is only for trap level 1 CEE events,
635 * as it is the only situation where we can safely record
636 * and log. For trap level >1 we just clear the CE bit
637 * in the AFSR and return.
639 * This is just like __spiftire_access_error above, but it
640 * specifically handles correctable errors. If an
641 * uncorrectable error is indicated in the AFSR we
642 * will branch directly above to __spitfire_access_error
643 * to handle it instead. Uncorrectable therefore takes
644 * priority over correctable, and the error logging
645 * C code will notice this case by inspecting the
648 .globl __spitfire_cee_trap
650 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
652 sllx %g3, SFAFSR_UE_SHIFT, %g3
653 andcc %g4, %g3, %g0 ! Check for UE
654 bne,pn %xcc, __spitfire_access_error
657 /* Ok, in this case we only have a correctable error.
658 * Indicate we only wish to capture that state in register
659 * %g1, and we only disable CE error reporting unlike UE
660 * handling which disables all errors.
662 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
663 andn %g3, ESTATE_ERR_CE, %g3
664 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
667 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
668 ba,pt %xcc, __spitfire_cee_trap_continue
671 .globl __spitfire_data_access_exception
672 .globl __spitfire_data_access_exception_tl1
673 __spitfire_data_access_exception_tl1:
675 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
678 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
679 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
680 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
683 cmp %g3, 0x80 ! first win spill/fill trap
685 cmp %g3, 0xff ! last win spill/fill trap
688 ba,pt %xcc, winfix_dax
690 1: sethi %hi(109f), %g7
692 109: or %g7, %lo(109b), %g7
695 call spitfire_data_access_exception_tl1
696 add %sp, PTREGS_OFF, %o0
700 __spitfire_data_access_exception:
702 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
705 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
706 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
707 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
711 109: or %g7, %lo(109b), %g7
714 call spitfire_data_access_exception
715 add %sp, PTREGS_OFF, %o0
719 .globl __spitfire_insn_access_exception
720 .globl __spitfire_insn_access_exception_tl1
721 __spitfire_insn_access_exception_tl1:
723 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
725 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
726 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
727 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
731 109: or %g7, %lo(109b), %g7
734 call spitfire_insn_access_exception_tl1
735 add %sp, PTREGS_OFF, %o0
739 __spitfire_insn_access_exception:
741 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
743 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
744 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
745 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
749 109: or %g7, %lo(109b), %g7
752 call spitfire_insn_access_exception
753 add %sp, PTREGS_OFF, %o0
757 /* These get patched into the trap table at boot time
758 * once we know we have a cheetah processor.
760 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
761 cheetah_fecc_trap_vector:
763 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
764 andn %g1, DCU_DC | DCU_IC, %g1
765 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
767 sethi %hi(cheetah_fast_ecc), %g2
768 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
770 cheetah_fecc_trap_vector_tl1:
772 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
773 andn %g1, DCU_DC | DCU_IC, %g1
774 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
776 sethi %hi(cheetah_fast_ecc), %g2
777 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
779 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
780 cheetah_cee_trap_vector:
782 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
783 andn %g1, DCU_IC, %g1
784 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
786 sethi %hi(cheetah_cee), %g2
787 jmpl %g2 + %lo(cheetah_cee), %g0
789 cheetah_cee_trap_vector_tl1:
791 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
792 andn %g1, DCU_IC, %g1
793 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
795 sethi %hi(cheetah_cee), %g2
796 jmpl %g2 + %lo(cheetah_cee), %g0
798 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
799 cheetah_deferred_trap_vector:
801 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
802 andn %g1, DCU_DC | DCU_IC, %g1;
803 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
805 sethi %hi(cheetah_deferred_trap), %g2
806 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
808 cheetah_deferred_trap_vector_tl1:
810 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
811 andn %g1, DCU_DC | DCU_IC, %g1;
812 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
814 sethi %hi(cheetah_deferred_trap), %g2
815 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
818 /* Cheetah+ specific traps. These are for the new I/D cache parity
819 * error traps. The first argument to cheetah_plus_parity_handler
820 * is encoded as follows:
822 * Bit0: 0=dcache,1=icache
823 * Bit1: 0=recoverable,1=unrecoverable
825 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
826 cheetah_plus_dcpe_trap_vector:
828 sethi %hi(do_cheetah_plus_data_parity), %g7
829 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
836 do_cheetah_plus_data_parity:
839 ba,pt %xcc, etrap_irq
842 call cheetah_plus_parity_error
843 add %sp, PTREGS_OFF, %o1
844 ba,a,pt %xcc, rtrap_irq
846 cheetah_plus_dcpe_trap_vector_tl1:
848 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
849 sethi %hi(do_dcpe_tl1), %g3
850 jmpl %g3 + %lo(do_dcpe_tl1), %g0
856 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
857 cheetah_plus_icpe_trap_vector:
859 sethi %hi(do_cheetah_plus_insn_parity), %g7
860 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
867 do_cheetah_plus_insn_parity:
870 ba,pt %xcc, etrap_irq
873 call cheetah_plus_parity_error
874 add %sp, PTREGS_OFF, %o1
875 ba,a,pt %xcc, rtrap_irq
877 cheetah_plus_icpe_trap_vector_tl1:
879 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
880 sethi %hi(do_icpe_tl1), %g3
881 jmpl %g3 + %lo(do_icpe_tl1), %g0
887 /* If we take one of these traps when tl >= 1, then we
888 * jump to interrupt globals. If some trap level above us
889 * was also using interrupt globals, we cannot recover.
890 * We may use all interrupt global registers except %g6.
892 .globl do_dcpe_tl1, do_icpe_tl1
894 rdpr %tl, %g1 ! Save original trap level
895 mov 1, %g2 ! Setup TSTATE checking loop
896 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
897 1: wrpr %g2, %tl ! Set trap level to check
898 rdpr %tstate, %g4 ! Read TSTATE for this level
899 andcc %g4, %g3, %g0 ! Interrupt globals in use?
900 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
901 wrpr %g1, %tl ! Restore original trap level
902 add %g2, 1, %g2 ! Next trap level
903 cmp %g2, %g1 ! Hit them all yet?
904 ble,pt %icc, 1b ! Not yet
906 wrpr %g1, %tl ! Restore original trap level
907 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
908 sethi %hi(dcache_parity_tl1_occurred), %g2
909 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
911 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
912 /* Reset D-cache parity */
913 sethi %hi(1 << 16), %g1 ! D-cache size
914 mov (1 << 5), %g2 ! D-cache line size
915 sub %g1, %g2, %g1 ! Move down 1 cacheline
916 1: srl %g1, 14, %g3 ! Compute UTAG
918 stxa %g3, [%g1] ASI_DCACHE_UTAG
920 sub %g2, 8, %g3 ! 64-bit data word within line
922 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
924 subcc %g3, 8, %g3 ! Next 64-bit data word
927 subcc %g1, %g2, %g1 ! Next cacheline
930 ba,pt %xcc, dcpe_icpe_tl1_common
936 1: or %g7, %lo(1b), %g7
938 call cheetah_plus_parity_error
939 add %sp, PTREGS_OFF, %o1
944 rdpr %tl, %g1 ! Save original trap level
945 mov 1, %g2 ! Setup TSTATE checking loop
946 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
947 1: wrpr %g2, %tl ! Set trap level to check
948 rdpr %tstate, %g4 ! Read TSTATE for this level
949 andcc %g4, %g3, %g0 ! Interrupt globals in use?
950 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
951 wrpr %g1, %tl ! Restore original trap level
952 add %g2, 1, %g2 ! Next trap level
953 cmp %g2, %g1 ! Hit them all yet?
954 ble,pt %icc, 1b ! Not yet
956 wrpr %g1, %tl ! Restore original trap level
957 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
958 sethi %hi(icache_parity_tl1_occurred), %g2
959 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
961 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
963 sethi %hi(1 << 15), %g1 ! I-cache size
964 mov (1 << 5), %g2 ! I-cache line size
966 1: or %g1, (2 << 3), %g3
967 stxa %g0, [%g3] ASI_IC_TAG
972 ba,pt %xcc, dcpe_icpe_tl1_common
978 1: or %g7, %lo(1b), %g7
980 call cheetah_plus_parity_error
981 add %sp, PTREGS_OFF, %o1
985 dcpe_icpe_tl1_common:
986 /* Flush D-cache, re-enable D/I caches in DCU and finally
987 * retry the trapping instruction.
989 sethi %hi(1 << 16), %g1 ! D-cache size
990 mov (1 << 5), %g2 ! D-cache line size
992 1: stxa %g0, [%g1] ASI_DCACHE_TAG
997 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
998 or %g1, (DCU_DC | DCU_IC), %g1
999 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1003 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1005 * %g1: (TL>=0) ? 1 : 0
1010 * %g6: unused, will have current thread ptr after etrap
1013 __cheetah_log_error:
1014 /* Put "TL1" software bit into AFSR. */
1019 /* Get log entry pointer for this cpu at this trap level. */
1020 BRANCH_IF_JALAPENO(g2,g3,50f)
1021 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1026 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1030 60: sllx %g2, 9, %g2
1031 sethi %hi(cheetah_error_log), %g3
1032 ldx [%g3 + %lo(cheetah_error_log)], %g3
1040 /* %g1 holds pointer to the top of the logging scoreboard */
1041 ldx [%g1 + 0x0], %g7
1046 stx %g4, [%g1 + 0x0]
1047 stx %g5, [%g1 + 0x8]
1050 /* %g1 now points to D-cache logging area */
1051 set 0x3ff8, %g2 /* DC_addr mask */
1052 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1054 or %g3, 1, %g3 /* PHYS tag + valid */
1056 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
1057 cmp %g3, %g7 /* TAG match? */
1061 /* Yep, what we want, capture state. */
1062 stx %g2, [%g1 + 0x20]
1063 stx %g7, [%g1 + 0x28]
1065 /* A membar Sync is required before and after utag access. */
1067 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1069 stx %g7, [%g1 + 0x30]
1070 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1071 stx %g7, [%g1 + 0x38]
1074 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1076 add %g3, (1 << 5), %g3
1084 13: sethi %hi(1 << 14), %g7
1093 /* %g1 now points to I-cache logging area */
1094 20: set 0x1fe0, %g2 /* IC_addr mask */
1095 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1096 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1097 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1098 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1100 21: ldxa [%g2] ASI_IC_TAG, %g7
1106 /* Yep, what we want, capture state. */
1107 stx %g2, [%g1 + 0x40]
1108 stx %g7, [%g1 + 0x48]
1109 add %g2, (1 << 3), %g2
1110 ldxa [%g2] ASI_IC_TAG, %g7
1111 add %g2, (1 << 3), %g2
1112 stx %g7, [%g1 + 0x50]
1113 ldxa [%g2] ASI_IC_TAG, %g7
1114 add %g2, (1 << 3), %g2
1115 stx %g7, [%g1 + 0x60]
1116 ldxa [%g2] ASI_IC_TAG, %g7
1117 stx %g7, [%g1 + 0x68]
1118 sub %g2, (3 << 3), %g2
1119 ldxa [%g2] ASI_IC_STAG, %g7
1120 stx %g7, [%g1 + 0x58]
1124 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1126 add %g3, (1 << 3), %g3
1134 23: sethi %hi(1 << 14), %g7
1143 /* %g1 now points to E-cache logging area */
1144 30: andn %g5, (32 - 1), %g2
1145 stx %g2, [%g1 + 0x20]
1146 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1147 stx %g7, [%g1 + 0x28]
1148 ldxa [%g2] ASI_EC_R, %g0
1151 31: ldxa [%g3] ASI_EC_DATA, %g7
1152 stx %g7, [%g1 + %g3]
1165 ba,pt %xcc, c_deferred
1167 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1168 * in the trap table. That code has done a memory barrier
1169 * and has disabled both the I-cache and D-cache in the DCU
1170 * control register. The I-cache is disabled so that we may
1171 * capture the corrupted cache line, and the D-cache is disabled
1172 * because corrupt data may have been placed there and we don't
1173 * want to reference it.
1175 * %g1 is one if this trap occurred at %tl >= 1.
1177 * Next, we turn off error reporting so that we don't recurse.
1179 .globl cheetah_fast_ecc
1181 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1182 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1183 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1186 /* Fetch and clear AFSR/AFAR */
1187 ldxa [%g0] ASI_AFSR, %g4
1188 ldxa [%g0] ASI_AFAR, %g5
1189 stxa %g4, [%g0] ASI_AFSR
1192 ba,pt %xcc, __cheetah_log_error
1198 ba,pt %xcc, etrap_irq
1202 call cheetah_fecc_handler
1203 add %sp, PTREGS_OFF, %o0
1204 ba,a,pt %xcc, rtrap_irq
1206 /* Our caller has disabled I-cache and performed membar Sync. */
1209 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1210 andn %g2, ESTATE_ERROR_CEEN, %g2
1211 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1214 /* Fetch and clear AFSR/AFAR */
1215 ldxa [%g0] ASI_AFSR, %g4
1216 ldxa [%g0] ASI_AFAR, %g5
1217 stxa %g4, [%g0] ASI_AFSR
1220 ba,pt %xcc, __cheetah_log_error
1226 ba,pt %xcc, etrap_irq
1230 call cheetah_cee_handler
1231 add %sp, PTREGS_OFF, %o0
1232 ba,a,pt %xcc, rtrap_irq
1234 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1235 .globl cheetah_deferred_trap
1236 cheetah_deferred_trap:
1237 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1238 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1239 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1242 /* Fetch and clear AFSR/AFAR */
1243 ldxa [%g0] ASI_AFSR, %g4
1244 ldxa [%g0] ASI_AFAR, %g5
1245 stxa %g4, [%g0] ASI_AFSR
1248 ba,pt %xcc, __cheetah_log_error
1254 ba,pt %xcc, etrap_irq
1258 call cheetah_deferred_handler
1259 add %sp, PTREGS_OFF, %o0
1260 ba,a,pt %xcc, rtrap_irq
1265 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1267 sethi %hi(109f), %g7
1269 109: or %g7, %lo(109b), %g7
1271 add %sp, PTREGS_OFF, %o0
1280 /* Setup %g4/%g5 now as they are used in the
1285 ldxa [%g4] ASI_DMMU, %g4
1286 ldxa [%g3] ASI_DMMU, %g5
1287 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1289 bgu,pn %icc, winfix_mna
1292 1: sethi %hi(109f), %g7
1294 109: or %g7, %lo(109b), %g7
1297 call mem_address_unaligned
1298 add %sp, PTREGS_OFF, %o0
1304 sethi %hi(109f), %g7
1306 ldxa [%g4] ASI_DMMU, %g5
1307 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1310 ldxa [%g4] ASI_DMMU, %g4
1312 109: or %g7, %lo(109b), %g7
1316 add %sp, PTREGS_OFF, %o0
1322 sethi %hi(109f), %g7
1324 ldxa [%g4] ASI_DMMU, %g5
1325 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1328 ldxa [%g4] ASI_DMMU, %g4
1330 109: or %g7, %lo(109b), %g7
1334 add %sp, PTREGS_OFF, %o0
1338 .globl breakpoint_trap
1340 call sparc_breakpoint
1341 add %sp, PTREGS_OFF, %o0
1345 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1346 defined(CONFIG_SOLARIS_EMUL_MODULE)
1347 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1348 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1349 * This is complete brain damage.
1355 cmp %o0, NR_SYSCALLS
1358 sethi %hi(sunos_nosys), %l6
1360 or %l6, %lo(sunos_nosys), %l6
1361 1: sethi %hi(sunos_sys_table), %l7
1362 or %l7, %lo(sunos_sys_table), %l7
1363 lduw [%l7 + %o0], %l6
1377 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1378 b,pt %xcc, ret_sys_call
1379 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1381 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1384 call sys32_geteuid16
1387 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1388 b,pt %xcc, ret_sys_call
1389 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1391 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1394 call sys32_getegid16
1397 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1398 b,pt %xcc, ret_sys_call
1399 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1402 /* SunOS's execv() call only specifies the argv argument, the
1403 * environment settings are the same as the calling processes.
1407 sethi %hi(sparc_execve), %g1
1408 ba,pt %xcc, execve_merge
1409 or %g1, %lo(sparc_execve), %g1
1410 #ifdef CONFIG_COMPAT
1413 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1416 sethi %hi(sparc32_execve), %g1
1417 or %g1, %lo(sparc32_execve), %g1
1422 add %sp, PTREGS_OFF, %o0
1424 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1425 .globl sys_rt_sigreturn
1427 .globl sys_sigaltstack
1429 sys_pipe: ba,pt %xcc, sparc_pipe
1430 add %sp, PTREGS_OFF, %o0
1431 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1432 add %sp, PTREGS_OFF, %o0
1433 sys_memory_ordering:
1434 ba,pt %xcc, sparc_memory_ordering
1435 add %sp, PTREGS_OFF, %o1
1436 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1437 add %i6, STACK_BIAS, %o2
1438 #ifdef CONFIG_COMPAT
1439 .globl sys32_sigstack
1440 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1442 .globl sys32_sigaltstack
1444 ba,pt %xcc, do_sys32_sigaltstack
1448 #ifdef CONFIG_COMPAT
1449 .globl sys32_sigreturn
1451 add %sp, PTREGS_OFF, %o0
1453 add %o7, 1f-.-4, %o7
1457 add %sp, PTREGS_OFF, %o0
1458 call do_rt_sigreturn
1459 add %o7, 1f-.-4, %o7
1461 #ifdef CONFIG_COMPAT
1462 .globl sys32_rt_sigreturn
1464 add %sp, PTREGS_OFF, %o0
1465 call do_rt_sigreturn32
1466 add %o7, 1f-.-4, %o7
1469 sys_ptrace: add %sp, PTREGS_OFF, %o0
1471 add %o7, 1f-.-4, %o7
1474 1: ldx [%curptr + TI_FLAGS], %l5
1475 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1478 add %sp, PTREGS_OFF, %o0
1485 /* This is how fork() was meant to be done, 8 instruction entry.
1487 * I questioned the following code briefly, let me clear things
1488 * up so you must not reason on it like I did.
1490 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1491 * need it here because the only piece of window state we copy to
1492 * the child is the CWP register. Even if the parent sleeps,
1493 * we are safe because we stuck it into pt_regs of the parent
1494 * so it will not change.
1496 * XXX This raises the question, whether we can do the same on
1497 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1498 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1499 * XXX fork_kwim in UREG_G1 (global registers are considered
1500 * XXX volatile across a system call in the sparc ABI I think
1501 * XXX if it isn't we can use regs->y instead, anyone who depends
1502 * XXX upon the Y register being preserved across a fork deserves
1505 * In fact we should take advantage of that fact for other things
1506 * during system calls...
1508 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1509 .globl ret_from_syscall
1511 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1512 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1513 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1514 ba,pt %xcc, sys_clone
1520 ba,pt %xcc, sparc_do_fork
1521 add %sp, PTREGS_OFF, %o2
1523 /* Clear current_thread_info()->new_child, and
1524 * check performance counter stuff too.
1526 stb %g0, [%g6 + TI_NEW_CHILD]
1527 ldx [%g6 + TI_FLAGS], %l0
1530 andcc %l0, _TIF_PERFCTR, %g0
1533 ldx [%g6 + TI_PCR], %o7
1536 /* Blackbird errata workaround. See commentary in
1537 * smp.c:smp_percpu_timer_interrupt() for more
1543 99: wr %g0, %g0, %pic
1546 1: b,pt %xcc, ret_sys_call
1547 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1548 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1552 wrpr %g3, 0x0, %cansave
1553 wrpr %g0, 0x0, %otherwin
1554 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1555 ba,pt %xcc, sys_exit
1556 stb %g0, [%g6 + TI_WSAVED]
1558 linux_sparc_ni_syscall:
1559 sethi %hi(sys_ni_syscall), %l7
1561 or %l7, %lo(sys_ni_syscall), %l7
1563 linux_syscall_trace32:
1564 add %sp, PTREGS_OFF, %o0
1574 linux_syscall_trace:
1575 add %sp, PTREGS_OFF, %o0
1586 /* Linux 32-bit and SunOS system calls enter here... */
1588 .globl linux_sparc_syscall32
1589 linux_sparc_syscall32:
1590 /* Direct access to user regs, much faster. */
1591 cmp %g1, NR_SYSCALLS ! IEU1 Group
1592 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1593 srl %i0, 0, %o0 ! IEU0
1594 sll %g1, 2, %l4 ! IEU0 Group
1595 srl %i4, 0, %o4 ! IEU1
1596 lduw [%l7 + %l4], %l7 ! Load
1597 srl %i1, 0, %o1 ! IEU0 Group
1598 ldx [%curptr + TI_FLAGS], %l0 ! Load
1600 srl %i5, 0, %o5 ! IEU1
1601 srl %i2, 0, %o2 ! IEU0 Group
1602 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1603 bne,pn %icc, linux_syscall_trace32 ! CTI
1605 call %l7 ! CTI Group brk forced
1606 srl %i3, 0, %o3 ! IEU0
1609 /* Linux native and SunOS system calls enter here... */
1611 .globl linux_sparc_syscall, ret_sys_call
1612 linux_sparc_syscall:
1613 /* Direct access to user regs, much faster. */
1614 cmp %g1, NR_SYSCALLS ! IEU1 Group
1615 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1617 sll %g1, 2, %l4 ! IEU0 Group
1619 lduw [%l7 + %l4], %l7 ! Load
1620 4: mov %i2, %o2 ! IEU0 Group
1621 ldx [%curptr + TI_FLAGS], %l0 ! Load
1624 mov %i4, %o4 ! IEU0 Group
1625 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1626 bne,pn %icc, linux_syscall_trace ! CTI Group
1628 2: call %l7 ! CTI Group brk forced
1632 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1634 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1635 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1637 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1640 /* Check if force_successful_syscall_return()
1643 ldub [%curptr + TI_SYS_NOERROR], %l2
1645 stb %g0, [%curptr + TI_SYS_NOERROR]
1647 cmp %o0, -ERESTART_RESTARTBLOCK
1649 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1651 /* System call success, clear Carry condition code. */
1653 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1654 bne,pn %icc, linux_syscall_trace2
1655 add %l1, 0x4, %l2 ! npc = npc+4
1656 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1657 ba,pt %xcc, rtrap_clr_l6
1658 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1661 /* System call failure, set Carry condition code.
1662 * Also, get abs(errno) to return to the process.
1664 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1667 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1669 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1670 bne,pn %icc, linux_syscall_trace2
1671 add %l1, 0x4, %l2 ! npc = npc+4
1672 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1675 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1676 linux_syscall_trace2:
1677 add %sp, PTREGS_OFF, %o0
1680 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1682 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1685 .globl __flushw_user
1690 1: save %sp, -128, %sp
1696 restore %g0, %g0, %g0
1700 /* Read cpu ID from hardware, return in %g6.
1701 * (callers_pc - 4) is in %g1. Patched at boot time.
1703 * Default is spitfire implementation.
1705 * The instruction sequence needs to be 5 instructions
1706 * in order to fit the longest implementation, which is
1707 * currently starfire.
1712 ldxa [%g0] ASI_UPA_CONFIG, %g6
1718 __get_cpu_id_cheetah_safari:
1719 ldxa [%g0] ASI_SAFARI_CONFIG, %g6
1725 __get_cpu_id_cheetah_jbus:
1726 ldxa [%g0] ASI_JBUS_CONFIG, %g6
1732 __get_cpu_id_starfire:
1733 sethi %hi(0x1fff40000d0 >> 9), %g6
1737 lduwa [%g6] ASI_PHYS_BYPASS_EC_E, %g6
1739 .globl per_cpu_patch
1741 sethi %hi(this_is_starfire), %o0
1742 lduw [%o0 + %lo(this_is_starfire)], %o1
1743 sethi %hi(__get_cpu_id_starfire), %o0
1745 or %o0, %lo(__get_cpu_id_starfire), %o0
1746 sethi %hi(tlb_type), %o0
1747 lduw [%o0 + %lo(tlb_type)], %o1
1752 sethi %hi(0x003e0016), %o1
1753 or %o1, %lo(0x003e0016), %o1
1755 sethi %hi(__get_cpu_id_cheetah_jbus), %o0
1757 or %o0, %lo(__get_cpu_id_cheetah_jbus), %o0
1758 sethi %hi(__get_cpu_id_cheetah_safari), %o0
1759 or %o0, %lo(__get_cpu_id_cheetah_safari), %o0
1761 sethi %hi(__get_cpu_id), %o1
1762 or %o1, %lo(__get_cpu_id), %o1
1763 lduw [%o0 + 0x00], %o2
1764 stw %o2, [%o1 + 0x00]
1766 lduw [%o0 + 0x04], %o2
1767 stw %o2, [%o1 + 0x04]
1769 lduw [%o0 + 0x08], %o2
1770 stw %o2, [%o1 + 0x08]
1772 lduw [%o0 + 0x0c], %o2
1773 stw %o2, [%o1 + 0x0c]
1775 lduw [%o0 + 0x10], %o2
1776 stw %o2, [%o1 + 0x10]