1 /* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $
2 * pci_iommu.c: UltraSparc PCI controller IOM/STC support.
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
11 #include <linux/delay.h>
15 #include "iommu_common.h"
17 #define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
18 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
20 /* Accessing IOMMU and Streaming Buffer registers.
21 * REG parameter is a physical address. All registers
22 * are 64-bits in size.
24 #define pci_iommu_read(__reg) \
26 __asm__ __volatile__("ldxa [%1] %2, %0" \
28 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
32 #define pci_iommu_write(__reg, __val) \
33 __asm__ __volatile__("stxa %0, [%1] %2" \
35 : "r" (__val), "r" (__reg), \
36 "i" (ASI_PHYS_BYPASS_EC_E))
38 /* Must be invoked under the IOMMU lock. */
39 static void __iommu_flushall(struct pci_iommu *iommu)
44 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
45 for (entry = 0; entry < 16; entry++) {
46 pci_iommu_write(tag, 0);
50 /* Ensure completion of previous PIO writes. */
51 (void) pci_iommu_read(iommu->write_complete_reg);
53 /* Now update everyone's flush point. */
54 for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
55 iommu->alloc_info[entry].flush =
56 iommu->alloc_info[entry].next;
60 #define IOPTE_CONSISTENT(CTX) \
61 (IOPTE_VALID | IOPTE_CACHE | \
62 (((CTX) << 47) & IOPTE_CONTEXT))
64 #define IOPTE_STREAMING(CTX) \
65 (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
67 /* Existing mappings are never marked invalid, instead they
68 * are pointed to a dummy page.
70 #define IOPTE_IS_DUMMY(iommu, iopte) \
71 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
73 static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
75 unsigned long val = iopte_val(*iopte);
78 val |= iommu->dummy_page_pa;
80 iopte_val(*iopte) = val;
83 void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
85 unsigned long i, tsbbase, order;
87 /* Setup initial software IOMMU state. */
88 spin_lock_init(&iommu->lock);
89 iommu->ctx_lowest_free = 1;
90 iommu->page_table_map_base = dma_offset;
91 iommu->dma_addr_mask = dma_addr_mask;
93 switch (tsbsize / (8 * 1024)) {
95 iommu->page_table_sz_bits = 16;
98 iommu->page_table_sz_bits = 17;
101 prom_printf("PCI_IOMMU: Illegal TSB size %d\n",
102 tsbsize / (8 * 1024));
107 iommu->lowest_consistent_map =
108 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
110 for (i = 0; i < PBM_NCLUSTERS; i++) {
111 iommu->alloc_info[i].flush = 0;
112 iommu->alloc_info[i].next = 0;
115 /* Allocate and initialize the dummy page which we
116 * set inactive IO PTEs to point to.
118 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
119 if (!iommu->dummy_page) {
120 prom_printf("PCI_IOMMU: Error, gfp(dummy_page) failed.\n");
123 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
124 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
126 /* Now allocate and setup the IOMMU page table itself. */
127 order = get_order(tsbsize);
128 tsbbase = __get_free_pages(GFP_KERNEL, order);
130 prom_printf("PCI_IOMMU: Error, gfp(tsb) failed.\n");
133 iommu->page_table = (iopte_t *)tsbbase;
135 for (i = 0; i < tsbsize / sizeof(iopte_t); i++)
136 iopte_make_dummy(iommu, &iommu->page_table[i]);
139 static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
141 iopte_t *iopte, *limit, *first;
142 unsigned long cnum, ent, flush_point;
145 while ((1UL << cnum) < npages)
147 iopte = (iommu->page_table +
148 (cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
151 limit = (iommu->page_table +
152 iommu->lowest_consistent_map);
155 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
157 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
158 flush_point = iommu->alloc_info[cnum].flush;
162 if (IOPTE_IS_DUMMY(iommu, iopte)) {
163 if ((iopte + (1 << cnum)) >= limit)
167 iommu->alloc_info[cnum].next = ent;
168 if (ent == flush_point)
169 __iommu_flushall(iommu);
172 iopte += (1 << cnum);
174 if (iopte >= limit) {
175 iopte = (iommu->page_table +
177 (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
180 if (ent == flush_point)
181 __iommu_flushall(iommu);
186 /* I've got your streaming cluster right here buddy boy... */
190 printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
195 static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base,
196 unsigned long npages, unsigned long ctx)
198 unsigned long cnum, ent;
201 while ((1UL << cnum) < npages)
204 ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
205 >> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
207 /* If the global flush might not have caught this entry,
208 * adjust the flush point such that we will flush before
209 * ever trying to reuse it.
211 #define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
212 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
213 iommu->alloc_info[cnum].flush = ent;
217 /* We allocate consistent mappings from the end of cluster zero. */
218 static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
222 iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS));
223 while (iopte > iommu->page_table) {
225 if (IOPTE_IS_DUMMY(iommu, iopte)) {
226 unsigned long tmp = npages;
230 if (!IOPTE_IS_DUMMY(iommu, iopte))
234 u32 entry = (iopte - iommu->page_table);
236 if (entry < iommu->lowest_consistent_map)
237 iommu->lowest_consistent_map = entry;
245 static int iommu_alloc_ctx(struct pci_iommu *iommu)
247 int lowest = iommu->ctx_lowest_free;
248 int sz = IOMMU_NUM_CTXS - lowest;
249 int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
251 if (unlikely(n == sz)) {
252 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
253 if (unlikely(n == lowest)) {
254 printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
259 __set_bit(n, iommu->ctx_bitmap);
264 static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
267 __clear_bit(ctx, iommu->ctx_bitmap);
268 if (ctx < iommu->ctx_lowest_free)
269 iommu->ctx_lowest_free = ctx;
273 /* Allocate and map kernel buffer of size SIZE using consistent mode
274 * DMA for PCI device PDEV. Return non-NULL cpu-side address if
275 * successful and set *DMA_ADDRP to the PCI side dma address.
277 void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
279 struct pcidev_cookie *pcp;
280 struct pci_iommu *iommu;
282 unsigned long flags, order, first_page, ctx;
286 size = IO_PAGE_ALIGN(size);
287 order = get_order(size);
291 first_page = __get_free_pages(GFP_ATOMIC, order);
292 if (first_page == 0UL)
294 memset((char *)first_page, 0, PAGE_SIZE << order);
297 iommu = pcp->pbm->iommu;
299 spin_lock_irqsave(&iommu->lock, flags);
300 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
302 spin_unlock_irqrestore(&iommu->lock, flags);
303 free_pages(first_page, order);
307 *dma_addrp = (iommu->page_table_map_base +
308 ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
309 ret = (void *) first_page;
310 npages = size >> IO_PAGE_SHIFT;
312 if (iommu->iommu_ctxflush)
313 ctx = iommu_alloc_ctx(iommu);
314 first_page = __pa(first_page);
316 iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
318 (first_page & IOPTE_PAGE));
320 first_page += IO_PAGE_SIZE;
325 u32 daddr = *dma_addrp;
327 npages = size >> IO_PAGE_SHIFT;
328 for (i = 0; i < npages; i++) {
329 pci_iommu_write(iommu->iommu_flush, daddr);
330 daddr += IO_PAGE_SIZE;
334 spin_unlock_irqrestore(&iommu->lock, flags);
339 /* Free and unmap a consistent DMA translation. */
340 void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
342 struct pcidev_cookie *pcp;
343 struct pci_iommu *iommu;
345 unsigned long flags, order, npages, i, ctx;
347 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
349 iommu = pcp->pbm->iommu;
350 iopte = iommu->page_table +
351 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
353 spin_lock_irqsave(&iommu->lock, flags);
355 if ((iopte - iommu->page_table) ==
356 iommu->lowest_consistent_map) {
357 iopte_t *walk = iopte + npages;
360 limit = (iommu->page_table +
361 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
362 while (walk < limit) {
363 if (!IOPTE_IS_DUMMY(iommu, walk))
367 iommu->lowest_consistent_map =
368 (walk - iommu->page_table);
371 /* Data for consistent mappings cannot enter the streaming
372 * buffers, so we only need to update the TSB. We flush
373 * the IOMMU here as well to prevent conflicts with the
374 * streaming mapping deferred tlb flush scheme.
378 if (iommu->iommu_ctxflush)
379 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
381 for (i = 0; i < npages; i++, iopte++)
382 iopte_make_dummy(iommu, iopte);
384 if (iommu->iommu_ctxflush) {
385 pci_iommu_write(iommu->iommu_ctxflush, ctx);
387 for (i = 0; i < npages; i++) {
388 u32 daddr = dvma + (i << IO_PAGE_SHIFT);
390 pci_iommu_write(iommu->iommu_flush, daddr);
394 iommu_free_ctx(iommu, ctx);
396 spin_unlock_irqrestore(&iommu->lock, flags);
398 order = get_order(size);
400 free_pages((unsigned long)cpu, order);
403 /* Map a single buffer at PTR of SZ bytes for PCI DMA
406 dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
408 struct pcidev_cookie *pcp;
409 struct pci_iommu *iommu;
410 struct pci_strbuf *strbuf;
412 unsigned long flags, npages, oaddr;
413 unsigned long i, base_paddr, ctx;
415 unsigned long iopte_protection;
418 iommu = pcp->pbm->iommu;
419 strbuf = &pcp->pbm->stc;
421 if (direction == PCI_DMA_NONE)
424 oaddr = (unsigned long)ptr;
425 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
426 npages >>= IO_PAGE_SHIFT;
428 spin_lock_irqsave(&iommu->lock, flags);
430 base = alloc_streaming_cluster(iommu, npages);
433 bus_addr = (iommu->page_table_map_base +
434 ((base - iommu->page_table) << IO_PAGE_SHIFT));
435 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
436 base_paddr = __pa(oaddr & IO_PAGE_MASK);
438 if (iommu->iommu_ctxflush)
439 ctx = iommu_alloc_ctx(iommu);
440 if (strbuf->strbuf_enabled)
441 iopte_protection = IOPTE_STREAMING(ctx);
443 iopte_protection = IOPTE_CONSISTENT(ctx);
444 if (direction != PCI_DMA_TODEVICE)
445 iopte_protection |= IOPTE_WRITE;
447 for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
448 iopte_val(*base) = iopte_protection | base_paddr;
450 spin_unlock_irqrestore(&iommu->lock, flags);
455 spin_unlock_irqrestore(&iommu->lock, flags);
456 return PCI_DMA_ERROR_CODE;
459 static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
463 if (strbuf->strbuf_ctxflush &&
464 iommu->iommu_ctxflush) {
465 unsigned long matchreg, flushreg;
468 flushreg = strbuf->strbuf_ctxflush;
469 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
471 pci_iommu_write(flushreg, ctx);
472 val = pci_iommu_read(matchreg);
479 pci_iommu_write(flushreg, ctx);
482 val = pci_iommu_read(matchreg);
484 printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
485 "timeout matchreg[%lx] ctx[%lx]\n",
493 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
494 pci_iommu_write(strbuf->strbuf_pflush, vaddr);
498 /* If the device could not have possibly put dirty data into
499 * the streaming cache, no flush-flag synchronization needs
502 if (direction == PCI_DMA_TODEVICE)
505 PCI_STC_FLUSHFLAG_INIT(strbuf);
506 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
507 (void) pci_iommu_read(iommu->write_complete_reg);
510 while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
518 printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout "
519 "vaddr[%08x] ctx[%lx] npages[%ld]\n",
523 /* Unmap a single streaming mode DMA translation. */
524 void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
526 struct pcidev_cookie *pcp;
527 struct pci_iommu *iommu;
528 struct pci_strbuf *strbuf;
530 unsigned long flags, npages, ctx;
532 if (direction == PCI_DMA_NONE)
536 iommu = pcp->pbm->iommu;
537 strbuf = &pcp->pbm->stc;
539 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
540 npages >>= IO_PAGE_SHIFT;
541 base = iommu->page_table +
542 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
543 #ifdef DEBUG_PCI_IOMMU
544 if (IOPTE_IS_DUMMY(iommu, base))
545 printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n",
546 bus_addr, sz, __builtin_return_address(0));
548 bus_addr &= IO_PAGE_MASK;
550 spin_lock_irqsave(&iommu->lock, flags);
552 /* Record the context, if any. */
554 if (iommu->iommu_ctxflush)
555 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
557 /* Step 1: Kick data out of streaming buffers if necessary. */
558 if (strbuf->strbuf_enabled)
559 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
561 /* Step 2: Clear out first TSB entry. */
562 iopte_make_dummy(iommu, base);
564 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
567 iommu_free_ctx(iommu, ctx);
569 spin_unlock_irqrestore(&iommu->lock, flags);
572 #define SG_ENT_PHYS_ADDRESS(SG) \
573 (__pa(page_address((SG)->page)) + (SG)->offset)
575 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
576 int nused, int nelems, unsigned long iopte_protection)
578 struct scatterlist *dma_sg = sg;
579 struct scatterlist *sg_end = sg + nelems;
582 for (i = 0; i < nused; i++) {
583 unsigned long pteval = ~0UL;
586 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
588 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
590 unsigned long offset;
593 /* If we are here, we know we have at least one
594 * more page to map. So walk forward until we
595 * hit a page crossing, and begin creating new
596 * mappings from that spot.
601 tmp = SG_ENT_PHYS_ADDRESS(sg);
603 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
604 pteval = tmp & IO_PAGE_MASK;
605 offset = tmp & (IO_PAGE_SIZE - 1UL);
608 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
609 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
611 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
617 pteval = iopte_protection | (pteval & IOPTE_PAGE);
619 *iopte++ = __iopte(pteval);
620 pteval += IO_PAGE_SIZE;
621 len -= (IO_PAGE_SIZE - offset);
626 pteval = (pteval & IOPTE_PAGE) + len;
629 /* Skip over any tail mappings we've fully mapped,
630 * adjusting pteval along the way. Stop when we
631 * detect a page crossing event.
633 while (sg < sg_end &&
634 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
635 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
637 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
638 pteval += sg->length;
641 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
643 } while (dma_npages != 0);
648 /* Map a set of buffers described by SGLIST with NELEMS array
649 * elements in streaming mode for PCI DMA.
650 * When making changes here, inspect the assembly output. I was having
651 * hard time to kepp this routine out of using stack slots for holding variables.
653 int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
655 struct pcidev_cookie *pcp;
656 struct pci_iommu *iommu;
657 struct pci_strbuf *strbuf;
658 unsigned long flags, ctx, npages, iopte_protection;
661 struct scatterlist *sgtmp;
664 /* Fast path single entry scatterlists. */
666 sglist->dma_address =
668 (page_address(sglist->page) + sglist->offset),
669 sglist->length, direction);
670 sglist->dma_length = sglist->length;
675 iommu = pcp->pbm->iommu;
676 strbuf = &pcp->pbm->stc;
678 if (direction == PCI_DMA_NONE)
681 /* Step 1: Prepare scatter list. */
683 npages = prepare_sg(sglist, nelems);
685 /* Step 2: Allocate a cluster. */
687 spin_lock_irqsave(&iommu->lock, flags);
689 base = alloc_streaming_cluster(iommu, npages);
692 dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
694 /* Step 3: Normalize DMA addresses. */
698 while (used && sgtmp->dma_length) {
699 sgtmp->dma_address += dma_base;
703 used = nelems - used;
705 /* Step 4: Choose a context if necessary. */
707 if (iommu->iommu_ctxflush)
708 ctx = iommu_alloc_ctx(iommu);
710 /* Step 5: Create the mappings. */
711 if (strbuf->strbuf_enabled)
712 iopte_protection = IOPTE_STREAMING(ctx);
714 iopte_protection = IOPTE_CONSISTENT(ctx);
715 if (direction != PCI_DMA_TODEVICE)
716 iopte_protection |= IOPTE_WRITE;
717 fill_sg (base, sglist, used, nelems, iopte_protection);
719 verify_sglist(sglist, nelems, base, npages);
722 spin_unlock_irqrestore(&iommu->lock, flags);
727 spin_unlock_irqrestore(&iommu->lock, flags);
728 return PCI_DMA_ERROR_CODE;
731 /* Unmap a set of streaming mode DMA translations. */
732 void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
734 struct pcidev_cookie *pcp;
735 struct pci_iommu *iommu;
736 struct pci_strbuf *strbuf;
738 unsigned long flags, ctx, i, npages;
741 if (direction == PCI_DMA_NONE)
745 iommu = pcp->pbm->iommu;
746 strbuf = &pcp->pbm->stc;
748 bus_addr = sglist->dma_address & IO_PAGE_MASK;
750 for (i = 1; i < nelems; i++)
751 if (sglist[i].dma_length == 0)
754 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT;
756 base = iommu->page_table +
757 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
759 #ifdef DEBUG_PCI_IOMMU
760 if (IOPTE_IS_DUMMY(iommu, base))
761 printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0));
764 spin_lock_irqsave(&iommu->lock, flags);
766 /* Record the context, if any. */
768 if (iommu->iommu_ctxflush)
769 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
771 /* Step 1: Kick data out of streaming buffers if necessary. */
772 if (strbuf->strbuf_enabled)
773 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
775 /* Step 2: Clear out first TSB entry. */
776 iopte_make_dummy(iommu, base);
778 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
781 iommu_free_ctx(iommu, ctx);
783 spin_unlock_irqrestore(&iommu->lock, flags);
786 /* Make physical memory consistent for a single
787 * streaming mode DMA translation after a transfer.
789 void pci_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
791 struct pcidev_cookie *pcp;
792 struct pci_iommu *iommu;
793 struct pci_strbuf *strbuf;
794 unsigned long flags, ctx, npages;
797 iommu = pcp->pbm->iommu;
798 strbuf = &pcp->pbm->stc;
800 if (!strbuf->strbuf_enabled)
803 spin_lock_irqsave(&iommu->lock, flags);
805 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
806 npages >>= IO_PAGE_SHIFT;
807 bus_addr &= IO_PAGE_MASK;
809 /* Step 1: Record the context, if any. */
811 if (iommu->iommu_ctxflush &&
812 strbuf->strbuf_ctxflush) {
815 iopte = iommu->page_table +
816 ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
817 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
820 /* Step 2: Kick data out of streaming buffers. */
821 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
823 spin_unlock_irqrestore(&iommu->lock, flags);
826 /* Make physical memory consistent for a set of streaming
827 * mode DMA translations after a transfer.
829 void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
831 struct pcidev_cookie *pcp;
832 struct pci_iommu *iommu;
833 struct pci_strbuf *strbuf;
834 unsigned long flags, ctx, npages, i;
838 iommu = pcp->pbm->iommu;
839 strbuf = &pcp->pbm->stc;
841 if (!strbuf->strbuf_enabled)
844 spin_lock_irqsave(&iommu->lock, flags);
846 /* Step 1: Record the context, if any. */
848 if (iommu->iommu_ctxflush &&
849 strbuf->strbuf_ctxflush) {
852 iopte = iommu->page_table +
853 ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
854 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
857 /* Step 2: Kick data out of streaming buffers. */
858 bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
859 for(i = 1; i < nelems; i++)
860 if (!sglist[i].dma_length)
863 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
864 - bus_addr) >> IO_PAGE_SHIFT;
865 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
867 spin_unlock_irqrestore(&iommu->lock, flags);
870 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
872 struct pci_dev *ali_isa_bridge;
875 /* ALI sound chips generate 31-bits of DMA, a special register
876 * determines what bit 31 is emitted as.
878 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
879 PCI_DEVICE_ID_AL_M1533,
882 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
887 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
888 pci_dev_put(ali_isa_bridge);
891 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
893 struct pcidev_cookie *pcp = pdev->sysdata;
897 dma_addr_mask = 0xffffffff;
899 struct pci_iommu *iommu = pcp->pbm->iommu;
901 dma_addr_mask = iommu->dma_addr_mask;
903 if (pdev->vendor == PCI_VENDOR_ID_AL &&
904 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
905 device_mask == 0x7fffffff) {
906 ali_sound_dma_hack(pdev,
907 (dma_addr_mask & 0x80000000) != 0);
912 if (device_mask >= (1UL << 32UL))
915 return (device_mask & dma_addr_mask) == dma_addr_mask;