arch/sparc64/kernel/pci_sun4v.c

   1 /* pci_sun4v.c: SUN4V specific PCI controller support.
   2  *
   3  * Copyright (C) 2006 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/percpu.h>
  13
  14 #include <asm/pbm.h>
  15 #include <asm/iommu.h>
  16 #include <asm/irq.h>
  17 #include <asm/upa.h>
  18 #include <asm/pstate.h>
  19 #include <asm/oplib.h>
  20 #include <asm/hypervisor.h>
  21
  22 #include "pci_impl.h"
  23 #include "iommu_common.h"
  24
  25 #include "pci_sun4v.h"
  26
  27 #define PGLIST_NENTS    2048
  28
  29 struct sun4v_pglist {
  30         u64     pglist[PGLIST_NENTS];
  31 };
  32
  33 static DEFINE_PER_CPU(struct sun4v_pglist, iommu_pglists);
  34
  35 static long pci_arena_alloc(struct pci_iommu_arena *arena, unsigned long npages)
  36 {
  37         unsigned long n, i, start, end, limit;
  38         int pass;
  39
  40         limit = arena->limit;
  41         start = arena->hint;
  42         pass = 0;
  43
  44 again:
  45         n = find_next_zero_bit(arena->map, limit, start);
  46         end = n + npages;
  47         if (unlikely(end >= limit)) {
  48                 if (likely(pass < 1)) {
  49                         limit = start;
  50                         start = 0;
  51                         pass++;
  52                         goto again;
  53                 } else {
  54                         /* Scanned the whole thing, give up. */
  55                         return -1;
  56                 }
  57         }
  58
  59         for (i = n; i < end; i++) {
  60                 if (test_bit(i, arena->map)) {
  61                         start = i + 1;
  62                         goto again;
  63                 }
  64         }
  65
  66         for (i = n; i < end; i++)
  67                 __set_bit(i, arena->map);
  68
  69         arena->hint = end;
  70
  71         return n;
  72 }
  73
  74 static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
  75 {
  76         unsigned long i;
  77
  78         for (i = base; i < (base + npages); i++)
  79                 __clear_bit(i, arena->map);
  80 }
  81
  82 static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
  83 {
  84         struct pcidev_cookie *pcp;
  85         struct pci_iommu *iommu;
  86         unsigned long devhandle, flags, order, first_page, npages, n;
  87         void *ret;
  88         long entry;
  89         u64 *pglist;
  90         int cpu;
  91
  92         size = IO_PAGE_ALIGN(size);
  93         order = get_order(size);
  94         if (order >= MAX_ORDER)
  95                 return NULL;
  96
  97         npages = size >> IO_PAGE_SHIFT;
  98         if (npages > PGLIST_NENTS)
  99                 return NULL;
 100
 101         first_page = __get_free_pages(GFP_ATOMIC, order);
 102         if (first_page == 0UL)
 103                 return NULL;
 104         memset((char *)first_page, 0, PAGE_SIZE << order);
 105
 106         pcp = pdev->sysdata;
 107         devhandle = pcp->pbm->devhandle;
 108         iommu = pcp->pbm->iommu;
 109
 110         spin_lock_irqsave(&iommu->lock, flags);
 111         entry = pci_arena_alloc(&iommu->arena, npages);
 112         spin_unlock_irqrestore(&iommu->lock, flags);
 113
 114         if (unlikely(entry < 0L)) {
 115                 free_pages(first_page, order);
 116                 return NULL;
 117         }
 118
 119         *dma_addrp = (iommu->page_table_map_base +
 120                       (entry << IO_PAGE_SHIFT));
 121         ret = (void *) first_page;
 122         first_page = __pa(first_page);
 123
 124         cpu = get_cpu();
 125
 126         pglist = &__get_cpu_var(iommu_pglists).pglist[0];
 127         for (n = 0; n < npages; n++)
 128                 pglist[n] = first_page + (n * PAGE_SIZE);
 129
 130         do {
 131                 unsigned long num;
 132
 133                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
 134                                           npages,
 135                                           (HV_PCI_MAP_ATTR_READ |
 136                                            HV_PCI_MAP_ATTR_WRITE),
 137                                           __pa(pglist));
 138                 entry += num;
 139                 npages -= num;
 140                 pglist += num;
 141         } while (npages != 0);
 142
 143         put_cpu();
 144
 145         return ret;
 146 }
 147
 148 static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
 149 {
 150         struct pcidev_cookie *pcp;
 151         struct pci_iommu *iommu;
 152         unsigned long flags, order, npages, entry, devhandle;
 153
 154         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 155         pcp = pdev->sysdata;
 156         iommu = pcp->pbm->iommu;
 157         devhandle = pcp->pbm->devhandle;
 158         entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 159
 160         spin_lock_irqsave(&iommu->lock, flags);
 161
 162         pci_arena_free(&iommu->arena, entry, npages);
 163
 164         do {
 165                 unsigned long num;
 166
 167                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 168                                             npages);
 169                 entry += num;
 170                 npages -= num;
 171         } while (npages != 0);
 172
 173         spin_unlock_irqrestore(&iommu->lock, flags);
 174
 175         order = get_order(size);
 176         if (order < 10)
 177                 free_pages((unsigned long)cpu, order);
 178 }
 179
 180 static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
 181 {
 182         struct pcidev_cookie *pcp;
 183         struct pci_iommu *iommu;
 184         unsigned long flags, npages, oaddr;
 185         unsigned long i, base_paddr, devhandle;
 186         u32 bus_addr, ret;
 187         unsigned long prot;
 188         long entry;
 189         u64 *pglist;
 190         int cpu;
 191
 192         pcp = pdev->sysdata;
 193         iommu = pcp->pbm->iommu;
 194         devhandle = pcp->pbm->devhandle;
 195
 196         if (unlikely(direction == PCI_DMA_NONE))
 197                 goto bad;
 198
 199         oaddr = (unsigned long)ptr;
 200         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 201         npages >>= IO_PAGE_SHIFT;
 202         if (unlikely(npages > PGLIST_NENTS))
 203                 goto bad;
 204
 205         spin_lock_irqsave(&iommu->lock, flags);
 206         entry = pci_arena_alloc(&iommu->arena, npages);
 207         spin_unlock_irqrestore(&iommu->lock, flags);
 208
 209         if (unlikely(entry < 0L))
 210                 goto bad;
 211
 212         bus_addr = (iommu->page_table_map_base +
 213                     (entry << IO_PAGE_SHIFT));
 214         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 215         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 216         prot = HV_PCI_MAP_ATTR_READ;
 217         if (direction != PCI_DMA_TODEVICE)
 218                 prot |= HV_PCI_MAP_ATTR_WRITE;
 219
 220         cpu = get_cpu();
 221
 222         pglist = &__get_cpu_var(iommu_pglists).pglist[0];
 223         for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE)
 224                 pglist[i] = base_paddr;
 225
 226         do {
 227                 unsigned long num;
 228
 229                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
 230                                           npages, prot,
 231                                           __pa(pglist));
 232                 entry += num;
 233                 npages -= num;
 234                 pglist += num;
 235         } while (npages != 0);
 236
 237         put_cpu();
 238
 239         return ret;
 240
 241 bad:
 242         if (printk_ratelimit())
 243                 WARN_ON(1);
 244         return PCI_DMA_ERROR_CODE;
 245 }
 246
 247 static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
 248 {
 249         struct pcidev_cookie *pcp;
 250         struct pci_iommu *iommu;
 251         unsigned long flags, npages, devhandle;
 252         long entry;
 253
 254         if (unlikely(direction == PCI_DMA_NONE)) {
 255                 if (printk_ratelimit())
 256                         WARN_ON(1);
 257                 return;
 258         }
 259
 260         pcp = pdev->sysdata;
 261         iommu = pcp->pbm->iommu;
 262         devhandle = pcp->pbm->devhandle;
 263
 264         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 265         npages >>= IO_PAGE_SHIFT;
 266         bus_addr &= IO_PAGE_MASK;
 267
 268         spin_lock_irqsave(&iommu->lock, flags);
 269
 270         entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
 271         pci_arena_free(&iommu->arena, entry, npages);
 272
 273         do {
 274                 unsigned long num;
 275
 276                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 277                                             npages);
 278                 entry += num;
 279                 npages -= num;
 280         } while (npages != 0);
 281
 282         spin_unlock_irqrestore(&iommu->lock, flags);
 283 }
 284
 285 #define SG_ENT_PHYS_ADDRESS(SG) \
 286         (__pa(page_address((SG)->page)) + (SG)->offset)
 287
 288 static inline void fill_sg(long entry, unsigned long devhandle,
 289                            struct scatterlist *sg,
 290                            int nused, int nelems, unsigned long prot)
 291 {
 292         struct scatterlist *dma_sg = sg;
 293         struct scatterlist *sg_end = sg + nelems;
 294         int i, cpu, pglist_ent;
 295         u64 *pglist;
 296
 297         cpu = get_cpu();
 298         pglist = &__get_cpu_var(iommu_pglists).pglist[0];
 299         pglist_ent = 0;
 300         for (i = 0; i < nused; i++) {
 301                 unsigned long pteval = ~0UL;
 302                 u32 dma_npages;
 303
 304                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
 305                               dma_sg->dma_length +
 306                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
 307                 do {
 308                         unsigned long offset;
 309                         signed int len;
 310
 311                         /* If we are here, we know we have at least one
 312                          * more page to map.  So walk forward until we
 313                          * hit a page crossing, and begin creating new
 314                          * mappings from that spot.
 315                          */
 316                         for (;;) {
 317                                 unsigned long tmp;
 318
 319                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
 320                                 len = sg->length;
 321                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
 322                                         pteval = tmp & IO_PAGE_MASK;
 323                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
 324                                         break;
 325                                 }
 326                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
 327                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
 328                                         offset = 0UL;
 329                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
 330                                         break;
 331                                 }
 332                                 sg++;
 333                         }
 334
 335                         pteval = (pteval & IOPTE_PAGE);
 336                         while (len > 0) {
 337                                 pglist[pglist_ent++] = pteval;
 338                                 pteval += IO_PAGE_SIZE;
 339                                 len -= (IO_PAGE_SIZE - offset);
 340                                 offset = 0;
 341                                 dma_npages--;
 342                         }
 343
 344                         pteval = (pteval & IOPTE_PAGE) + len;
 345                         sg++;
 346
 347                         /* Skip over any tail mappings we've fully mapped,
 348                          * adjusting pteval along the way.  Stop when we
 349                          * detect a page crossing event.
 350                          */
 351                         while (sg < sg_end &&
 352                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
 353                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
 354                                ((pteval ^
 355                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
 356                                 pteval += sg->length;
 357                                 sg++;
 358                         }
 359                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
 360                                 pteval = ~0UL;
 361                 } while (dma_npages != 0);
 362                 dma_sg++;
 363         }
 364
 365         BUG_ON(pglist_ent == 0);
 366
 367         do {
 368                 unsigned long num;
 369
 370                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 371                                             pglist_ent);
 372                 entry += num;
 373                 pglist_ent -= num;
 374         } while (pglist_ent != 0);
 375
 376         put_cpu();
 377 }
 378
 379 static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 380 {
 381         struct pcidev_cookie *pcp;
 382         struct pci_iommu *iommu;
 383         unsigned long flags, npages, prot, devhandle;
 384         u32 dma_base;
 385         struct scatterlist *sgtmp;
 386         long entry;
 387         int used;
 388
 389         /* Fast path single entry scatterlists. */
 390         if (nelems == 1) {
 391                 sglist->dma_address =
 392                         pci_4v_map_single(pdev,
 393                                           (page_address(sglist->page) + sglist->offset),
 394                                           sglist->length, direction);
 395                 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
 396                         return 0;
 397                 sglist->dma_length = sglist->length;
 398                 return 1;
 399         }
 400
 401         pcp = pdev->sysdata;
 402         iommu = pcp->pbm->iommu;
 403         devhandle = pcp->pbm->devhandle;
 404
 405         if (unlikely(direction == PCI_DMA_NONE))
 406                 goto bad;
 407
 408         /* Step 1: Prepare scatter list. */
 409         npages = prepare_sg(sglist, nelems);
 410         if (unlikely(npages > PGLIST_NENTS))
 411                 goto bad;
 412
 413         /* Step 2: Allocate a cluster and context, if necessary. */
 414         spin_lock_irqsave(&iommu->lock, flags);
 415         entry = pci_arena_alloc(&iommu->arena, npages);
 416         spin_unlock_irqrestore(&iommu->lock, flags);
 417
 418         if (unlikely(entry < 0L))
 419                 goto bad;
 420
 421         dma_base = iommu->page_table_map_base +
 422                 (entry << IO_PAGE_SHIFT);
 423
 424         /* Step 3: Normalize DMA addresses. */
 425         used = nelems;
 426
 427         sgtmp = sglist;
 428         while (used && sgtmp->dma_length) {
 429                 sgtmp->dma_address += dma_base;
 430                 sgtmp++;
 431                 used--;
 432         }
 433         used = nelems - used;
 434
 435         /* Step 4: Create the mappings. */
 436         prot = HV_PCI_MAP_ATTR_READ;
 437         if (direction != PCI_DMA_TODEVICE)
 438                 prot |= HV_PCI_MAP_ATTR_WRITE;
 439
 440         fill_sg(entry, devhandle, sglist, used, nelems, prot);
 441
 442         return used;
 443
 444 bad:
 445         if (printk_ratelimit())
 446                 WARN_ON(1);
 447         return 0;
 448 }
 449
 450 static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 451 {
 452         struct pcidev_cookie *pcp;
 453         struct pci_iommu *iommu;
 454         unsigned long flags, i, npages, devhandle;
 455         long entry;
 456         u32 bus_addr;
 457
 458         if (unlikely(direction == PCI_DMA_NONE)) {
 459                 if (printk_ratelimit())
 460                         WARN_ON(1);
 461         }
 462
 463         pcp = pdev->sysdata;
 464         iommu = pcp->pbm->iommu;
 465         devhandle = pcp->pbm->devhandle;
 466
 467         bus_addr = sglist->dma_address & IO_PAGE_MASK;
 468
 469         for (i = 1; i < nelems; i++)
 470                 if (sglist[i].dma_length == 0)
 471                         break;
 472         i--;
 473         npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
 474                   bus_addr) >> IO_PAGE_SHIFT;
 475
 476         entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 477
 478         spin_lock_irqsave(&iommu->lock, flags);
 479
 480         pci_arena_free(&iommu->arena, entry, npages);
 481
 482         do {
 483                 unsigned long num;
 484
 485                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 486                                             npages);
 487                 entry += num;
 488                 npages -= num;
 489         } while (npages != 0);
 490
 491         spin_unlock_irqrestore(&iommu->lock, flags);
 492 }
 493
 494 static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
 495 {
 496         /* Nothing to do... */
 497 }
 498
 499 static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 500 {
 501         /* Nothing to do... */
 502 }
 503
 504 struct pci_iommu_ops pci_sun4v_iommu_ops = {
 505         .alloc_consistent               = pci_4v_alloc_consistent,
 506         .free_consistent                = pci_4v_free_consistent,
 507         .map_single                     = pci_4v_map_single,
 508         .unmap_single                   = pci_4v_unmap_single,
 509         .map_sg                         = pci_4v_map_sg,
 510         .unmap_sg                       = pci_4v_unmap_sg,
 511         .dma_sync_single_for_cpu        = pci_4v_dma_sync_single_for_cpu,
 512         .dma_sync_sg_for_cpu            = pci_4v_dma_sync_sg_for_cpu,
 513 };
 514
 515 /* SUN4V PCI configuration space accessors. */
 516
 517 static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus)
 518 {
 519         if (bus < pbm->pci_first_busno ||
 520             bus > pbm->pci_last_busno)
 521                 return 1;
 522         return 0;
 523 }
 524
 525 static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 526                                   int where, int size, u32 *value)
 527 {
 528         struct pci_pbm_info *pbm = bus_dev->sysdata;
 529         u32 devhandle = pbm->devhandle;
 530         unsigned int bus = bus_dev->number;
 531         unsigned int device = PCI_SLOT(devfn);
 532         unsigned int func = PCI_FUNC(devfn);
 533         unsigned long ret;
 534
 535         if (pci_sun4v_out_of_range(pbm, bus)) {
 536                 ret = ~0UL;
 537         } else {
 538                 ret = pci_sun4v_config_get(devhandle,
 539                                 HV_PCI_DEVICE_BUILD(bus, device, func),
 540                                 where, size);
 541 #if 0
 542                 printk("read_pci_cfg: devh[%x] device[%08x] where[%x] sz[%d] "
 543                        "== [%016lx]\n",
 544                        devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
 545                        where, size, ret);
 546 #endif
 547         }
 548         switch (size) {
 549         case 1:
 550                 *value = ret & 0xff;
 551                 break;
 552         case 2:
 553                 *value = ret & 0xffff;
 554                 break;
 555         case 4:
 556                 *value = ret & 0xffffffff;
 557                 break;
 558         };
 559
 560
 561         return PCIBIOS_SUCCESSFUL;
 562 }
 563
 564 static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 565                                    int where, int size, u32 value)
 566 {
 567         struct pci_pbm_info *pbm = bus_dev->sysdata;
 568         u32 devhandle = pbm->devhandle;
 569         unsigned int bus = bus_dev->number;
 570         unsigned int device = PCI_SLOT(devfn);
 571         unsigned int func = PCI_FUNC(devfn);
 572         unsigned long ret;
 573
 574         if (pci_sun4v_out_of_range(pbm, bus)) {
 575                 /* Do nothing. */
 576         } else {
 577                 ret = pci_sun4v_config_put(devhandle,
 578                                 HV_PCI_DEVICE_BUILD(bus, device, func),
 579                                 where, size, value);
 580 #if 0
 581                 printk("write_pci_cfg: devh[%x] device[%08x] where[%x] sz[%d] "
 582                        "val[%08x] == [%016lx]\n",
 583                        devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
 584                        where, size, value, ret);
 585 #endif
 586         }
 587         return PCIBIOS_SUCCESSFUL;
 588 }
 589
 590 static struct pci_ops pci_sun4v_ops = {
 591         .read =         pci_sun4v_read_pci_cfg,
 592         .write =        pci_sun4v_write_pci_cfg,
 593 };
 594
 595
 596 static void pbm_scan_bus(struct pci_controller_info *p,
 597                          struct pci_pbm_info *pbm)
 598 {
 599         struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
 600
 601         if (!cookie) {
 602                 prom_printf("%s: Critical allocation failure.\n", pbm->name);
 603                 prom_halt();
 604         }
 605
 606         /* All we care about is the PBM. */
 607         memset(cookie, 0, sizeof(*cookie));
 608         cookie->pbm = pbm;
 609
 610         pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
 611                                     p->pci_ops,
 612                                     pbm);
 613 #if 0
 614         pci_fixup_host_bridge_self(pbm->pci_bus);
 615         pbm->pci_bus->self->sysdata = cookie;
 616 #endif
 617
 618         pci_fill_in_pbm_cookies(pbm->pci_bus, pbm,
 619                                 prom_getchild(pbm->prom_node));
 620         pci_record_assignments(pbm, pbm->pci_bus);
 621         pci_assign_unassigned(pbm, pbm->pci_bus);
 622         pci_fixup_irq(pbm, pbm->pci_bus);
 623         pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
 624         pci_setup_busmastering(pbm, pbm->pci_bus);
 625 }
 626
 627 static void pci_sun4v_scan_bus(struct pci_controller_info *p)
 628 {
 629         if (p->pbm_A.prom_node) {
 630                 p->pbm_A.is_66mhz_capable =
 631                         prom_getbool(p->pbm_A.prom_node, "66mhz-capable");
 632
 633                 pbm_scan_bus(p, &p->pbm_A);
 634         }
 635         if (p->pbm_B.prom_node) {
 636                 p->pbm_B.is_66mhz_capable =
 637                         prom_getbool(p->pbm_B.prom_node, "66mhz-capable");
 638
 639                 pbm_scan_bus(p, &p->pbm_B);
 640         }
 641
 642         /* XXX register error interrupt handlers XXX */
 643 }
 644
 645 static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
 646                                         struct pci_dev *pdev,
 647                                         unsigned int ino)
 648 {
 649         struct ino_bucket *bucket;
 650         unsigned long sysino;
 651         u32 devhandle = pbm->devhandle;
 652         int pil;
 653
 654         sysino = sun4v_devino_to_sysino(devhandle, ino);
 655
 656         printk(KERN_INFO "pci_irq_buld: Mapping ( devh[%08x] ino[%08x] ) "
 657                "--> sysino[%016lx]\n", devhandle, ino, sysino);
 658
 659         pil = 4;
 660         if (pdev) {
 661                 switch ((pdev->class >> 16) & 0xff) {
 662                 case PCI_BASE_CLASS_STORAGE:
 663                         pil = 4;
 664                         break;
 665
 666                 case PCI_BASE_CLASS_NETWORK:
 667                         pil = 6;
 668                         break;
 669
 670                 case PCI_BASE_CLASS_DISPLAY:
 671                         pil = 9;
 672                         break;
 673
 674                 case PCI_BASE_CLASS_MULTIMEDIA:
 675                 case PCI_BASE_CLASS_MEMORY:
 676                 case PCI_BASE_CLASS_BRIDGE:
 677                 case PCI_BASE_CLASS_SERIAL:
 678                         pil = 10;
 679                         break;
 680
 681                 default:
 682                         pil = 4;
 683                         break;
 684                 };
 685         }
 686         BUG_ON(PIL_RESERVED(pil));
 687
 688         bucket = &ivector_table[sysino];
 689
 690         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 691          * is done by hypervisor calls on sun4v platforms, not by direct
 692          * register accesses.
 693          */
 694         bucket->imap = ~0UL;
 695         bucket->iclr = ~0UL;
 696
 697         bucket->pil = pil;
 698         bucket->flags = IBF_PCI;
 699
 700         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 701         if (!bucket->irq_info) {
 702                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 703                 prom_halt();
 704         }
 705         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 706
 707         return __irq(bucket);
 708 }
 709
 710 static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
 711 {
 712         struct pcidev_cookie *pcp = pdev->sysdata;
 713         struct pci_pbm_info *pbm = pcp->pbm;
 714         struct resource *res, *root;
 715         u32 reg;
 716         int where, size, is_64bit;
 717
 718         res = &pdev->resource[resource];
 719         if (resource < 6) {
 720                 where = PCI_BASE_ADDRESS_0 + (resource * 4);
 721         } else if (resource == PCI_ROM_RESOURCE) {
 722                 where = pdev->rom_base_reg;
 723         } else {
 724                 /* Somebody might have asked allocation of a non-standard resource */
 725                 return;
 726         }
 727
 728         /* XXX 64-bit MEM handling is not %100 correct... XXX */
 729         is_64bit = 0;
 730         if (res->flags & IORESOURCE_IO)
 731                 root = &pbm->io_space;
 732         else {
 733                 root = &pbm->mem_space;
 734                 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
 735                     == PCI_BASE_ADDRESS_MEM_TYPE_64)
 736                         is_64bit = 1;
 737         }
 738
 739         size = res->end - res->start;
 740         pci_read_config_dword(pdev, where, &reg);
 741         reg = ((reg & size) |
 742                (((u32)(res->start - root->start)) & ~size));
 743         if (resource == PCI_ROM_RESOURCE) {
 744                 reg |= PCI_ROM_ADDRESS_ENABLE;
 745                 res->flags |= IORESOURCE_ROM_ENABLE;
 746         }
 747         pci_write_config_dword(pdev, where, reg);
 748
 749         /* This knows that the upper 32-bits of the address
 750          * must be zero.  Our PCI common layer enforces this.
 751          */
 752         if (is_64bit)
 753                 pci_write_config_dword(pdev, where + 4, 0);
 754 }
 755
 756 static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
 757                                       struct resource *res,
 758                                       struct resource *root)
 759 {
 760         res->start += root->start;
 761         res->end += root->start;
 762 }
 763
 764 /* Use ranges property to determine where PCI MEM, I/O, and Config
 765  * space are for this PCI bus module.
 766  */
 767 static void pci_sun4v_determine_mem_io_space(struct pci_pbm_info *pbm)
 768 {
 769         int i, saw_mem, saw_io;
 770
 771         saw_mem = saw_io = 0;
 772         for (i = 0; i < pbm->num_pbm_ranges; i++) {
 773                 struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
 774                 unsigned long a;
 775                 int type;
 776
 777                 type = (pr->child_phys_hi >> 24) & 0x3;
 778                 a = (((unsigned long)pr->parent_phys_hi << 32UL) |
 779                      ((unsigned long)pr->parent_phys_lo  <<  0UL));
 780
 781                 switch (type) {
 782                 case 1:
 783                         /* 16-bit IO space, 16MB */
 784                         pbm->io_space.start = a;
 785                         pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
 786                         pbm->io_space.flags = IORESOURCE_IO;
 787                         saw_io = 1;
 788                         break;
 789
 790                 case 2:
 791                         /* 32-bit MEM space, 2GB */
 792                         pbm->mem_space.start = a;
 793                         pbm->mem_space.end = a + (0x80000000UL - 1UL);
 794                         pbm->mem_space.flags = IORESOURCE_MEM;
 795                         saw_mem = 1;
 796                         break;
 797
 798                 case 3:
 799                         /* XXX 64-bit MEM handling XXX */
 800
 801                 default:
 802                         break;
 803                 };
 804         }
 805
 806         if (!saw_io || !saw_mem) {
 807                 prom_printf("%s: Fatal error, missing %s PBM range.\n",
 808                             pbm->name,
 809                             (!saw_io ? "IO" : "MEM"));
 810                 prom_halt();
 811         }
 812
 813         printk("%s: PCI IO[%lx] MEM[%lx]\n",
 814                pbm->name,
 815                pbm->io_space.start,
 816                pbm->mem_space.start);
 817 }
 818
 819 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
 820                                             struct pci_pbm_info *pbm)
 821 {
 822         pbm->io_space.name = pbm->mem_space.name = pbm->name;
 823
 824         request_resource(&ioport_resource, &pbm->io_space);
 825         request_resource(&iomem_resource, &pbm->mem_space);
 826         pci_register_legacy_regions(&pbm->io_space,
 827                                     &pbm->mem_space);
 828 }
 829
 830 static void probe_existing_entries(struct pci_pbm_info *pbm,
 831                                    struct pci_iommu *iommu)
 832 {
 833         struct pci_iommu_arena *arena = &iommu->arena;
 834         unsigned long i, devhandle;
 835
 836         devhandle = pbm->devhandle;
 837         for (i = 0; i < arena->limit; i++) {
 838                 unsigned long ret, io_attrs, ra;
 839
 840                 ret = pci_sun4v_iommu_getmap(devhandle,
 841                                              HV_PCI_TSBID(0, i),
 842                                              &io_attrs, &ra);
 843                 if (ret == HV_EOK)
 844                         __set_bit(i, arena->map);
 845         }
 846 }
 847
 848 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
 849 {
 850         struct pci_iommu *iommu = pbm->iommu;
 851         unsigned long num_tsb_entries, sz;
 852         u32 vdma[2], dma_mask, dma_offset;
 853         int err, tsbsize;
 854
 855         err = prom_getproperty(pbm->prom_node, "virtual-dma",
 856                                (char *)&vdma[0], sizeof(vdma));
 857         if (err == 0 || err == -1) {
 858                 /* No property, use default values. */
 859                 vdma[0] = 0x80000000;
 860                 vdma[1] = 0x80000000;
 861         }
 862
 863         dma_mask = vdma[0];
 864         switch (vdma[1]) {
 865                 case 0x20000000:
 866                         dma_mask |= 0x1fffffff;
 867                         tsbsize = 64;
 868                         break;
 869
 870                 case 0x40000000:
 871                         dma_mask |= 0x3fffffff;
 872                         tsbsize = 128;
 873                         break;
 874
 875                 case 0x80000000:
 876                         dma_mask |= 0x7fffffff;
 877                         tsbsize = 128;
 878                         break;
 879
 880                 default:
 881                         prom_printf("PCI-SUN4V: strange virtual-dma size.\n");
 882                         prom_halt();
 883         };
 884
 885         num_tsb_entries = tsbsize / sizeof(iopte_t);
 886
 887         dma_offset = vdma[0];
 888
 889         /* Setup initial software IOMMU state. */
 890         spin_lock_init(&iommu->lock);
 891         iommu->ctx_lowest_free = 1;
 892         iommu->page_table_map_base = dma_offset;
 893         iommu->dma_addr_mask = dma_mask;
 894
 895         /* Allocate and initialize the free area map.  */
 896         sz = num_tsb_entries / 8;
 897         sz = (sz + 7UL) & ~7UL;
 898         iommu->arena.map = kmalloc(sz, GFP_KERNEL);
 899         if (!iommu->arena.map) {
 900                 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
 901                 prom_halt();
 902         }
 903         memset(iommu->arena.map, 0, sz);
 904         iommu->arena.limit = num_tsb_entries;
 905
 906         probe_existing_entries(pbm, iommu);
 907 }
 908
 909 /* Don't get this from the root nexus, get it from the "pci@0" node below.  */
 910 static void pci_sun4v_get_bus_range(struct pci_pbm_info *pbm)
 911 {
 912         unsigned int busrange[2];
 913         int prom_node = pbm->prom_node;
 914         int err;
 915
 916         prom_node = prom_getchild(prom_node);
 917         if (prom_node == 0) {
 918                 prom_printf("%s: Fatal error, no child OBP node.\n", pbm->name);
 919                 prom_halt();
 920         }
 921
 922         err = prom_getproperty(prom_node, "bus-range",
 923                                (char *)&busrange[0],
 924                                sizeof(busrange));
 925         if (err == 0 || err == -1) {
 926                 prom_printf("%s: Fatal error, no bus-range.\n", pbm->name);
 927                 prom_halt();
 928         }
 929
 930         pbm->pci_first_busno = busrange[0];
 931         pbm->pci_last_busno = busrange[1];
 932
 933 }
 934
 935 static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node, unsigned int devhandle)
 936 {
 937         struct pci_pbm_info *pbm;
 938         int err, i;
 939
 940         if (devhandle & 0x40)
 941                 pbm = &p->pbm_B;
 942         else
 943                 pbm = &p->pbm_A;
 944
 945         pbm->parent = p;
 946         pbm->prom_node = prom_node;
 947         pbm->pci_first_slot = 1;
 948
 949         pbm->devhandle = devhandle;
 950
 951         sprintf(pbm->name, "SUN4V-PCI%d PBM%c",
 952                 p->index, (pbm == &p->pbm_A ? 'A' : 'B'));
 953
 954         printk("%s: devhandle[%x]\n", pbm->name, pbm->devhandle);
 955
 956         prom_getstring(prom_node, "name",
 957                        pbm->prom_name, sizeof(pbm->prom_name));
 958
 959         err = prom_getproperty(prom_node, "ranges",
 960                                (char *) pbm->pbm_ranges,
 961                                sizeof(pbm->pbm_ranges));
 962         if (err == 0 || err == -1) {
 963                 prom_printf("%s: Fatal error, no ranges property.\n",
 964                             pbm->name);
 965                 prom_halt();
 966         }
 967
 968         pbm->num_pbm_ranges =
 969                 (err / sizeof(struct linux_prom_pci_ranges));
 970
 971         /* Mask out the top 8 bits of the ranges, leaving the real
 972          * physical address.
 973          */
 974         for (i = 0; i < pbm->num_pbm_ranges; i++)
 975                 pbm->pbm_ranges[i].parent_phys_hi &= 0x0fffffff;
 976
 977         pci_sun4v_determine_mem_io_space(pbm);
 978         pbm_register_toplevel_resources(p, pbm);
 979
 980         err = prom_getproperty(prom_node, "interrupt-map",
 981                                (char *)pbm->pbm_intmap,
 982                                sizeof(pbm->pbm_intmap));
 983         if (err != -1) {
 984                 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
 985                 err = prom_getproperty(prom_node, "interrupt-map-mask",
 986                                        (char *)&pbm->pbm_intmask,
 987                                        sizeof(pbm->pbm_intmask));
 988                 if (err == -1) {
 989                         prom_printf("%s: Fatal error, no "
 990                                     "interrupt-map-mask.\n", pbm->name);
 991                         prom_halt();
 992                 }
 993         } else {
 994                 pbm->num_pbm_intmap = 0;
 995                 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
 996         }
 997
 998         pci_sun4v_get_bus_range(pbm);
 999         pci_sun4v_iommu_init(pbm);
1000 }
1001
1002 void sun4v_pci_init(int node, char *model_name)
1003 {
1004         struct pci_controller_info *p;
1005         struct pci_iommu *iommu;
1006         struct linux_prom64_registers regs;
1007         unsigned int devhandle;
1008
1009         prom_getproperty(node, "reg", (char *)&regs, sizeof(regs));
1010         devhandle = (regs.phys_addr >> 32UL) & 0x0fffffff;;
1011
1012         for (p = pci_controller_root; p; p = p->next) {
1013                 struct pci_pbm_info *pbm;
1014
1015                 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
1016                         continue;
1017
1018                 pbm = (p->pbm_A.prom_node ?
1019                        &p->pbm_A :
1020                        &p->pbm_B);
1021
1022                 if (pbm->devhandle == (devhandle ^ 0x40)) {
1023                         pci_sun4v_pbm_init(p, node, devhandle);
1024                         return;
1025                 }
1026         }
1027
1028         p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1029         if (!p) {
1030                 prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
1031                 prom_halt();
1032         }
1033         memset(p, 0, sizeof(*p));
1034
1035         iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1036         if (!iommu) {
1037                 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1038                 prom_halt();
1039         }
1040         memset(iommu, 0, sizeof(*iommu));
1041         p->pbm_A.iommu = iommu;
1042
1043         iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1044         if (!iommu) {
1045                 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1046                 prom_halt();
1047         }
1048         memset(iommu, 0, sizeof(*iommu));
1049         p->pbm_B.iommu = iommu;
1050
1051         p->next = pci_controller_root;
1052         pci_controller_root = p;
1053
1054         p->index = pci_num_controllers++;
1055         p->pbms_same_domain = 0;
1056
1057         p->scan_bus = pci_sun4v_scan_bus;
1058         p->irq_build = pci_sun4v_irq_build;
1059         p->base_address_update = pci_sun4v_base_address_update;
1060         p->resource_adjust = pci_sun4v_resource_adjust;
1061         p->pci_ops = &pci_sun4v_ops;
1062
1063         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
1064          * for memory space.
1065          */
1066         pci_memspace_mask = 0x7fffffffUL;
1067
1068         pci_sun4v_pbm_init(p, node, devhandle);
1069 }