1 /* pci_sun4v.c: SUN4V specific PCI controller support.
3 * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
6 #include <linux/kernel.h>
7 #include <linux/types.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/log2.h>
17 #include <asm/iommu.h>
20 #include <asm/pstate.h>
21 #include <asm/oplib.h>
22 #include <asm/hypervisor.h>
26 #include "iommu_common.h"
28 #include "pci_sun4v.h"
30 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
33 struct pci_dev *pdev; /* Device mapping is for. */
34 unsigned long prot; /* IOMMU page protections */
35 unsigned long entry; /* Index into IOTSB. */
36 u64 *pglist; /* List of physical pages */
37 unsigned long npages; /* Number of pages in list. */
40 static DEFINE_PER_CPU(struct iommu_batch, pci_iommu_batch);
42 /* Interrupts must be disabled. */
43 static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry)
45 struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
53 /* Interrupts must be disabled. */
54 static long pci_iommu_batch_flush(struct iommu_batch *p)
56 struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
57 unsigned long devhandle = pbm->devhandle;
58 unsigned long prot = p->prot;
59 unsigned long entry = p->entry;
60 u64 *pglist = p->pglist;
61 unsigned long npages = p->npages;
66 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
67 npages, prot, __pa(pglist));
68 if (unlikely(num < 0)) {
69 if (printk_ratelimit())
70 printk("pci_iommu_batch_flush: IOMMU map of "
71 "[%08lx:%08lx:%lx:%lx:%lx] failed with "
73 devhandle, HV_PCI_TSBID(0, entry),
74 npages, prot, __pa(pglist), num);
89 /* Interrupts must be disabled. */
90 static inline long pci_iommu_batch_add(u64 phys_page)
92 struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
94 BUG_ON(p->npages >= PGLIST_NENTS);
96 p->pglist[p->npages++] = phys_page;
97 if (p->npages == PGLIST_NENTS)
98 return pci_iommu_batch_flush(p);
103 /* Interrupts must be disabled. */
104 static inline long pci_iommu_batch_end(void)
106 struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
108 BUG_ON(p->npages >= PGLIST_NENTS);
110 return pci_iommu_batch_flush(p);
113 static long pci_arena_alloc(struct iommu_arena *arena, unsigned long npages)
115 unsigned long n, i, start, end, limit;
118 limit = arena->limit;
123 n = find_next_zero_bit(arena->map, limit, start);
125 if (unlikely(end >= limit)) {
126 if (likely(pass < 1)) {
132 /* Scanned the whole thing, give up. */
137 for (i = n; i < end; i++) {
138 if (test_bit(i, arena->map)) {
144 for (i = n; i < end; i++)
145 __set_bit(i, arena->map);
152 static void pci_arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
156 for (i = base; i < (base + npages); i++)
157 __clear_bit(i, arena->map);
160 static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
163 unsigned long flags, order, first_page, npages, n;
167 size = IO_PAGE_ALIGN(size);
168 order = get_order(size);
169 if (unlikely(order >= MAX_ORDER))
172 npages = size >> IO_PAGE_SHIFT;
174 first_page = __get_free_pages(gfp, order);
175 if (unlikely(first_page == 0UL))
178 memset((char *)first_page, 0, PAGE_SIZE << order);
180 iommu = pdev->dev.archdata.iommu;
182 spin_lock_irqsave(&iommu->lock, flags);
183 entry = pci_arena_alloc(&iommu->arena, npages);
184 spin_unlock_irqrestore(&iommu->lock, flags);
186 if (unlikely(entry < 0L))
187 goto arena_alloc_fail;
189 *dma_addrp = (iommu->page_table_map_base +
190 (entry << IO_PAGE_SHIFT));
191 ret = (void *) first_page;
192 first_page = __pa(first_page);
194 local_irq_save(flags);
196 pci_iommu_batch_start(pdev,
197 (HV_PCI_MAP_ATTR_READ |
198 HV_PCI_MAP_ATTR_WRITE),
201 for (n = 0; n < npages; n++) {
202 long err = pci_iommu_batch_add(first_page + (n * PAGE_SIZE));
203 if (unlikely(err < 0L))
207 if (unlikely(pci_iommu_batch_end() < 0L))
210 local_irq_restore(flags);
215 /* Interrupts are disabled. */
216 spin_lock(&iommu->lock);
217 pci_arena_free(&iommu->arena, entry, npages);
218 spin_unlock_irqrestore(&iommu->lock, flags);
221 free_pages(first_page, order);
225 static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
227 struct pci_pbm_info *pbm;
229 unsigned long flags, order, npages, entry;
232 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
233 iommu = pdev->dev.archdata.iommu;
234 pbm = pdev->dev.archdata.host_controller;
235 devhandle = pbm->devhandle;
236 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
238 spin_lock_irqsave(&iommu->lock, flags);
240 pci_arena_free(&iommu->arena, entry, npages);
245 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
249 } while (npages != 0);
251 spin_unlock_irqrestore(&iommu->lock, flags);
253 order = get_order(size);
255 free_pages((unsigned long)cpu, order);
258 static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
261 unsigned long flags, npages, oaddr;
262 unsigned long i, base_paddr;
267 iommu = pdev->dev.archdata.iommu;
269 if (unlikely(direction == PCI_DMA_NONE))
272 oaddr = (unsigned long)ptr;
273 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
274 npages >>= IO_PAGE_SHIFT;
276 spin_lock_irqsave(&iommu->lock, flags);
277 entry = pci_arena_alloc(&iommu->arena, npages);
278 spin_unlock_irqrestore(&iommu->lock, flags);
280 if (unlikely(entry < 0L))
283 bus_addr = (iommu->page_table_map_base +
284 (entry << IO_PAGE_SHIFT));
285 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
286 base_paddr = __pa(oaddr & IO_PAGE_MASK);
287 prot = HV_PCI_MAP_ATTR_READ;
288 if (direction != PCI_DMA_TODEVICE)
289 prot |= HV_PCI_MAP_ATTR_WRITE;
291 local_irq_save(flags);
293 pci_iommu_batch_start(pdev, prot, entry);
295 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
296 long err = pci_iommu_batch_add(base_paddr);
297 if (unlikely(err < 0L))
300 if (unlikely(pci_iommu_batch_end() < 0L))
303 local_irq_restore(flags);
308 if (printk_ratelimit())
310 return PCI_DMA_ERROR_CODE;
313 /* Interrupts are disabled. */
314 spin_lock(&iommu->lock);
315 pci_arena_free(&iommu->arena, entry, npages);
316 spin_unlock_irqrestore(&iommu->lock, flags);
318 return PCI_DMA_ERROR_CODE;
321 static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
323 struct pci_pbm_info *pbm;
325 unsigned long flags, npages;
329 if (unlikely(direction == PCI_DMA_NONE)) {
330 if (printk_ratelimit())
335 iommu = pdev->dev.archdata.iommu;
336 pbm = pdev->dev.archdata.host_controller;
337 devhandle = pbm->devhandle;
339 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
340 npages >>= IO_PAGE_SHIFT;
341 bus_addr &= IO_PAGE_MASK;
343 spin_lock_irqsave(&iommu->lock, flags);
345 entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
346 pci_arena_free(&iommu->arena, entry, npages);
351 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
355 } while (npages != 0);
357 spin_unlock_irqrestore(&iommu->lock, flags);
360 #define SG_ENT_PHYS_ADDRESS(SG) \
361 (__pa(page_address((SG)->page)) + (SG)->offset)
363 static inline long fill_sg(long entry, struct pci_dev *pdev,
364 struct scatterlist *sg,
365 int nused, int nelems, unsigned long prot)
367 struct scatterlist *dma_sg = sg;
368 struct scatterlist *sg_end = sg + nelems;
372 local_irq_save(flags);
374 pci_iommu_batch_start(pdev, prot, entry);
376 for (i = 0; i < nused; i++) {
377 unsigned long pteval = ~0UL;
380 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
382 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
384 unsigned long offset;
387 /* If we are here, we know we have at least one
388 * more page to map. So walk forward until we
389 * hit a page crossing, and begin creating new
390 * mappings from that spot.
395 tmp = SG_ENT_PHYS_ADDRESS(sg);
397 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
398 pteval = tmp & IO_PAGE_MASK;
399 offset = tmp & (IO_PAGE_SIZE - 1UL);
402 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
403 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
405 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
411 pteval = (pteval & IOPTE_PAGE);
415 err = pci_iommu_batch_add(pteval);
416 if (unlikely(err < 0L))
417 goto iommu_map_failed;
419 pteval += IO_PAGE_SIZE;
420 len -= (IO_PAGE_SIZE - offset);
425 pteval = (pteval & IOPTE_PAGE) + len;
428 /* Skip over any tail mappings we've fully mapped,
429 * adjusting pteval along the way. Stop when we
430 * detect a page crossing event.
432 while (sg < sg_end &&
433 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
434 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
436 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
437 pteval += sg->length;
440 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
442 } while (dma_npages != 0);
446 if (unlikely(pci_iommu_batch_end() < 0L))
447 goto iommu_map_failed;
449 local_irq_restore(flags);
453 local_irq_restore(flags);
457 static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
460 unsigned long flags, npages, prot;
462 struct scatterlist *sgtmp;
466 /* Fast path single entry scatterlists. */
468 sglist->dma_address =
469 pci_4v_map_single(pdev,
470 (page_address(sglist->page) + sglist->offset),
471 sglist->length, direction);
472 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
474 sglist->dma_length = sglist->length;
478 iommu = pdev->dev.archdata.iommu;
480 if (unlikely(direction == PCI_DMA_NONE))
483 /* Step 1: Prepare scatter list. */
484 npages = prepare_sg(sglist, nelems);
486 /* Step 2: Allocate a cluster and context, if necessary. */
487 spin_lock_irqsave(&iommu->lock, flags);
488 entry = pci_arena_alloc(&iommu->arena, npages);
489 spin_unlock_irqrestore(&iommu->lock, flags);
491 if (unlikely(entry < 0L))
494 dma_base = iommu->page_table_map_base +
495 (entry << IO_PAGE_SHIFT);
497 /* Step 3: Normalize DMA addresses. */
501 while (used && sgtmp->dma_length) {
502 sgtmp->dma_address += dma_base;
506 used = nelems - used;
508 /* Step 4: Create the mappings. */
509 prot = HV_PCI_MAP_ATTR_READ;
510 if (direction != PCI_DMA_TODEVICE)
511 prot |= HV_PCI_MAP_ATTR_WRITE;
513 err = fill_sg(entry, pdev, sglist, used, nelems, prot);
514 if (unlikely(err < 0L))
515 goto iommu_map_failed;
520 if (printk_ratelimit())
525 spin_lock_irqsave(&iommu->lock, flags);
526 pci_arena_free(&iommu->arena, entry, npages);
527 spin_unlock_irqrestore(&iommu->lock, flags);
532 static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
534 struct pci_pbm_info *pbm;
536 unsigned long flags, i, npages;
538 u32 devhandle, bus_addr;
540 if (unlikely(direction == PCI_DMA_NONE)) {
541 if (printk_ratelimit())
545 iommu = pdev->dev.archdata.iommu;
546 pbm = pdev->dev.archdata.host_controller;
547 devhandle = pbm->devhandle;
549 bus_addr = sglist->dma_address & IO_PAGE_MASK;
551 for (i = 1; i < nelems; i++)
552 if (sglist[i].dma_length == 0)
555 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
556 bus_addr) >> IO_PAGE_SHIFT;
558 entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
560 spin_lock_irqsave(&iommu->lock, flags);
562 pci_arena_free(&iommu->arena, entry, npages);
567 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
571 } while (npages != 0);
573 spin_unlock_irqrestore(&iommu->lock, flags);
576 static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
578 /* Nothing to do... */
581 static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
583 /* Nothing to do... */
586 const struct pci_iommu_ops pci_sun4v_iommu_ops = {
587 .alloc_consistent = pci_4v_alloc_consistent,
588 .free_consistent = pci_4v_free_consistent,
589 .map_single = pci_4v_map_single,
590 .unmap_single = pci_4v_unmap_single,
591 .map_sg = pci_4v_map_sg,
592 .unmap_sg = pci_4v_unmap_sg,
593 .dma_sync_single_for_cpu = pci_4v_dma_sync_single_for_cpu,
594 .dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu,
597 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
599 struct property *prop;
600 struct device_node *dp;
603 prop = of_find_property(dp, "66mhz-capable", NULL);
604 pbm->is_66mhz_capable = (prop != NULL);
605 pbm->pci_bus = pci_scan_one_pbm(pbm);
607 /* XXX register error interrupt handlers XXX */
610 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
613 struct iommu_arena *arena = &iommu->arena;
614 unsigned long i, cnt = 0;
617 devhandle = pbm->devhandle;
618 for (i = 0; i < arena->limit; i++) {
619 unsigned long ret, io_attrs, ra;
621 ret = pci_sun4v_iommu_getmap(devhandle,
625 if (page_in_phys_avail(ra)) {
626 pci_sun4v_iommu_demap(devhandle,
627 HV_PCI_TSBID(0, i), 1);
630 __set_bit(i, arena->map);
638 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
640 struct iommu *iommu = pbm->iommu;
641 struct property *prop;
642 unsigned long num_tsb_entries, sz, tsbsize;
643 u32 vdma[2], dma_mask, dma_offset;
645 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
647 u32 *val = prop->value;
652 /* No property, use default values. */
653 vdma[0] = 0x80000000;
654 vdma[1] = 0x80000000;
657 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
658 prom_printf("PCI-SUN4V: strange virtual-dma[%08x:%08x].\n",
663 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
664 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
665 tsbsize = num_tsb_entries * sizeof(iopte_t);
667 dma_offset = vdma[0];
669 /* Setup initial software IOMMU state. */
670 spin_lock_init(&iommu->lock);
671 iommu->ctx_lowest_free = 1;
672 iommu->page_table_map_base = dma_offset;
673 iommu->dma_addr_mask = dma_mask;
675 /* Allocate and initialize the free area map. */
676 sz = (num_tsb_entries + 7) / 8;
677 sz = (sz + 7UL) & ~7UL;
678 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
679 if (!iommu->arena.map) {
680 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
683 iommu->arena.limit = num_tsb_entries;
685 sz = probe_existing_entries(pbm, iommu);
687 printk("%s: Imported %lu TSB entries from OBP\n",
691 #ifdef CONFIG_PCI_MSI
692 struct pci_sun4v_msiq_entry {
694 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
695 #define MSIQ_VERSION_SHIFT 32
696 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
697 #define MSIQ_TYPE_SHIFT 0
698 #define MSIQ_TYPE_NONE 0x00
699 #define MSIQ_TYPE_MSG 0x01
700 #define MSIQ_TYPE_MSI32 0x02
701 #define MSIQ_TYPE_MSI64 0x03
702 #define MSIQ_TYPE_INTX 0x08
703 #define MSIQ_TYPE_NONE2 0xff
708 u64 req_id; /* bus/device/func */
709 #define MSIQ_REQID_BUS_MASK 0xff00UL
710 #define MSIQ_REQID_BUS_SHIFT 8
711 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
712 #define MSIQ_REQID_DEVICE_SHIFT 3
713 #define MSIQ_REQID_FUNC_MASK 0x0007UL
714 #define MSIQ_REQID_FUNC_SHIFT 0
718 /* The format of this value is message type dependent.
719 * For MSI bits 15:0 are the data from the MSI packet.
720 * For MSI-X bits 31:0 are the data from the MSI packet.
721 * For MSG, the message code and message routing code where:
722 * bits 39:32 is the bus/device/fn of the msg target-id
723 * bits 18:16 is the message routing code
724 * bits 7:0 is the message code
725 * For INTx the low order 2-bits are:
736 /* For now this just runs as a pre-handler for the real interrupt handler.
737 * So we just walk through the queue and ACK all the entries, update the
738 * head pointer, and return.
740 * In the longer term it would be nice to do something more integrated
741 * wherein we can pass in some of this MSI info to the drivers. This
742 * would be most useful for PCIe fabric error messages, although we could
743 * invoke those directly from the loop here in order to pass the info around.
745 static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2)
747 struct pci_pbm_info *pbm = data1;
748 struct pci_sun4v_msiq_entry *base, *ep;
749 unsigned long msiqid, orig_head, head, type, err;
751 msiqid = (unsigned long) data2;
754 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head);
758 if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))))
761 head /= sizeof(struct pci_sun4v_msiq_entry);
763 base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
764 (pbm->msiq_ent_count *
765 sizeof(struct pci_sun4v_msiq_entry))));
767 while ((ep->version_type & MSIQ_TYPE_MASK) != 0) {
768 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
769 if (unlikely(type != MSIQ_TYPE_MSI32 &&
770 type != MSIQ_TYPE_MSI64))
773 pci_sun4v_msi_setstate(pbm->devhandle,
774 ep->msi_data /* msi_num */,
777 /* Clear the entry. */
778 ep->version_type &= ~MSIQ_TYPE_MASK;
780 /* Go to next entry in ring. */
782 if (head >= pbm->msiq_ent_count)
787 if (likely(head != orig_head)) {
788 /* ACK entries by updating head pointer. */
789 head *= sizeof(struct pci_sun4v_msiq_entry);
790 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
797 printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err);
801 printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err);
804 printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n",
805 pbm->devhandle, msiqid, head);
809 printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n",
810 head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry));
814 printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
818 static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
820 unsigned long size, bits_per_ulong;
822 bits_per_ulong = sizeof(unsigned long) * 8;
823 size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
825 BUG_ON(size % sizeof(unsigned long));
827 pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
828 if (!pbm->msi_bitmap)
834 static void msi_bitmap_free(struct pci_pbm_info *pbm)
836 kfree(pbm->msi_bitmap);
837 pbm->msi_bitmap = NULL;
840 static int msi_queue_alloc(struct pci_pbm_info *pbm)
842 unsigned long q_size, alloc_size, pages, order;
845 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
846 alloc_size = (pbm->msiq_num * q_size);
847 order = get_order(alloc_size);
848 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
850 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
854 memset((char *)pages, 0, PAGE_SIZE << order);
855 pbm->msi_queues = (void *) pages;
857 for (i = 0; i < pbm->msiq_num; i++) {
858 unsigned long err, base = __pa(pages + (i * q_size));
859 unsigned long ret1, ret2;
861 err = pci_sun4v_msiq_conf(pbm->devhandle,
863 base, pbm->msiq_ent_count);
865 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
870 err = pci_sun4v_msiq_info(pbm->devhandle,
874 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
878 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
879 printk(KERN_ERR "MSI: Bogus qconf "
880 "expected[%lx:%x] got[%lx:%lx]\n",
881 base, pbm->msiq_ent_count,
890 free_pages(pages, order);
895 static int alloc_msi(struct pci_pbm_info *pbm)
899 for (i = 0; i < pbm->msi_num; i++) {
900 if (!test_and_set_bit(i, pbm->msi_bitmap))
901 return i + pbm->msi_first;
907 static void free_msi(struct pci_pbm_info *pbm, int msi_num)
909 msi_num -= pbm->msi_first;
910 clear_bit(msi_num, pbm->msi_bitmap);
913 static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
914 struct pci_dev *pdev,
915 struct msi_desc *entry)
917 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
918 unsigned long devino, msiqid;
924 msi_num = alloc_msi(pbm);
928 devino = sun4v_build_msi(pbm->devhandle, virt_irq_p,
929 pbm->msiq_first_devino,
930 (pbm->msiq_first_devino +
936 msiqid = ((devino - pbm->msiq_first_devino) +
940 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
944 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
947 if (pci_sun4v_msi_setmsiq(pbm->devhandle,
949 (entry->msi_attrib.is_64 ?
950 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
953 if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE))
956 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
959 pdev->dev.archdata.msi_num = msi_num;
961 if (entry->msi_attrib.is_64) {
962 msg.address_hi = pbm->msi64_start >> 32;
963 msg.address_lo = pbm->msi64_start & 0xffffffff;
966 msg.address_lo = pbm->msi32_start;
970 set_irq_msi(*virt_irq_p, entry);
971 write_msi_msg(*virt_irq_p, &msg);
973 irq_install_pre_handler(*virt_irq_p,
974 pci_sun4v_msi_prehandler,
975 pbm, (void *) msiqid);
980 free_msi(pbm, msi_num);
981 sun4v_destroy_msi(*virt_irq_p);
987 static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
988 struct pci_dev *pdev)
990 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
991 unsigned long msiqid, err;
992 unsigned int msi_num;
994 msi_num = pdev->dev.archdata.msi_num;
995 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
997 printk(KERN_ERR "%s: getmsiq gives error %lu\n",
1002 pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID);
1003 pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID);
1005 free_msi(pbm, msi_num);
1007 /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ
1010 sun4v_destroy_msi(virt_irq);
1013 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1018 val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
1019 if (!val || len != 4)
1021 pbm->msiq_num = *val;
1022 if (pbm->msiq_num) {
1023 const struct msiq_prop {
1028 const struct msi_range_prop {
1032 const struct addr_range_prop {
1041 val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
1042 if (!val || len != 4)
1045 pbm->msiq_ent_count = *val;
1047 mqp = of_get_property(pbm->prom_node,
1048 "msi-eq-to-devino", &len);
1049 if (!mqp || len != sizeof(struct msiq_prop))
1052 pbm->msiq_first = mqp->first_msiq;
1053 pbm->msiq_first_devino = mqp->first_devino;
1055 val = of_get_property(pbm->prom_node, "#msi", &len);
1056 if (!val || len != 4)
1058 pbm->msi_num = *val;
1060 mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
1061 if (!mrng || len != sizeof(struct msi_range_prop))
1063 pbm->msi_first = mrng->first_msi;
1065 val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
1066 if (!val || len != 4)
1068 pbm->msi_data_mask = *val;
1070 val = of_get_property(pbm->prom_node, "msix-data-width", &len);
1071 if (!val || len != 4)
1073 pbm->msix_data_width = *val;
1075 arng = of_get_property(pbm->prom_node, "msi-address-ranges",
1077 if (!arng || len != sizeof(struct addr_range_prop))
1079 pbm->msi32_start = ((u64)arng->msi32_high << 32) |
1080 (u64) arng->msi32_low;
1081 pbm->msi64_start = ((u64)arng->msi64_high << 32) |
1082 (u64) arng->msi64_low;
1083 pbm->msi32_len = arng->msi32_len;
1084 pbm->msi64_len = arng->msi64_len;
1086 if (msi_bitmap_alloc(pbm))
1089 if (msi_queue_alloc(pbm)) {
1090 msi_bitmap_free(pbm);
1094 printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
1097 pbm->msiq_first, pbm->msiq_num,
1098 pbm->msiq_ent_count,
1099 pbm->msiq_first_devino);
1100 printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
1103 pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
1104 pbm->msix_data_width);
1105 printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
1106 "addr64[0x%lx:0x%x]\n",
1108 pbm->msi32_start, pbm->msi32_len,
1109 pbm->msi64_start, pbm->msi64_len);
1110 printk(KERN_INFO "%s: MSI queues at RA [%p]\n",
1114 pbm->setup_msi_irq = pci_sun4v_setup_msi_irq;
1115 pbm->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
1121 printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
1123 #else /* CONFIG_PCI_MSI */
1124 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1127 #endif /* !(CONFIG_PCI_MSI) */
1129 static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
1131 struct pci_pbm_info *pbm;
1133 if (devhandle & 0x40)
1138 pbm->next = pci_pbm_root;
1141 pbm->scan_bus = pci_sun4v_scan_bus;
1142 pbm->pci_ops = &sun4v_pci_ops;
1143 pbm->config_space_reg_bits = 12;
1145 pbm->index = pci_num_pbms++;
1148 pbm->prom_node = dp;
1150 pbm->devhandle = devhandle;
1152 pbm->name = dp->full_name;
1154 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1156 pci_determine_mem_io_space(pbm);
1158 pci_get_pbm_props(pbm);
1159 pci_sun4v_iommu_init(pbm);
1160 pci_sun4v_msi_init(pbm);
1163 void sun4v_pci_init(struct device_node *dp, char *model_name)
1165 struct pci_controller_info *p;
1166 struct pci_pbm_info *pbm;
1167 struct iommu *iommu;
1168 struct property *prop;
1169 struct linux_prom64_registers *regs;
1173 prop = of_find_property(dp, "reg", NULL);
1176 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1178 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1179 if (pbm->devhandle == (devhandle ^ 0x40)) {
1180 pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
1185 for_each_possible_cpu(i) {
1186 unsigned long page = get_zeroed_page(GFP_ATOMIC);
1189 goto fatal_memory_error;
1191 per_cpu(pci_iommu_batch, i).pglist = (u64 *) page;
1194 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1196 goto fatal_memory_error;
1198 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1200 goto fatal_memory_error;
1202 p->pbm_A.iommu = iommu;
1204 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1206 goto fatal_memory_error;
1208 p->pbm_B.iommu = iommu;
1210 /* Like PSYCHO and SCHIZO we have a 2GB aligned area
1213 pci_memspace_mask = 0x7fffffffUL;
1215 pci_sun4v_pbm_init(p, dp, devhandle);
1219 prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");