1 /* psycho_common.c: Code common to PSYCHO and derivative PCI controllers.
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
5 #include <linux/kernel.h>
6 #include <linux/interrupt.h>
11 #include "iommu_common.h"
12 #include "psycho_common.h"
14 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL
15 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL
16 #define PSYCHO_STCERR_READ 0x0000000000000001UL
17 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL
18 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL
19 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL
20 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL
21 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL
22 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL
23 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL
24 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL
25 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL
26 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL
28 static DEFINE_SPINLOCK(stc_buf_lock);
29 static unsigned long stc_error_buf[128];
30 static unsigned long stc_tag_buf[16];
31 static unsigned long stc_line_buf[16];
33 static void psycho_check_stc_error(struct pci_pbm_info *pbm)
35 unsigned long err_base, tag_base, line_base;
36 struct strbuf *strbuf = &pbm->stc;
40 if (!strbuf->strbuf_control)
43 err_base = strbuf->strbuf_err_stat;
44 tag_base = strbuf->strbuf_tag_diag;
45 line_base = strbuf->strbuf_line_diag;
47 spin_lock(&stc_buf_lock);
49 /* This is __REALLY__ dangerous. When we put the streaming
50 * buffer into diagnostic mode to probe it's tags and error
51 * status, we _must_ clear all of the line tag valid bits
52 * before re-enabling the streaming buffer. If any dirty data
53 * lives in the STC when we do this, we will end up
54 * invalidating it before it has a chance to reach main
57 control = upa_readq(strbuf->strbuf_control);
58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control);
59 for (i = 0; i < 128; i++) {
62 val = upa_readq(err_base + (i * 8UL));
63 upa_writeq(0UL, err_base + (i * 8UL));
64 stc_error_buf[i] = val;
66 for (i = 0; i < 16; i++) {
67 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
68 stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
69 upa_writeq(0UL, tag_base + (i * 8UL));
70 upa_writeq(0UL, line_base + (i * 8UL));
73 /* OK, state is logged, exit diagnostic mode. */
74 upa_writeq(control, strbuf->strbuf_control);
76 for (i = 0; i < 16; i++) {
77 int j, saw_error, first, last;
82 for (j = first; j < last; j++) {
83 u64 errval = stc_error_buf[j];
86 printk(KERN_ERR "%s: STC_ERR(%d)[wr(%d)"
90 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
91 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
95 u64 tagval = stc_tag_buf[i];
96 u64 lineval = stc_line_buf[i];
97 printk(KERN_ERR "%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)"
101 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
102 (tagval & PSYCHO_STCTAG_VPN),
103 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
104 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
105 printk(KERN_ERR "%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)"
106 "LADDR(%lx)EP(%lx)V(%d)FOFN(%d)]\n",
109 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
110 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
111 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
112 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
113 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
114 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
118 spin_unlock(&stc_buf_lock);
121 #define PSYCHO_IOMMU_TAG 0xa580UL
122 #define PSYCHO_IOMMU_DATA 0xa600UL
124 static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm,
129 for (i = 0; i < 16; i++) {
130 unsigned long base = pbm->controller_regs;
131 unsigned long off = i * 8UL;
133 tag[i] = upa_readq(base + PSYCHO_IOMMU_TAG+off);
134 data[i] = upa_readq(base + PSYCHO_IOMMU_DATA+off);
136 /* Now clear out the entry. */
137 upa_writeq(0, base + PSYCHO_IOMMU_TAG + off);
138 upa_writeq(0, base + PSYCHO_IOMMU_DATA + off);
142 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
143 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
144 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
145 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
146 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
147 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
148 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
149 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
150 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
152 static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm,
157 for (i = 0; i < 16; i++) {
158 u64 tag_val, data_val;
159 const char *type_str;
161 if (!(tag_val & PSYCHO_IOMMU_TAG_ERR))
165 switch((tag_val & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
167 type_str = "Protection Error";
170 type_str = "Invalid Error";
173 type_str = "TimeOut Error";
177 type_str = "ECC Error";
181 printk(KERN_ERR "%s: IOMMU TAG(%d)[error(%s) wr(%d) "
182 "str(%d) sz(%dK) vpg(%08lx)]\n",
183 pbm->name, i, type_str,
184 ((tag_val & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
185 ((tag_val & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
186 ((tag_val & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
187 (tag_val & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
188 printk(KERN_ERR "%s: IOMMU DATA(%d)[valid(%d) cache(%d) "
191 ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
192 ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
193 (data_val & PSYCHO_IOMMU_DATA_PPAGE)<<IOMMU_PAGE_SHIFT);
197 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL
198 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL
200 void psycho_check_iommu_error(struct pci_pbm_info *pbm,
203 enum psycho_error_type type)
205 u64 control, iommu_tag[16], iommu_data[16];
206 struct iommu *iommu = pbm->iommu;
209 spin_lock_irqsave(&iommu->lock, flags);
210 control = upa_readq(iommu->iommu_control);
211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
212 const char *type_str;
214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
215 upa_writeq(control, iommu->iommu_control);
217 switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
219 type_str = "Protection Error";
222 type_str = "Invalid Error";
225 type_str = "TimeOut Error";
229 type_str = "ECC Error";
232 printk(KERN_ERR "%s: IOMMU Error, type[%s]\n",
233 pbm->name, type_str);
235 /* It is very possible for another DVMA to occur while
236 * we do this probe, and corrupt the system further.
237 * But we are so screwed at this point that we are
238 * likely to crash hard anyways, so get as much
239 * diagnostic information to the console as we can.
241 psycho_record_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
242 psycho_dump_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
244 psycho_check_stc_error(pbm);
245 spin_unlock_irqrestore(&iommu->lock, flags);
248 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL
249 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL
251 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
253 irqreturn_t ret = IRQ_NONE;
254 u64 csr, csr_error_bits;
257 csr = upa_readq(pbm->pci_csr);
258 csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
259 if (csr_error_bits) {
260 /* Clear the errors. */
261 upa_writeq(csr, pbm->pci_csr);
264 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
265 printk(KERN_ERR "%s: PCI streaming byte hole "
266 "error asserted.\n", pbm->name);
267 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
268 printk(KERN_ERR "%s: PCI SERR signal asserted.\n",
272 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
273 if (stat & (PCI_STATUS_PARITY |
274 PCI_STATUS_SIG_TARGET_ABORT |
275 PCI_STATUS_REC_TARGET_ABORT |
276 PCI_STATUS_REC_MASTER_ABORT |
277 PCI_STATUS_SIG_SYSTEM_ERROR)) {
278 printk(KERN_ERR "%s: PCI bus error, PCI_STATUS[%04x]\n",
280 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
286 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL
287 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL
288 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL
289 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL
290 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL
291 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL
292 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL
293 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL
294 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL
295 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL
296 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL
297 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL
298 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL
299 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL
301 irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
303 struct pci_pbm_info *pbm = dev_id;
304 u64 afsr, afar, error_bits;
307 afsr = upa_readq(pbm->pci_afsr);
308 afar = upa_readq(pbm->pci_afar);
310 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
311 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
312 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
313 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
315 return psycho_pcierr_intr_other(pbm);
316 upa_writeq(error_bits, pbm->pci_afsr);
317 printk(KERN_ERR "%s: PCI Error, primary error type[%s]\n",
319 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
321 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
323 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
324 "Excessive Retries" :
325 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
326 "Parity Error" : "???"))))));
327 printk(KERN_ERR "%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
329 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
330 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
331 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
332 printk(KERN_ERR "%s: PCI AFAR [%016lx]\n", pbm->name, afar);
333 printk(KERN_ERR "%s: PCI Secondary errors [", pbm->name);
335 if (afsr & PSYCHO_PCIAFSR_SMA) {
337 printk("(Master Abort)");
339 if (afsr & PSYCHO_PCIAFSR_STA) {
341 printk("(Target Abort)");
343 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
345 printk("(Excessive Retries)");
347 if (afsr & PSYCHO_PCIAFSR_SPERR) {
349 printk("(Parity Error)");
355 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
356 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
357 pci_scan_for_target_abort(pbm, pbm->pci_bus);
359 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
360 pci_scan_for_master_abort(pbm, pbm->pci_bus);
362 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
363 pci_scan_for_parity_error(pbm, pbm->pci_bus);
368 static void psycho_iommu_flush(struct pci_pbm_info *pbm)
372 for (i = 0; i < 16; i++) {
373 unsigned long off = i * 8;
375 upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_TAG + off);
376 upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_DATA + off);
380 #define PSYCHO_IOMMU_CONTROL 0x0200UL
381 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL
382 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL
383 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL
384 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL
385 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL
386 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL
387 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL
388 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL
389 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL
390 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL
391 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL
392 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL
393 #define PSYCHO_IOMMU_FLUSH 0x0210UL
394 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
396 int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
397 u32 dvma_offset, u32 dma_mask,
398 unsigned long write_complete_offset)
400 struct iommu *iommu = pbm->iommu;
404 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
405 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
406 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
407 iommu->iommu_tags = pbm->controller_regs + PSYCHO_IOMMU_TAG;
408 iommu->write_complete_reg = (pbm->controller_regs +
409 write_complete_offset);
411 iommu->iommu_ctxflush = 0;
413 control = upa_readq(iommu->iommu_control);
414 control |= PSYCHO_IOMMU_CTRL_DENAB;
415 upa_writeq(control, iommu->iommu_control);
417 psycho_iommu_flush(pbm);
419 /* Leave diag mode enabled for full-flushing done in pci_iommu.c */
420 err = iommu_table_init(iommu, tsbsize * 1024 * 8,
421 dvma_offset, dma_mask, pbm->numa_node);
425 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
427 control = upa_readq(iommu->iommu_control);
428 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
429 control |= PSYCHO_IOMMU_CTRL_ENAB;
433 control |= PSYCHO_IOMMU_TSBSZ_64K;
436 control |= PSYCHO_IOMMU_TSBSZ_128K;
442 upa_writeq(control, iommu->iommu_control);
448 void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct of_device *op,
449 const char *chip_name, int chip_type)
451 struct device_node *dp = op->node;
453 pbm->name = dp->full_name;
455 pbm->chip_type = chip_type;
456 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
457 pbm->chip_revision = of_getintprop_default(dp, "module-revision#", 0);
459 pbm->pci_ops = &sun4u_pci_ops;
460 pbm->config_space_reg_bits = 8;
461 pbm->index = pci_num_pbms++;
462 pci_get_pbm_props(pbm);
463 pci_determine_mem_io_space(pbm);
465 printk(KERN_INFO "%s: %s PCI Bus Module ver[%x:%x]\n",
466 pbm->name, chip_name,
467 pbm->chip_version, pbm->chip_revision);