1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/atomic.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/cpudata.h>
31 #include <asm/hvtramp.h>
35 #include <asm/irq_regs.h>
37 #include <asm/pgtable.h>
38 #include <asm/oplib.h>
39 #include <asm/uaccess.h>
40 #include <asm/timer.h>
41 #include <asm/starfire.h>
43 #include <asm/sections.h>
45 #include <asm/mdesc.h>
48 extern void calibrate_delay(void);
50 int sparc64_multi_core __read_mostly;
52 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
53 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
54 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly =
55 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
56 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
57 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
59 EXPORT_SYMBOL(cpu_possible_map);
60 EXPORT_SYMBOL(cpu_online_map);
61 EXPORT_SYMBOL(cpu_sibling_map);
62 EXPORT_SYMBOL(cpu_core_map);
64 static cpumask_t smp_commenced_mask;
65 static cpumask_t cpu_callout_map;
67 void smp_info(struct seq_file *m)
71 seq_printf(m, "State:\n");
72 for_each_online_cpu(i)
73 seq_printf(m, "CPU%d:\t\tonline\n", i);
76 void smp_bogo(struct seq_file *m)
80 for_each_online_cpu(i)
82 "Cpu%dClkTck\t: %016lx\n",
83 i, cpu_data(i).clock_tick);
86 extern void setup_sparc64_timer(void);
88 static volatile unsigned long callin_flag = 0;
90 void __devinit smp_callin(void)
92 int cpuid = hard_smp_processor_id();
94 __local_per_cpu_offset = __per_cpu_offset(cpuid);
96 if (tlb_type == hypervisor)
97 sun4v_ktsb_register();
101 setup_sparc64_timer();
103 if (cheetah_pcache_forced_on)
104 cheetah_enable_pcache();
109 __asm__ __volatile__("membar #Sync\n\t"
110 "flush %%g6" : : : "memory");
112 /* Clear this or we will die instantly when we
113 * schedule back to this idler...
115 current_thread_info()->new_child = 0;
117 /* Attach to the address space of init_task. */
118 atomic_inc(&init_mm.mm_count);
119 current->active_mm = &init_mm;
121 while (!cpu_isset(cpuid, smp_commenced_mask))
124 cpu_set(cpuid, cpu_online_map);
126 /* idle thread is expected to have preempt disabled */
132 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
133 panic("SMP bolixed\n");
136 /* This tick register synchronization scheme is taken entirely from
137 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
139 * The only change I've made is to rework it so that the master
140 * initiates the synchonization instead of the slave. -DaveM
144 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
146 #define NUM_ROUNDS 64 /* magic value */
147 #define NUM_ITERS 5 /* likewise */
149 static DEFINE_SPINLOCK(itc_sync_lock);
150 static unsigned long go[SLAVE + 1];
152 #define DEBUG_TICK_SYNC 0
154 static inline long get_delta (long *rt, long *master)
156 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
157 unsigned long tcenter, t0, t1, tm;
160 for (i = 0; i < NUM_ITERS; i++) {
161 t0 = tick_ops->get_tick();
164 while (!(tm = go[SLAVE]))
168 t1 = tick_ops->get_tick();
170 if (t1 - t0 < best_t1 - best_t0)
171 best_t0 = t0, best_t1 = t1, best_tm = tm;
174 *rt = best_t1 - best_t0;
175 *master = best_tm - best_t0;
177 /* average best_t0 and best_t1 without overflow: */
178 tcenter = (best_t0/2 + best_t1/2);
179 if (best_t0 % 2 + best_t1 % 2 == 2)
181 return tcenter - best_tm;
184 void smp_synchronize_tick_client(void)
186 long i, delta, adj, adjust_latency = 0, done = 0;
187 unsigned long flags, rt, master_time_stamp, bound;
190 long rt; /* roundtrip time */
191 long master; /* master's timestamp */
192 long diff; /* difference between midpoint and master's timestamp */
193 long lat; /* estimate of itc adjustment latency */
202 local_irq_save(flags);
204 for (i = 0; i < NUM_ROUNDS; i++) {
205 delta = get_delta(&rt, &master_time_stamp);
207 done = 1; /* let's lock on to this... */
213 adjust_latency += -delta;
214 adj = -delta + adjust_latency/4;
218 tick_ops->add_tick(adj);
222 t[i].master = master_time_stamp;
224 t[i].lat = adjust_latency/4;
228 local_irq_restore(flags);
231 for (i = 0; i < NUM_ROUNDS; i++)
232 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
233 t[i].rt, t[i].master, t[i].diff, t[i].lat);
236 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
237 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
240 static void smp_start_sync_tick_client(int cpu);
242 static void smp_synchronize_one_tick(int cpu)
244 unsigned long flags, i;
248 smp_start_sync_tick_client(cpu);
250 /* wait for client to be ready */
254 /* now let the client proceed into his loop */
258 spin_lock_irqsave(&itc_sync_lock, flags);
260 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
265 go[SLAVE] = tick_ops->get_tick();
269 spin_unlock_irqrestore(&itc_sync_lock, flags);
272 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
273 /* XXX Put this in some common place. XXX */
274 static unsigned long kimage_addr_to_ra(void *p)
276 unsigned long val = (unsigned long) p;
278 return kern_base + (val - KERNBASE);
281 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
283 extern unsigned long sparc64_ttable_tl0;
284 extern unsigned long kern_locked_tte_data;
285 extern int bigkernel;
286 struct hvtramp_descr *hdesc;
287 unsigned long trampoline_ra;
288 struct trap_per_cpu *tb;
289 u64 tte_vaddr, tte_data;
290 unsigned long hv_err;
292 hdesc = kzalloc(sizeof(*hdesc), GFP_KERNEL);
294 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
300 hdesc->num_mappings = (bigkernel ? 2 : 1);
302 tb = &trap_block[cpu];
305 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
306 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
308 hdesc->thread_reg = thread_reg;
310 tte_vaddr = (unsigned long) KERNBASE;
311 tte_data = kern_locked_tte_data;
313 hdesc->maps[0].vaddr = tte_vaddr;
314 hdesc->maps[0].tte = tte_data;
316 tte_vaddr += 0x400000;
317 tte_data += 0x400000;
318 hdesc->maps[1].vaddr = tte_vaddr;
319 hdesc->maps[1].tte = tte_data;
322 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
324 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
325 kimage_addr_to_ra(&sparc64_ttable_tl0),
330 extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load);
332 extern unsigned long sparc64_cpu_startup;
334 /* The OBP cpu startup callback truncates the 3rd arg cookie to
335 * 32-bits (I think) so to be safe we have it read the pointer
336 * contained here so we work on >4GB machines. -DaveM
338 static struct thread_info *cpu_new_thread = NULL;
340 static int __devinit smp_boot_one_cpu(unsigned int cpu)
342 struct trap_per_cpu *tb = &trap_block[cpu];
343 unsigned long entry =
344 (unsigned long)(&sparc64_cpu_startup);
345 unsigned long cookie =
346 (unsigned long)(&cpu_new_thread);
347 struct task_struct *p;
352 cpu_new_thread = task_thread_info(p);
353 cpu_set(cpu, cpu_callout_map);
355 if (tlb_type == hypervisor) {
356 /* Alloc the mondo queues, cpu will load them. */
357 sun4v_init_mondo_queues(0, cpu, 1, 0);
359 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
360 if (ldom_domaining_enabled)
361 ldom_startcpu_cpuid(cpu,
362 (unsigned long) cpu_new_thread);
365 prom_startcpu_cpuid(cpu, entry, cookie);
367 struct device_node *dp = of_find_node_by_cpuid(cpu);
369 prom_startcpu(dp->node, entry, cookie);
372 for (timeout = 0; timeout < 50000; timeout++) {
381 printk("Processor %d is stuck.\n", cpu);
382 cpu_clear(cpu, cpu_callout_map);
385 cpu_new_thread = NULL;
395 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
400 if (this_is_starfire) {
401 /* map to real upaid */
402 cpu = (((cpu & 0x3c) << 1) |
403 ((cpu & 0x40) >> 4) |
407 target = (cpu << 14) | 0x70;
409 /* Ok, this is the real Spitfire Errata #54.
410 * One must read back from a UDB internal register
411 * after writes to the UDB interrupt dispatch, but
412 * before the membar Sync for that write.
413 * So we use the high UDB control register (ASI 0x7f,
414 * ADDR 0x20) for the dummy read. -DaveM
417 __asm__ __volatile__(
418 "wrpr %1, %2, %%pstate\n\t"
419 "stxa %4, [%0] %3\n\t"
420 "stxa %5, [%0+%8] %3\n\t"
422 "stxa %6, [%0+%8] %3\n\t"
424 "stxa %%g0, [%7] %3\n\t"
427 "ldxa [%%g1] 0x7f, %%g0\n\t"
430 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
431 "r" (data0), "r" (data1), "r" (data2), "r" (target),
432 "r" (0x10), "0" (tmp)
435 /* NOTE: PSTATE_IE is still clear. */
438 __asm__ __volatile__("ldxa [%%g0] %1, %0"
440 : "i" (ASI_INTR_DISPATCH_STAT));
442 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
449 } while (result & 0x1);
450 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
453 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
454 smp_processor_id(), result);
461 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
466 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
467 for_each_cpu_mask(i, mask)
468 spitfire_xcall_helper(data0, data1, data2, pstate, i);
471 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
472 * packet, but we have no use for that. However we do take advantage of
473 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
475 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
478 int nack_busy_id, is_jbus, need_more;
480 if (cpus_empty(mask))
483 /* Unfortunately, someone at Sun had the brilliant idea to make the
484 * busy/nack fields hard-coded by ITID number for this Ultra-III
485 * derivative processor.
487 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
488 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
489 (ver >> 32) == __SERRANO_ID);
491 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
495 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
496 : : "r" (pstate), "i" (PSTATE_IE));
498 /* Setup the dispatch data registers. */
499 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
500 "stxa %1, [%4] %6\n\t"
501 "stxa %2, [%5] %6\n\t"
504 : "r" (data0), "r" (data1), "r" (data2),
505 "r" (0x40), "r" (0x50), "r" (0x60),
512 for_each_cpu_mask(i, mask) {
513 u64 target = (i << 14) | 0x70;
516 target |= (nack_busy_id << 24);
517 __asm__ __volatile__(
518 "stxa %%g0, [%0] %1\n\t"
521 : "r" (target), "i" (ASI_INTR_W));
523 if (nack_busy_id == 32) {
530 /* Now, poll for completion. */
535 stuck = 100000 * nack_busy_id;
537 __asm__ __volatile__("ldxa [%%g0] %1, %0"
538 : "=r" (dispatch_stat)
539 : "i" (ASI_INTR_DISPATCH_STAT));
540 if (dispatch_stat == 0UL) {
541 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
543 if (unlikely(need_more)) {
545 for_each_cpu_mask(i, mask) {
557 } while (dispatch_stat & 0x5555555555555555UL);
559 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
562 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
563 /* Busy bits will not clear, continue instead
564 * of freezing up on this cpu.
566 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
567 smp_processor_id(), dispatch_stat);
569 int i, this_busy_nack = 0;
571 /* Delay some random time with interrupts enabled
572 * to prevent deadlock.
574 udelay(2 * nack_busy_id);
576 /* Clear out the mask bits for cpus which did not
579 for_each_cpu_mask(i, mask) {
583 check_mask = (0x2UL << (2*i));
585 check_mask = (0x2UL <<
587 if ((dispatch_stat & check_mask) == 0)
590 if (this_busy_nack == 64)
599 /* Multi-cpu list version. */
600 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
602 struct trap_per_cpu *tb;
605 cpumask_t error_mask;
606 unsigned long flags, status;
607 int cnt, retries, this_cpu, prev_sent, i;
609 if (cpus_empty(mask))
612 /* We have to do this whole thing with interrupts fully disabled.
613 * Otherwise if we send an xcall from interrupt context it will
614 * corrupt both our mondo block and cpu list state.
616 * One consequence of this is that we cannot use timeout mechanisms
617 * that depend upon interrupts being delivered locally. So, for
618 * example, we cannot sample jiffies and expect it to advance.
620 * Fortunately, udelay() uses %stick/%tick so we can use that.
622 local_irq_save(flags);
624 this_cpu = smp_processor_id();
625 tb = &trap_block[this_cpu];
627 mondo = __va(tb->cpu_mondo_block_pa);
633 cpu_list = __va(tb->cpu_list_pa);
635 /* Setup the initial cpu list. */
637 for_each_cpu_mask(i, mask)
640 cpus_clear(error_mask);
644 int forward_progress, n_sent;
646 status = sun4v_cpu_mondo_send(cnt,
648 tb->cpu_mondo_block_pa);
650 /* HV_EOK means all cpus received the xcall, we're done. */
651 if (likely(status == HV_EOK))
654 /* First, see if we made any forward progress.
656 * The hypervisor indicates successful sends by setting
657 * cpu list entries to the value 0xffff.
660 for (i = 0; i < cnt; i++) {
661 if (likely(cpu_list[i] == 0xffff))
665 forward_progress = 0;
666 if (n_sent > prev_sent)
667 forward_progress = 1;
671 /* If we get a HV_ECPUERROR, then one or more of the cpus
672 * in the list are in error state. Use the cpu_state()
673 * hypervisor call to find out which cpus are in error state.
675 if (unlikely(status == HV_ECPUERROR)) {
676 for (i = 0; i < cnt; i++) {
684 err = sun4v_cpu_state(cpu);
686 err == HV_CPU_STATE_ERROR) {
687 cpu_list[i] = 0xffff;
688 cpu_set(cpu, error_mask);
691 } else if (unlikely(status != HV_EWOULDBLOCK))
692 goto fatal_mondo_error;
694 /* Don't bother rewriting the CPU list, just leave the
695 * 0xffff and non-0xffff entries in there and the
696 * hypervisor will do the right thing.
698 * Only advance timeout state if we didn't make any
701 if (unlikely(!forward_progress)) {
702 if (unlikely(++retries > 10000))
703 goto fatal_mondo_timeout;
705 /* Delay a little bit to let other cpus catch up
706 * on their cpu mondo queue work.
712 local_irq_restore(flags);
714 if (unlikely(!cpus_empty(error_mask)))
715 goto fatal_mondo_cpu_error;
719 fatal_mondo_cpu_error:
720 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
721 "were in error state\n",
723 printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
724 for_each_cpu_mask(i, error_mask)
730 local_irq_restore(flags);
731 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
732 " progress after %d retries.\n",
734 goto dump_cpu_list_and_out;
737 local_irq_restore(flags);
738 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
740 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
741 "mondo_block_pa(%lx)\n",
742 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
744 dump_cpu_list_and_out:
745 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
746 for (i = 0; i < cnt; i++)
747 printk("%u ", cpu_list[i]);
751 /* Send cross call to all processors mentioned in MASK
754 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
756 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
757 int this_cpu = get_cpu();
759 cpus_and(mask, mask, cpu_online_map);
760 cpu_clear(this_cpu, mask);
762 if (tlb_type == spitfire)
763 spitfire_xcall_deliver(data0, data1, data2, mask);
764 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
765 cheetah_xcall_deliver(data0, data1, data2, mask);
767 hypervisor_xcall_deliver(data0, data1, data2, mask);
768 /* NOTE: Caller runs local copy on master. */
773 extern unsigned long xcall_sync_tick;
775 static void smp_start_sync_tick_client(int cpu)
777 cpumask_t mask = cpumask_of_cpu(cpu);
779 smp_cross_call_masked(&xcall_sync_tick,
783 /* Send cross call to all processors except self. */
784 #define smp_cross_call(func, ctx, data1, data2) \
785 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
787 struct call_data_struct {
788 void (*func) (void *info);
794 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
795 static struct call_data_struct *call_data;
797 extern unsigned long xcall_call_function;
800 * smp_call_function(): Run a function on all other CPUs.
801 * @func: The function to run. This must be fast and non-blocking.
802 * @info: An arbitrary pointer to pass to the function.
803 * @nonatomic: currently unused.
804 * @wait: If true, wait (atomically) until function has completed on other CPUs.
806 * Returns 0 on success, else a negative status code. Does not return until
807 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
809 * You must not call this function with disabled interrupts or from a
810 * hardware interrupt handler or from a bottom half handler.
812 static int smp_call_function_mask(void (*func)(void *info), void *info,
813 int nonatomic, int wait, cpumask_t mask)
815 struct call_data_struct data;
818 /* Can deadlock when called with interrupts disabled */
819 WARN_ON(irqs_disabled());
823 atomic_set(&data.finished, 0);
826 spin_lock(&call_lock);
828 cpu_clear(smp_processor_id(), mask);
829 cpus = cpus_weight(mask);
836 smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
838 /* Wait for response */
839 while (atomic_read(&data.finished) != cpus)
843 spin_unlock(&call_lock);
848 int smp_call_function(void (*func)(void *info), void *info,
849 int nonatomic, int wait)
851 return smp_call_function_mask(func, info, nonatomic, wait,
855 void smp_call_function_client(int irq, struct pt_regs *regs)
857 void (*func) (void *info) = call_data->func;
858 void *info = call_data->info;
860 clear_softint(1 << irq);
861 if (call_data->wait) {
862 /* let initiator proceed only after completion */
864 atomic_inc(&call_data->finished);
866 /* let initiator proceed after getting data */
867 atomic_inc(&call_data->finished);
872 static void tsb_sync(void *info)
874 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
875 struct mm_struct *mm = info;
877 /* It is not valid to test "currrent->active_mm == mm" here.
879 * The value of "current" is not changed atomically with
880 * switch_mm(). But that's OK, we just need to check the
881 * current cpu's trap block PGD physical address.
883 if (tp->pgd_paddr == __pa(mm->pgd))
884 tsb_context_switch(mm);
887 void smp_tsb_sync(struct mm_struct *mm)
889 smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
892 extern unsigned long xcall_flush_tlb_mm;
893 extern unsigned long xcall_flush_tlb_pending;
894 extern unsigned long xcall_flush_tlb_kernel_range;
895 extern unsigned long xcall_report_regs;
896 extern unsigned long xcall_receive_signal;
897 extern unsigned long xcall_new_mmu_context_version;
899 #ifdef DCACHE_ALIASING_POSSIBLE
900 extern unsigned long xcall_flush_dcache_page_cheetah;
902 extern unsigned long xcall_flush_dcache_page_spitfire;
904 #ifdef CONFIG_DEBUG_DCFLUSH
905 extern atomic_t dcpage_flushes;
906 extern atomic_t dcpage_flushes_xcall;
909 static __inline__ void __local_flush_dcache_page(struct page *page)
911 #ifdef DCACHE_ALIASING_POSSIBLE
912 __flush_dcache_page(page_address(page),
913 ((tlb_type == spitfire) &&
914 page_mapping(page) != NULL));
916 if (page_mapping(page) != NULL &&
917 tlb_type == spitfire)
918 __flush_icache_page(__pa(page_address(page)));
922 void smp_flush_dcache_page_impl(struct page *page, int cpu)
924 cpumask_t mask = cpumask_of_cpu(cpu);
927 if (tlb_type == hypervisor)
930 #ifdef CONFIG_DEBUG_DCFLUSH
931 atomic_inc(&dcpage_flushes);
934 this_cpu = get_cpu();
936 if (cpu == this_cpu) {
937 __local_flush_dcache_page(page);
938 } else if (cpu_online(cpu)) {
939 void *pg_addr = page_address(page);
942 if (tlb_type == spitfire) {
944 ((u64)&xcall_flush_dcache_page_spitfire);
945 if (page_mapping(page) != NULL)
946 data0 |= ((u64)1 << 32);
947 spitfire_xcall_deliver(data0,
951 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
952 #ifdef DCACHE_ALIASING_POSSIBLE
954 ((u64)&xcall_flush_dcache_page_cheetah);
955 cheetah_xcall_deliver(data0,
960 #ifdef CONFIG_DEBUG_DCFLUSH
961 atomic_inc(&dcpage_flushes_xcall);
968 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
970 void *pg_addr = page_address(page);
971 cpumask_t mask = cpu_online_map;
975 if (tlb_type == hypervisor)
978 this_cpu = get_cpu();
980 cpu_clear(this_cpu, mask);
982 #ifdef CONFIG_DEBUG_DCFLUSH
983 atomic_inc(&dcpage_flushes);
985 if (cpus_empty(mask))
987 if (tlb_type == spitfire) {
988 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
989 if (page_mapping(page) != NULL)
990 data0 |= ((u64)1 << 32);
991 spitfire_xcall_deliver(data0,
995 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
996 #ifdef DCACHE_ALIASING_POSSIBLE
997 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
998 cheetah_xcall_deliver(data0,
1003 #ifdef CONFIG_DEBUG_DCFLUSH
1004 atomic_inc(&dcpage_flushes_xcall);
1007 __local_flush_dcache_page(page);
1012 static void __smp_receive_signal_mask(cpumask_t mask)
1014 smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
1017 void smp_receive_signal(int cpu)
1019 cpumask_t mask = cpumask_of_cpu(cpu);
1021 if (cpu_online(cpu))
1022 __smp_receive_signal_mask(mask);
1025 void smp_receive_signal_client(int irq, struct pt_regs *regs)
1027 clear_softint(1 << irq);
1030 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
1032 struct mm_struct *mm;
1033 unsigned long flags;
1035 clear_softint(1 << irq);
1037 /* See if we need to allocate a new TLB context because
1038 * the version of the one we are using is now out of date.
1040 mm = current->active_mm;
1041 if (unlikely(!mm || (mm == &init_mm)))
1044 spin_lock_irqsave(&mm->context.lock, flags);
1046 if (unlikely(!CTX_VALID(mm->context)))
1047 get_new_mmu_context(mm);
1049 spin_unlock_irqrestore(&mm->context.lock, flags);
1051 load_secondary_context(mm);
1052 __flush_tlb_mm(CTX_HWBITS(mm->context),
1056 void smp_new_mmu_context_version(void)
1058 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1061 void smp_report_regs(void)
1063 smp_cross_call(&xcall_report_regs, 0, 0, 0);
1066 /* We know that the window frames of the user have been flushed
1067 * to the stack before we get here because all callers of us
1068 * are flush_tlb_*() routines, and these run after flush_cache_*()
1069 * which performs the flushw.
1071 * The SMP TLB coherency scheme we use works as follows:
1073 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1074 * space has (potentially) executed on, this is the heuristic
1075 * we use to avoid doing cross calls.
1077 * Also, for flushing from kswapd and also for clones, we
1078 * use cpu_vm_mask as the list of cpus to make run the TLB.
1080 * 2) TLB context numbers are shared globally across all processors
1081 * in the system, this allows us to play several games to avoid
1084 * One invariant is that when a cpu switches to a process, and
1085 * that processes tsk->active_mm->cpu_vm_mask does not have the
1086 * current cpu's bit set, that tlb context is flushed locally.
1088 * If the address space is non-shared (ie. mm->count == 1) we avoid
1089 * cross calls when we want to flush the currently running process's
1090 * tlb state. This is done by clearing all cpu bits except the current
1091 * processor's in current->active_mm->cpu_vm_mask and performing the
1092 * flush locally only. This will force any subsequent cpus which run
1093 * this task to flush the context from the local tlb if the process
1094 * migrates to another cpu (again).
1096 * 3) For shared address spaces (threads) and swapping we bite the
1097 * bullet for most cases and perform the cross call (but only to
1098 * the cpus listed in cpu_vm_mask).
1100 * The performance gain from "optimizing" away the cross call for threads is
1101 * questionable (in theory the big win for threads is the massive sharing of
1102 * address space state across processors).
1105 /* This currently is only used by the hugetlb arch pre-fault
1106 * hook on UltraSPARC-III+ and later when changing the pagesize
1107 * bits of the context register for an address space.
1109 void smp_flush_tlb_mm(struct mm_struct *mm)
1111 u32 ctx = CTX_HWBITS(mm->context);
1112 int cpu = get_cpu();
1114 if (atomic_read(&mm->mm_users) == 1) {
1115 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1116 goto local_flush_and_out;
1119 smp_cross_call_masked(&xcall_flush_tlb_mm,
1123 local_flush_and_out:
1124 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1129 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1131 u32 ctx = CTX_HWBITS(mm->context);
1132 int cpu = get_cpu();
1134 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1135 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1137 smp_cross_call_masked(&xcall_flush_tlb_pending,
1138 ctx, nr, (unsigned long) vaddrs,
1141 __flush_tlb_pending(ctx, nr, vaddrs);
1146 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1149 end = PAGE_ALIGN(end);
1151 smp_cross_call(&xcall_flush_tlb_kernel_range,
1154 __flush_tlb_kernel_range(start, end);
1159 /* #define CAPTURE_DEBUG */
1160 extern unsigned long xcall_capture;
1162 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1163 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1164 static unsigned long penguins_are_doing_time;
1166 void smp_capture(void)
1168 int result = atomic_add_ret(1, &smp_capture_depth);
1171 int ncpus = num_online_cpus();
1173 #ifdef CAPTURE_DEBUG
1174 printk("CPU[%d]: Sending penguins to jail...",
1175 smp_processor_id());
1177 penguins_are_doing_time = 1;
1178 membar_storestore_loadstore();
1179 atomic_inc(&smp_capture_registry);
1180 smp_cross_call(&xcall_capture, 0, 0, 0);
1181 while (atomic_read(&smp_capture_registry) != ncpus)
1183 #ifdef CAPTURE_DEBUG
1189 void smp_release(void)
1191 if (atomic_dec_and_test(&smp_capture_depth)) {
1192 #ifdef CAPTURE_DEBUG
1193 printk("CPU[%d]: Giving pardon to "
1194 "imprisoned penguins\n",
1195 smp_processor_id());
1197 penguins_are_doing_time = 0;
1198 membar_storeload_storestore();
1199 atomic_dec(&smp_capture_registry);
1203 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1204 * can service tlb flush xcalls...
1206 extern void prom_world(int);
1208 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1210 clear_softint(1 << irq);
1214 __asm__ __volatile__("flushw");
1216 atomic_inc(&smp_capture_registry);
1217 membar_storeload_storestore();
1218 while (penguins_are_doing_time)
1220 atomic_dec(&smp_capture_registry);
1226 /* /proc/profile writes can call this, don't __init it please. */
1227 int setup_profiling_timer(unsigned int multiplier)
1232 void __init smp_prepare_cpus(unsigned int max_cpus)
1236 void __devinit smp_prepare_boot_cpu(void)
1240 void __devinit smp_fill_in_sib_core_maps(void)
1244 for_each_possible_cpu(i) {
1247 if (cpu_data(i).core_id == 0) {
1248 cpu_set(i, cpu_core_map[i]);
1252 for_each_possible_cpu(j) {
1253 if (cpu_data(i).core_id ==
1254 cpu_data(j).core_id)
1255 cpu_set(j, cpu_core_map[i]);
1259 for_each_possible_cpu(i) {
1262 if (cpu_data(i).proc_id == -1) {
1263 cpu_set(i, cpu_sibling_map[i]);
1267 for_each_possible_cpu(j) {
1268 if (cpu_data(i).proc_id ==
1269 cpu_data(j).proc_id)
1270 cpu_set(j, cpu_sibling_map[i]);
1275 int __cpuinit __cpu_up(unsigned int cpu)
1277 int ret = smp_boot_one_cpu(cpu);
1280 cpu_set(cpu, smp_commenced_mask);
1281 while (!cpu_isset(cpu, cpu_online_map))
1283 if (!cpu_isset(cpu, cpu_online_map)) {
1286 /* On SUN4V, writes to %tick and %stick are
1289 if (tlb_type != hypervisor)
1290 smp_synchronize_one_tick(cpu);
1296 #ifdef CONFIG_HOTPLUG_CPU
1297 int __cpu_disable(void)
1299 printk(KERN_ERR "SMP: __cpu_disable() on cpu %d\n",
1300 smp_processor_id());
1304 void __cpu_die(unsigned int cpu)
1306 printk(KERN_ERR "SMP: __cpu_die(%u)\n", cpu);
1310 void __init smp_cpus_done(unsigned int max_cpus)
1314 void smp_send_reschedule(int cpu)
1316 smp_receive_signal(cpu);
1319 /* This is a nop because we capture all other cpus
1320 * anyways when making the PROM active.
1322 void smp_send_stop(void)
1326 unsigned long __per_cpu_base __read_mostly;
1327 unsigned long __per_cpu_shift __read_mostly;
1329 EXPORT_SYMBOL(__per_cpu_base);
1330 EXPORT_SYMBOL(__per_cpu_shift);
1332 void __init real_setup_per_cpu_areas(void)
1334 unsigned long goal, size, i;
1337 /* Copy section for each CPU (we discard the original) */
1338 goal = PERCPU_ENOUGH_ROOM;
1340 __per_cpu_shift = PAGE_SHIFT;
1341 for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1344 ptr = alloc_bootmem_pages(size * NR_CPUS);
1346 __per_cpu_base = ptr - __per_cpu_start;
1348 for (i = 0; i < NR_CPUS; i++, ptr += size)
1349 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1351 /* Setup %g5 for the boot cpu. */
1352 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());