1 /* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $
2 * ultra.S: Don't expand these all over the place...
4 * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com)
7 #include <linux/config.h>
9 #include <asm/pgtable.h>
11 #include <asm/spitfire.h>
12 #include <asm/mmu_context.h>
16 #include <asm/thread_info.h>
17 #include <asm/cacheflush.h>
19 /* Basically, most of the Spitfire vs. Cheetah madness
20 * has to do with the fact that Cheetah does not support
21 * IMMU flushes out of the secondary context. Someone needs
22 * to throw a south lake birthday party for the folks
23 * in Microelectronics who refused to fix this shit.
26 /* This file is meant to be read efficiently by the CPU, not humans.
27 * Staraj sie tego nikomu nie pierdolnac...
32 __flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
33 ldxa [%o1] ASI_DMMU, %g2
35 bne,pn %icc, __spitfire_flush_tlb_mm_slow
37 stxa %g0, [%g3] ASI_DMMU_DEMAP
38 stxa %g0, [%g3] ASI_IMMU_DEMAP
39 sethi %hi(KERNBASE), %g3
54 .globl __flush_tlb_pending
56 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
59 andn %g7, PSTATE_IE, %g2
61 mov SECONDARY_CONTEXT, %o4
62 ldxa [%o4] ASI_DMMU, %g2
63 stxa %o0, [%o4] ASI_DMMU
64 1: sub %o1, (1 << 3), %o1
70 stxa %g0, [%o3] ASI_IMMU_DEMAP
71 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
75 stxa %g2, [%o4] ASI_DMMU
76 sethi %hi(KERNBASE), %o4
79 wrpr %g7, 0x0, %pstate
86 .globl __flush_tlb_kernel_range
87 __flush_tlb_kernel_range: /* %o0=start, %o1=end */
90 sethi %hi(PAGE_SIZE), %o4
93 or %o0, 0x20, %o0 ! Nucleus
94 1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
95 stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
99 2: sethi %hi(KERNBASE), %o3
104 __spitfire_flush_tlb_mm_slow:
106 wrpr %g1, PSTATE_IE, %pstate
107 stxa %o0, [%o1] ASI_DMMU
108 stxa %g0, [%g3] ASI_DMMU_DEMAP
109 stxa %g0, [%g3] ASI_IMMU_DEMAP
111 stxa %g2, [%o1] ASI_DMMU
112 sethi %hi(KERNBASE), %o1
118 * The following code flushes one page_size worth.
120 #if (PAGE_SHIFT == 13)
121 #define ITAG_MASK 0xfe
122 #elif (PAGE_SHIFT == 16)
123 #define ITAG_MASK 0x7fe
125 #error unsupported PAGE_SIZE
127 .section .kprobes.text, "ax"
129 .globl __flush_icache_page
130 __flush_icache_page: /* %o0 = phys_page */
132 srlx %o0, PAGE_SHIFT, %o0
133 sethi %uhi(PAGE_OFFSET), %g1
134 sllx %o0, PAGE_SHIFT, %o0
135 sethi %hi(PAGE_SIZE), %g2
138 1: subcc %g2, 32, %g2
144 #ifdef DCACHE_ALIASING_POSSIBLE
146 #if (PAGE_SHIFT != 13)
147 #error only page shift of 13 is supported by dcache flush
150 #define DTAG_MASK 0x3
152 /* This routine is Spitfire specific so the hardcoded
153 * D-cache size and line-size are OK.
156 .globl __flush_dcache_page
157 __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
158 sethi %uhi(PAGE_OFFSET), %g1
160 sub %o0, %g1, %o0 ! physical address
161 srlx %o0, 11, %o0 ! make D-cache TAG
162 sethi %hi(1 << 14), %o2 ! D-cache size
163 sub %o2, (1 << 5), %o2 ! D-cache line size
164 1: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG
165 andcc %o3, DTAG_MASK, %g0 ! Valid?
166 be,pn %xcc, 2f ! Nope, branch
167 andn %o3, DTAG_MASK, %o3 ! Clear valid bits
168 cmp %o3, %o0 ! TAG match?
169 bne,pt %xcc, 2f ! Nope, branch
171 stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG
174 sub %o2, (1 << 5), %o2 ! D-cache line size
176 /* The I-cache does not snoop local stores so we
177 * better flush that too when necessary.
179 brnz,pt %o1, __flush_icache_page
184 #endif /* DCACHE_ALIASING_POSSIBLE */
188 /* Cheetah specific versions, patched at boot time. */
189 __cheetah_flush_tlb_mm: /* 19 insns */
191 andn %g7, PSTATE_IE, %g2
192 wrpr %g2, 0x0, %pstate
194 mov PRIMARY_CONTEXT, %o2
196 ldxa [%o2] ASI_DMMU, %g2
197 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1
198 sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1
199 or %o0, %o1, %o0 /* Preserve nucleus page size fields */
200 stxa %o0, [%o2] ASI_DMMU
201 stxa %g0, [%g3] ASI_DMMU_DEMAP
202 stxa %g0, [%g3] ASI_IMMU_DEMAP
203 stxa %g2, [%o2] ASI_DMMU
204 sethi %hi(KERNBASE), %o2
208 wrpr %g7, 0x0, %pstate
210 __cheetah_flush_tlb_pending: /* 27 insns */
211 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
214 andn %g7, PSTATE_IE, %g2
215 wrpr %g2, 0x0, %pstate
217 mov PRIMARY_CONTEXT, %o4
218 ldxa [%o4] ASI_DMMU, %g2
219 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
220 sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
221 or %o0, %o3, %o0 /* Preserve nucleus page size fields */
222 stxa %o0, [%o4] ASI_DMMU
223 1: sub %o1, (1 << 3), %o1
228 stxa %g0, [%o3] ASI_IMMU_DEMAP
229 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
233 stxa %g2, [%o4] ASI_DMMU
234 sethi %hi(KERNBASE), %o4
238 wrpr %g7, 0x0, %pstate
240 #ifdef DCACHE_ALIASING_POSSIBLE
241 __cheetah_flush_dcache_page: /* 11 insns */
242 sethi %uhi(PAGE_OFFSET), %g1
245 sethi %hi(PAGE_SIZE), %o4
246 1: subcc %o4, (1 << 5), %o4
247 stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
251 retl /* I-cache flush never needed on Cheetah, see callers. */
253 #endif /* DCACHE_ALIASING_POSSIBLE */
266 .globl cheetah_patch_cachetlbops
267 cheetah_patch_cachetlbops:
270 sethi %hi(__flush_tlb_mm), %o0
271 or %o0, %lo(__flush_tlb_mm), %o0
272 sethi %hi(__cheetah_flush_tlb_mm), %o1
273 or %o1, %lo(__cheetah_flush_tlb_mm), %o1
274 call cheetah_patch_one
277 sethi %hi(__flush_tlb_pending), %o0
278 or %o0, %lo(__flush_tlb_pending), %o0
279 sethi %hi(__cheetah_flush_tlb_pending), %o1
280 or %o1, %lo(__cheetah_flush_tlb_pending), %o1
281 call cheetah_patch_one
284 #ifdef DCACHE_ALIASING_POSSIBLE
285 sethi %hi(__flush_dcache_page), %o0
286 or %o0, %lo(__flush_dcache_page), %o0
287 sethi %hi(__cheetah_flush_dcache_page), %o1
288 or %o1, %lo(__cheetah_flush_dcache_page), %o1
289 call cheetah_patch_one
291 #endif /* DCACHE_ALIASING_POSSIBLE */
297 /* These are all called by the slaves of a cross call, at
298 * trap level 1, with interrupts fully disabled.
301 * %g5 mm->context (all tlb flushes)
302 * %g1 address arg 1 (tlb page and range flushes)
303 * %g7 address arg 2 (tlb range flush only)
311 .globl xcall_flush_tlb_mm
313 mov PRIMARY_CONTEXT, %g2
314 ldxa [%g2] ASI_DMMU, %g3
315 srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4
316 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
317 or %g5, %g4, %g5 /* Preserve nucleus page size fields */
318 stxa %g5, [%g2] ASI_DMMU
320 stxa %g0, [%g4] ASI_DMMU_DEMAP
321 stxa %g0, [%g4] ASI_IMMU_DEMAP
322 stxa %g3, [%g2] ASI_DMMU
325 .globl xcall_flush_tlb_pending
326 xcall_flush_tlb_pending:
327 /* %g5=context, %g1=nr, %g7=vaddrs[] */
329 mov PRIMARY_CONTEXT, %g4
330 ldxa [%g4] ASI_DMMU, %g2
331 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
332 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
334 mov PRIMARY_CONTEXT, %g4
335 stxa %g5, [%g4] ASI_DMMU
336 1: sub %g1, (1 << 3), %g1
342 stxa %g0, [%g5] ASI_IMMU_DEMAP
343 2: stxa %g0, [%g5] ASI_DMMU_DEMAP
347 stxa %g2, [%g4] ASI_DMMU
350 .globl xcall_flush_tlb_kernel_range
351 xcall_flush_tlb_kernel_range:
352 sethi %hi(PAGE_SIZE - 1), %g2
353 or %g2, %lo(PAGE_SIZE - 1), %g2
359 or %g1, 0x20, %g1 ! Nucleus
360 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
361 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
369 /* This runs in a very controlled environment, so we do
370 * not need to worry about BH races etc.
372 .globl xcall_sync_tick
375 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
380 109: or %g7, %lo(109b), %g7
381 call smp_synchronize_tick_client
385 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
387 /* NOTE: This is SPECIAL!! We do etrap/rtrap however
388 * we choose to deal with the "BH's run with
389 * %pil==15" problem (described in asm/pil.h)
390 * by just invoking rtrap directly past where
391 * BH's are checked for.
393 * We do it like this because we do not want %pil==15
394 * lockups to prevent regs being reported.
396 .globl xcall_report_regs
399 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
404 109: or %g7, %lo(109b), %g7
406 add %sp, PTREGS_OFF, %o0
408 /* Has to be a non-v9 branch due to the large distance. */
410 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
412 #ifdef DCACHE_ALIASING_POSSIBLE
414 .globl xcall_flush_dcache_page_cheetah
415 xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
416 sethi %hi(PAGE_SIZE), %g3
417 1: subcc %g3, (1 << 5), %g3
418 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
424 #endif /* DCACHE_ALIASING_POSSIBLE */
426 .globl xcall_flush_dcache_page_spitfire
427 xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
428 %g7 == kernel page virtual address
429 %g5 == (page->mapping != NULL) */
430 #ifdef DCACHE_ALIASING_POSSIBLE
431 srlx %g1, (13 - 2), %g1 ! Form tag comparitor
432 sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
433 sub %g3, (1 << 5), %g3 ! D$ linesize == 32
434 1: ldxa [%g3] ASI_DCACHE_TAG, %g2
442 stxa %g0, [%g3] ASI_DCACHE_TAG
446 sub %g3, (1 << 5), %g3
449 #endif /* DCACHE_ALIASING_POSSIBLE */
450 sethi %hi(PAGE_SIZE), %g3
453 subcc %g3, (1 << 5), %g3
455 add %g7, (1 << 5), %g7
461 /* These just get rescheduled to PIL vectors. */
462 .globl xcall_call_function
464 wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
467 .globl xcall_receive_signal
468 xcall_receive_signal:
469 wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
474 wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
477 #endif /* CONFIG_SMP */