2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_PCI_BRIDGE_H
16 #define _ASM_TILE_PCI_BRIDGE_H
18 #include <linux/ioport.h>
19 #include <linux/pci.h>
22 struct pci_controller;
25 * pci_io_base returns the memory address at which you can access
26 * the I/O space for PCI bus number `bus' (or NULL on error).
28 extern void __iomem *pci_bus_io_base(unsigned int bus);
29 extern unsigned long pci_bus_io_base_phys(unsigned int bus);
30 extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
32 /* Allocate a new PCI host bridge structure */
33 extern struct pci_controller *pcibios_alloc_controller(void);
35 /* Helper function for setting up resources */
36 extern void pci_init_resource(struct resource *res, unsigned long start,
37 unsigned long end, int flags, char *name);
39 /* Get the PCI host controller for a bus */
40 extern struct pci_controller *pci_bus_to_hose(int bus);
43 * Structure of a PCI controller (host bridge)
45 struct pci_controller {
46 int index; /* PCI domain number */
47 struct pci_bus *root_bus;
52 int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
53 int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
57 int irq_base; /* Base IRQ from the Hypervisor */
58 int plx_gen1; /* flag for PLX Gen 1 configuration */
60 /* Address ranges that are routed to this controller/bridge. */
61 struct resource mem_resources[3];
64 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
69 extern void setup_indirect_pci_nomap(struct pci_controller *hose,
70 void __iomem *cfg_addr, void __iomem *cfg_data);
71 extern void setup_indirect_pci(struct pci_controller *hose,
72 u32 cfg_addr, u32 cfg_data);
73 extern void setup_grackle(struct pci_controller *hose);
75 extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
78 * The following code swizzles for exactly one bridge. The routine
79 * common_swizzle below handles multiple bridges. But there are a
80 * some boards that don't follow the PCI spec's suggestion so we
81 * break this piece out separately.
83 static inline unsigned char bridge_swizzle(unsigned char pin,
86 return (((pin-1) + idsel) % 4) + 1;
90 * The following macro is used to lookup irqs in a standard table
91 * format for those PPC systems that do not already have PCI
92 * interrupts properly routed.
94 /* FIXME - double check this */
95 #define PCI_IRQ_TABLE_LOOKUP ({ \
97 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
98 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
103 * Scan the buses below a given PCI host bridge and assign suitable
104 * resources to all devices found.
106 extern int pciauto_bus_scan(struct pci_controller *, int);
109 extern unsigned long pci_address_to_pio(phys_addr_t address);
111 static inline unsigned long pci_address_to_pio(phys_addr_t address)
113 return (unsigned long)-1;
117 #endif /* _ASM_TILE_PCI_BRIDGE_H */