2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_PCI_H
16 #define _ASM_TILE_PCI_H
18 #include <asm/pci-bridge.h>
21 * The hypervisor maps the entirety of CPA-space as bus addresses, so
22 * bus addresses are physical addresses. The networking and block
23 * device layers use this boolean for bounce buffer decisions.
25 #define PCI_DMA_BUS_IS_PHYS 1
27 struct pci_controller *pci_bus_to_hose(int bus);
28 unsigned char __init common_swizzle(struct pci_dev *dev, unsigned char *pinp);
29 int __init tile_pci_init(void);
30 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
31 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
32 void __devinit pcibios_fixup_bus(struct pci_bus *bus);
34 int __devinit _tile_cfg_read(struct pci_controller *hose,
41 int __devinit _tile_cfg_write(struct pci_controller *hose,
50 * These are used to to config reads and writes in the early stages of
51 * setup before the driver infrastructure has been set up enough to be
52 * able to do config reads and writes.
54 #define early_cfg_read(where, size, value) \
55 _tile_cfg_read(controller, \
63 #define early_cfg_write(where, size, value) \
64 _tile_cfg_write(controller, \
76 #define PCICFG_DWORD 4
78 #define TILE_NUM_PCIE 2
80 #define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
83 * This decides whether to display the domain number in /proc.
85 static inline int pci_proc_domain(struct pci_bus *bus)
91 * I/O space is currently not supported.
94 #define TILE_PCIE_LOWER_IO 0x0
95 #define TILE_PCIE_UPPER_IO 0x10000
96 #define TILE_PCIE_PCIE_IO_SIZE 0x0000FFFF
98 #define _PAGE_NO_CACHE 0
99 #define _PAGE_GUARDED 0
102 #define pcibios_assign_all_busses() pci_assign_all_buses
103 extern int pci_assign_all_buses;
105 static inline void pcibios_set_master(struct pci_dev *dev)
107 /* No special bus mastering setup handling */
110 #define PCIBIOS_MIN_MEM 0
111 #define PCIBIOS_MIN_IO TILE_PCIE_LOWER_IO
114 * This flag tells if the platform is TILEmpower that needs
115 * special configuration for the PLX switch chip.
117 extern int blade_pci;
119 /* implement the pci_ DMA API in terms of the generic device dma_ one */
120 #include <asm-generic/pci-dma-compat.h>
122 /* generic pci stuff */
123 #include <asm-generic/pci.h>
125 /* Use any cpu for PCI. */
126 #define cpumask_of_pcibus(bus) cpu_online_mask
128 #endif /* _ASM_TILE_PCI_H */