2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
17 #include <linux/linkage.h>
18 #include <linux/init.h>
20 #include <asm/pgtable.h>
21 #include <asm/thread_info.h>
22 #include <asm/processor.h>
23 #include <asm/asm-offsets.h>
24 #include <hv/hypervisor.h>
25 #include <arch/chip.h>
28 * This module contains the entry code for kernel images. It performs the
29 * minimal setup needed to call the generic C routines.
34 /* Notify the hypervisor of what version of the API we want */
37 movei r2, TILE_CHIP_REV
40 moveli r0, _HV_VERSION
43 /* Get a reasonable default ASID in r0 */
48 /* Install the default page table */
50 moveli r6, lo16(swapper_pgprot - PAGE_OFFSET)
51 move r4, r0 /* use starting ASID of range for this page table */
54 moveli r0, lo16(swapper_pg_dir - PAGE_OFFSET)
55 auli r6, r6, ha16(swapper_pgprot - PAGE_OFFSET)
63 auli r0, r0, ha16(swapper_pg_dir - PAGE_OFFSET)
67 move r1, zero /* high 32 bits of CPA is zero */
79 /* Get our processor number and save it away in SAVE_1_0. */
80 jal hv_inquire_topology
81 mulll_uu r4, r1, r2 /* r1 == y, r2 == width */
82 add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */
86 * Load up our per-cpu offset. When the first (master) tile
87 * boots, this value is still zero, so we will load boot_pc
88 * with start_kernel, and boot_sp with init_stack + THREAD_SIZE.
89 * The master tile initializes the per-cpu offset array, so that
90 * when subsequent (secondary) tiles boot, they will instead load
91 * from their per-cpu versions of boot_sp and boot_pc.
93 moveli r5, lo16(__per_cpu_offset)
94 auli r5, r5, ha16(__per_cpu_offset)
100 * Save the width and height to the smp_topology variable
103 moveli r0, lo16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
104 auli r0, r0, ha16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
107 addi r0, r0, (HV_TOPOLOGY_HEIGHT_OFFSET - HV_TOPOLOGY_WIDTH_OFFSET)
115 /* Load and go with the correct pc and sp. */
117 addli r1, r5, lo16(boot_sp)
118 addli r0, r5, lo16(boot_pc)
121 auli r1, r1, ha16(boot_sp)
122 auli r0, r0, ha16(boot_pc)
127 mtspr SYSTEM_SAVE_1_0, r4 /* save ksp0 + cpu */
128 addi sp, sp, -STACK_TOP_DELTA
130 move lr, zero /* stop backtraces in the called function */
135 .section ".bss.page_aligned","w"
137 ENTRY(empty_zero_page)
141 .macro PTE va, cpa, bits1, no_org=0
143 .org swapper_pg_dir + HV_L1_INDEX(\va) * HV_PTE_SIZE
145 .word HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED | \
146 (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
147 .word (\bits1) | (HV_CPA_TO_PFN(\cpa) << HV_PTE_INDEX_PFN)
150 .section ".data.page_aligned","wa"
152 ENTRY(swapper_pg_dir)
154 * All data pages from PAGE_OFFSET to MEM_USER_INTRPT are mapped as
155 * VA = PA + PAGE_OFFSET. We remap things with more precise access
156 * permissions and more respect for size of RAM later.
159 .rept (MEM_USER_INTRPT - PAGE_OFFSET) >> PGDIR_SHIFT
160 PTE addr + PAGE_OFFSET, addr, HV_PTE_READABLE | HV_PTE_WRITABLE
161 .set addr, addr + PGDIR_SIZE
164 /* The true text VAs are mapped as VA = PA + MEM_SV_INTRPT */
165 PTE MEM_SV_INTRPT, 0, HV_PTE_READABLE | HV_PTE_EXECUTABLE
166 .org swapper_pg_dir + HV_L1_SIZE
170 * Isolate swapper_pgprot to its own cache line, since each cpu
171 * starting up will read it using VA-is-PA and local homing.
172 * This would otherwise likely conflict with other data on the cache
173 * line, once we have set its permanent home in the page tables.
176 .align CHIP_L2_LINE_SIZE()
177 ENTRY(swapper_pgprot)
178 PTE 0, 0, HV_PTE_READABLE | HV_PTE_WRITABLE, 1
179 .align CHIP_L2_LINE_SIZE()