2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #include <linux/cache.h>
16 #include <linux/delay.h>
17 #include <linux/uaccess.h>
18 #include <linux/module.h>
20 #include <asm/atomic.h>
21 #include <asm/futex.h>
22 #include <arch/chip.h>
24 /* See <asm/atomic_32.h> */
25 #if ATOMIC_LOCKS_FOUND_VIA_TABLE()
28 * A block of memory containing locks for atomic ops. Each instance of this
29 * struct will be homed on a different CPU.
31 struct atomic_locks_on_cpu {
32 int lock[ATOMIC_HASH_L2_SIZE];
33 } __attribute__((aligned(ATOMIC_HASH_L2_SIZE * 4)));
35 static DEFINE_PER_CPU(struct atomic_locks_on_cpu, atomic_lock_pool);
37 /* The locks we'll use until __init_atomic_per_cpu is called. */
38 static struct atomic_locks_on_cpu __initdata initial_atomic_locks;
40 /* Hash into this vector to get a pointer to lock for the given atomic. */
41 struct atomic_locks_on_cpu *atomic_lock_ptr[ATOMIC_HASH_L1_SIZE]
43 [0 ... ATOMIC_HASH_L1_SIZE-1] (&initial_atomic_locks)
46 #else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
48 /* This page is remapped on startup to be hash-for-home. */
49 int atomic_locks[PAGE_SIZE / sizeof(int) /* Only ATOMIC_HASH_SIZE is used */]
50 __attribute__((aligned(PAGE_SIZE), section(".bss.page_aligned")));
52 #endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
54 static inline int *__atomic_hashed_lock(volatile void *v)
56 /* NOTE: this code must match "sys_cmpxchg" in kernel/intvec.S */
57 #if ATOMIC_LOCKS_FOUND_VIA_TABLE()
59 (unsigned long) v & ((PAGE_SIZE-1) & -sizeof(long long));
60 unsigned long n = __insn_crc32_32(0, i);
62 /* Grab high bits for L1 index. */
63 unsigned long l1_index = n >> ((sizeof(n) * 8) - ATOMIC_HASH_L1_SHIFT);
64 /* Grab low bits for L2 index. */
65 unsigned long l2_index = n & (ATOMIC_HASH_L2_SIZE - 1);
67 return &atomic_lock_ptr[l1_index]->lock[l2_index];
70 * Use bits [3, 3 + ATOMIC_HASH_SHIFT) as the lock index.
71 * Using mm works here because atomic_locks is page aligned.
73 unsigned long ptr = __insn_mm((unsigned long)v >> 1,
74 (unsigned long)atomic_locks,
75 2, (ATOMIC_HASH_SHIFT + 2) - 1);
81 /* Return whether the passed pointer is a valid atomic lock pointer. */
82 static int is_atomic_lock(int *p)
84 #if ATOMIC_LOCKS_FOUND_VIA_TABLE()
86 for (i = 0; i < ATOMIC_HASH_L1_SIZE; ++i) {
88 if (p >= &atomic_lock_ptr[i]->lock[0] &&
89 p < &atomic_lock_ptr[i]->lock[ATOMIC_HASH_L2_SIZE]) {
95 return p >= &atomic_locks[0] && p < &atomic_locks[ATOMIC_HASH_SIZE];
99 void __atomic_fault_unlock(int *irqlock_word)
101 BUG_ON(!is_atomic_lock(irqlock_word));
102 BUG_ON(*irqlock_word != 1);
106 #endif /* CONFIG_SMP */
108 static inline int *__atomic_setup(volatile void *v)
110 /* Issue a load to the target to bring it into cache. */
112 return __atomic_hashed_lock(v);
115 int _atomic_xchg(atomic_t *v, int n)
117 return __atomic_xchg(&v->counter, __atomic_setup(v), n).val;
119 EXPORT_SYMBOL(_atomic_xchg);
121 int _atomic_xchg_add(atomic_t *v, int i)
123 return __atomic_xchg_add(&v->counter, __atomic_setup(v), i).val;
125 EXPORT_SYMBOL(_atomic_xchg_add);
127 int _atomic_xchg_add_unless(atomic_t *v, int a, int u)
130 * Note: argument order is switched here since it is easier
131 * to use the first argument consistently as the "old value"
132 * in the assembly, as is done for _atomic_cmpxchg().
134 return __atomic_xchg_add_unless(&v->counter, __atomic_setup(v), u, a)
137 EXPORT_SYMBOL(_atomic_xchg_add_unless);
139 int _atomic_cmpxchg(atomic_t *v, int o, int n)
141 return __atomic_cmpxchg(&v->counter, __atomic_setup(v), o, n).val;
143 EXPORT_SYMBOL(_atomic_cmpxchg);
145 unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask)
147 return __atomic_or((int *)p, __atomic_setup(p), mask).val;
149 EXPORT_SYMBOL(_atomic_or);
151 unsigned long _atomic_andn(volatile unsigned long *p, unsigned long mask)
153 return __atomic_andn((int *)p, __atomic_setup(p), mask).val;
155 EXPORT_SYMBOL(_atomic_andn);
157 unsigned long _atomic_xor(volatile unsigned long *p, unsigned long mask)
159 return __atomic_xor((int *)p, __atomic_setup(p), mask).val;
161 EXPORT_SYMBOL(_atomic_xor);
164 u64 _atomic64_xchg(atomic64_t *v, u64 n)
166 return __atomic64_xchg(&v->counter, __atomic_setup(v), n);
168 EXPORT_SYMBOL(_atomic64_xchg);
170 u64 _atomic64_xchg_add(atomic64_t *v, u64 i)
172 return __atomic64_xchg_add(&v->counter, __atomic_setup(v), i);
174 EXPORT_SYMBOL(_atomic64_xchg_add);
176 u64 _atomic64_xchg_add_unless(atomic64_t *v, u64 a, u64 u)
179 * Note: argument order is switched here since it is easier
180 * to use the first argument consistently as the "old value"
181 * in the assembly, as is done for _atomic_cmpxchg().
183 return __atomic64_xchg_add_unless(&v->counter, __atomic_setup(v),
186 EXPORT_SYMBOL(_atomic64_xchg_add_unless);
188 u64 _atomic64_cmpxchg(atomic64_t *v, u64 o, u64 n)
190 return __atomic64_cmpxchg(&v->counter, __atomic_setup(v), o, n);
192 EXPORT_SYMBOL(_atomic64_cmpxchg);
195 static inline int *__futex_setup(int __user *v)
198 * Issue a prefetch to the counter to bring it into cache.
199 * As for __atomic_setup, but we can't do a read into the L1
200 * since it might fault; instead we do a prefetch into the L2.
203 return __atomic_hashed_lock((int __force *)v);
206 struct __get_user futex_set(int __user *v, int i)
208 return __atomic_xchg((int __force *)v, __futex_setup(v), i);
211 struct __get_user futex_add(int __user *v, int n)
213 return __atomic_xchg_add((int __force *)v, __futex_setup(v), n);
216 struct __get_user futex_or(int __user *v, int n)
218 return __atomic_or((int __force *)v, __futex_setup(v), n);
221 struct __get_user futex_andn(int __user *v, int n)
223 return __atomic_andn((int __force *)v, __futex_setup(v), n);
226 struct __get_user futex_xor(int __user *v, int n)
228 return __atomic_xor((int __force *)v, __futex_setup(v), n);
231 struct __get_user futex_cmpxchg(int __user *v, int o, int n)
233 return __atomic_cmpxchg((int __force *)v, __futex_setup(v), o, n);
237 * If any of the atomic or futex routines hit a bad address (not in
238 * the page tables at kernel PL) this routine is called. The futex
239 * routines are never used on kernel space, and the normal atomics and
240 * bitops are never used on user space. So a fault on kernel space
241 * must be fatal, but a fault on userspace is a futex fault and we
242 * need to return -EFAULT. Note that the context this routine is
243 * invoked in is the context of the "_atomic_xxx()" routines called
244 * by the functions in this file.
246 struct __get_user __atomic_bad_address(int __user *addr)
248 if (unlikely(!access_ok(VERIFY_WRITE, addr, sizeof(int))))
249 panic("Bad address used for kernel atomic op: %p\n", addr);
250 return (struct __get_user) { .err = -EFAULT };
254 #if CHIP_HAS_CBOX_HOME_MAP()
255 static int __init noatomichash(char *str)
257 pr_warning("noatomichash is deprecated.\n");
260 __setup("noatomichash", noatomichash);
263 void __init __init_atomic_per_cpu(void)
265 #if ATOMIC_LOCKS_FOUND_VIA_TABLE()
271 * Before this is called from setup, we just have one lock for
272 * all atomic objects/operations. Here we replace the
273 * elements of atomic_lock_ptr so that they point at per_cpu
274 * integers. This seemingly over-complex approach stems from
275 * the fact that DEFINE_PER_CPU defines an entry for each cpu
276 * in the grid, not each cpu from 0..ATOMIC_HASH_SIZE-1. But
277 * for efficient hashing of atomics to their locks we want a
278 * compile time constant power of 2 for the size of this
279 * table, so we use ATOMIC_HASH_SIZE.
281 * Here we populate atomic_lock_ptr from the per cpu
282 * atomic_lock_pool, interspersing by actual cpu so that
283 * subsequent elements are homed on consecutive cpus.
286 actual_cpu = cpumask_first(cpu_possible_mask);
288 for (i = 0; i < ATOMIC_HASH_L1_SIZE; ++i) {
290 * Preincrement to slightly bias against using cpu 0,
291 * which has plenty of stuff homed on it already.
293 actual_cpu = cpumask_next(actual_cpu, cpu_possible_mask);
294 if (actual_cpu >= nr_cpu_ids)
295 actual_cpu = cpumask_first(cpu_possible_mask);
297 atomic_lock_ptr[i] = &per_cpu(atomic_lock_pool, actual_cpu);
300 #else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
302 /* Validate power-of-two and "bigger than cpus" assumption */
303 BUILD_BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1));
304 BUG_ON(ATOMIC_HASH_SIZE < nr_cpu_ids);
307 * On TILEPro we prefer to use a single hash-for-home
308 * page, since this means atomic operations are less
309 * likely to encounter a TLB fault and thus should
310 * in general perform faster. You may wish to disable
311 * this in situations where few hash-for-home tiles
314 BUG_ON((unsigned long)atomic_locks % PAGE_SIZE != 0);
316 /* The locks must all fit on one page. */
317 BUILD_BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE);
320 * We use the page offset of the atomic value's address as
321 * an index into atomic_locks, excluding the low 3 bits.
322 * That should not produce more indices than ATOMIC_HASH_SIZE.
324 BUILD_BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE);
326 #endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
328 /* The futex code makes this assumption, so we validate it here. */
329 BUILD_BUG_ON(sizeof(atomic_t) != sizeof(int));