2 * Copyright (C) 1995 Linus Torvalds
3 * Copyright 2010 Tilera Corporation. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for
16 #include <linux/module.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23 #include <linux/ptrace.h>
24 #include <linux/mman.h>
26 #include <linux/hugetlb.h>
27 #include <linux/swap.h>
28 #include <linux/smp.h>
29 #include <linux/init.h>
30 #include <linux/highmem.h>
31 #include <linux/pagemap.h>
32 #include <linux/poison.h>
33 #include <linux/bootmem.h>
34 #include <linux/slab.h>
35 #include <linux/proc_fs.h>
36 #include <linux/efi.h>
37 #include <linux/memory_hotplug.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/processor.h>
41 #include <asm/pgtable.h>
42 #include <asm/pgalloc.h>
44 #include <asm/fixmap.h>
46 #include <asm/tlbflush.h>
47 #include <asm/sections.h>
48 #include <asm/setup.h>
49 #include <asm/homecache.h>
50 #include <hv/hypervisor.h>
51 #include <arch/chip.h>
55 #define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
58 unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE;
59 EXPORT_SYMBOL(VMALLOC_RESERVE);
62 /* Create an L2 page table */
63 static pte_t * __init alloc_pte(void)
65 return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0);
69 * L2 page tables per controller. We allocate these all at once from
70 * the bootmem allocator and store them here. This saves on kernel L2
71 * page table memory, compared to allocating a full 64K page per L2
72 * page table, and also means that in cases where we use huge pages,
73 * we are guaranteed to later be able to shatter those huge pages and
74 * switch to using these page tables instead, without requiring
75 * further allocation. Each l2_ptes[] entry points to the first page
76 * table for the first hugepage-size piece of memory on the
77 * controller; other page tables are just indexed directly, i.e. the
78 * L2 page tables are contiguous in memory for each controller.
80 static pte_t *l2_ptes[MAX_NUMNODES];
81 static int num_l2_ptes[MAX_NUMNODES];
83 static void init_prealloc_ptes(int node, int pages)
85 BUG_ON(pages & (PTRS_PER_PTE - 1));
87 num_l2_ptes[node] = pages;
88 l2_ptes[node] = __alloc_bootmem(pages * sizeof(pte_t),
89 HV_PAGE_TABLE_ALIGN, 0);
93 pte_t *get_prealloc_pte(unsigned long pfn)
95 int node = pfn_to_nid(pfn);
96 pfn &= ~(-1UL << (NR_PA_HIGHBIT_SHIFT - PAGE_SHIFT));
97 BUG_ON(node >= MAX_NUMNODES);
98 BUG_ON(pfn >= num_l2_ptes[node]);
99 return &l2_ptes[node][pfn];
103 * What caching do we expect pages from the heap to have when
104 * they are allocated during bootup? (Once we've installed the
105 * "real" swapper_pg_dir.)
107 static int initial_heap_home(void)
109 #if CHIP_HAS_CBOX_HOME_MAP()
111 return PAGE_HOME_HASH;
113 return smp_processor_id();
117 * Place a pointer to an L2 page table in a middle page
120 static void __init assign_pte(pmd_t *pmd, pte_t *page_table)
122 phys_addr_t pa = __pa(page_table);
123 unsigned long l2_ptfn = pa >> HV_LOG2_PAGE_TABLE_ALIGN;
124 pte_t pteval = hv_pte_set_ptfn(__pgprot(_PAGE_TABLE), l2_ptfn);
125 BUG_ON((pa & (HV_PAGE_TABLE_ALIGN-1)) != 0);
126 pteval = pte_set_home(pteval, initial_heap_home());
127 *(pte_t *)pmd = pteval;
128 if (page_table != (pte_t *)pmd_page_vaddr(*pmd))
134 static inline pmd_t *alloc_pmd(void)
136 return __alloc_bootmem(L1_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0);
139 static inline void assign_pmd(pud_t *pud, pmd_t *pmd)
141 assign_pte((pmd_t *)pud, (pte_t *)pmd);
144 #endif /* __tilegx__ */
146 /* Replace the given pmd with a full PTE table. */
147 void __init shatter_pmd(pmd_t *pmd)
149 pte_t *pte = get_prealloc_pte(pte_pfn(*(pte_t *)pmd));
150 assign_pte(pmd, pte);
154 static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
156 pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
158 assign_pmd(pud, alloc_pmd());
159 return pmd_offset(pud, va);
162 static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
164 return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
169 * This function initializes a certain range of kernel virtual memory
170 * with new bootmem page tables, everywhere page tables are missing in
175 * NOTE: The pagetables are allocated contiguous on the physical space
176 * so we can cache the place of the first one and move around without
177 * checking the pgd every time.
179 static void __init page_table_range_init(unsigned long start,
180 unsigned long end, pgd_t *pgd)
183 start = round_down(start, PMD_SIZE);
184 end = round_up(end, PMD_SIZE);
185 for (vaddr = start; vaddr < end; vaddr += PMD_SIZE) {
186 pmd_t *pmd = get_pmd(pgd, vaddr);
188 assign_pte(pmd, alloc_pte());
193 #if CHIP_HAS_CBOX_HOME_MAP()
195 static int __initdata ktext_hash = 1; /* .text pages */
196 static int __initdata kdata_hash = 1; /* .data and .bss pages */
197 int __write_once hash_default = 1; /* kernel allocator pages */
198 EXPORT_SYMBOL(hash_default);
199 int __write_once kstack_hash = 1; /* if no homecaching, use h4h */
200 #endif /* CHIP_HAS_CBOX_HOME_MAP */
203 * CPUs to use to for striping the pages of kernel data. If hash-for-home
204 * is available, this is only relevant if kcache_hash sets up the
205 * .data and .bss to be page-homed, and we don't want the default mode
206 * of using the full set of kernel cpus for the striping.
208 static __initdata struct cpumask kdata_mask;
209 static __initdata int kdata_arg_seen;
211 int __write_once kdata_huge; /* if no homecaching, small pages */
214 /* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */
215 static pgprot_t __init construct_pgprot(pgprot_t prot, int home)
217 prot = pte_set_home(prot, home);
218 #if CHIP_HAS_CBOX_HOME_MAP()
219 if (home == PAGE_HOME_IMMUTABLE) {
221 prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_HASH_L3);
223 prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_NO_L3);
230 * For a given kernel data VA, how should it be cached?
231 * We return the complete pgprot_t with caching bits set.
233 static pgprot_t __init init_pgprot(ulong address)
237 enum { CODE_DELTA = MEM_SV_INTRPT - PAGE_OFFSET };
239 #if CHIP_HAS_CBOX_HOME_MAP()
240 /* For kdata=huge, everything is just hash-for-home. */
242 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
245 /* We map the aliased pages of permanent text inaccessible. */
246 if (address < (ulong) _sinittext - CODE_DELTA)
250 * We map read-only data non-coherent for performance. We could
251 * use neighborhood caching on TILE64, but it's not clear it's a win.
253 if ((address >= (ulong) __start_rodata &&
254 address < (ulong) __end_rodata) ||
255 address == (ulong) empty_zero_page) {
256 return construct_pgprot(PAGE_KERNEL_RO, PAGE_HOME_IMMUTABLE);
260 #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
261 /* Force the atomic_locks[] array page to be hash-for-home. */
262 if (address == (ulong) atomic_locks)
263 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
268 * Everything else that isn't data or bss is heap, so mark it
269 * with the initial heap home (hash-for-home, or this cpu). This
270 * includes any addresses after the loaded image and any address before
271 * _einitdata, since we already captured the case of text before
272 * _sinittext, and __pa(einittext) is approximately __pa(sinitdata).
274 * All the LOWMEM pages that we mark this way will get their
275 * struct page homecache properly marked later, in set_page_homes().
276 * The HIGHMEM pages we leave with a default zero for their
277 * homes, but with a zero free_time we don't have to actually
278 * do a flush action the first time we use them, either.
280 if (address >= (ulong) _end || address < (ulong) _einitdata)
281 return construct_pgprot(PAGE_KERNEL, initial_heap_home());
283 #if CHIP_HAS_CBOX_HOME_MAP()
284 /* Use hash-for-home if requested for data/bss. */
286 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
290 * Make the w1data homed like heap to start with, to avoid
291 * making it part of the page-striped data area when we're just
292 * going to convert it to read-only soon anyway.
294 if (address >= (ulong)__w1data_begin && address < (ulong)__w1data_end)
295 return construct_pgprot(PAGE_KERNEL, initial_heap_home());
298 * Otherwise we just hand out consecutive cpus. To avoid
299 * requiring this function to hold state, we just walk forward from
300 * _sdata by PAGE_SIZE, skipping the readonly and init data, to reach
301 * the requested address, while walking cpu home around kdata_mask.
302 * This is typically no more than a dozen or so iterations.
304 page = (((ulong)__w1data_end) + PAGE_SIZE - 1) & PAGE_MASK;
305 BUG_ON(address < page || address >= (ulong)_end);
306 cpu = cpumask_first(&kdata_mask);
307 for (; page < address; page += PAGE_SIZE) {
308 if (page >= (ulong)&init_thread_union &&
309 page < (ulong)&init_thread_union + THREAD_SIZE)
311 if (page == (ulong)empty_zero_page)
314 #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
315 if (page == (ulong)atomic_locks)
319 cpu = cpumask_next(cpu, &kdata_mask);
321 cpu = cpumask_first(&kdata_mask);
323 return construct_pgprot(PAGE_KERNEL, cpu);
327 * This function sets up how we cache the kernel text. If we have
328 * hash-for-home support, normally that is used instead (see the
329 * kcache_hash boot flag for more information). But if we end up
330 * using a page-based caching technique, this option sets up the
331 * details of that. In addition, the "ktext=nocache" option may
332 * always be used to disable local caching of text pages, if desired.
335 static int __initdata ktext_arg_seen;
336 static int __initdata ktext_small;
337 static int __initdata ktext_local;
338 static int __initdata ktext_all;
339 static int __initdata ktext_nondataplane;
340 static int __initdata ktext_nocache;
341 static struct cpumask __initdata ktext_mask;
343 static int __init setup_ktext(char *str)
348 /* If you have a leading "nocache", turn off ktext caching */
349 if (strncmp(str, "nocache", 7) == 0) {
351 pr_info("ktext: disabling local caching of kernel text\n");
361 /* Default setting on Tile64: use a huge page */
362 if (strcmp(str, "huge") == 0)
363 pr_info("ktext: using one huge locally cached page\n");
365 /* Pay TLB cost but get no cache benefit: cache small pages locally */
366 else if (strcmp(str, "local") == 0) {
369 pr_info("ktext: using small pages with local caching\n");
372 /* Neighborhood cache ktext pages on all cpus. */
373 else if (strcmp(str, "all") == 0) {
376 pr_info("ktext: using maximal caching neighborhood\n");
380 /* Neighborhood ktext pages on specified mask */
381 else if (cpulist_parse(str, &ktext_mask) == 0) {
382 char buf[NR_CPUS * 5];
383 cpulist_scnprintf(buf, sizeof(buf), &ktext_mask);
384 if (cpumask_weight(&ktext_mask) > 1) {
386 pr_info("ktext: using caching neighborhood %s "
387 "with small pages\n", buf);
389 pr_info("ktext: caching on cpu %s with one huge page\n",
400 early_param("ktext", setup_ktext);
403 static inline pgprot_t ktext_set_nocache(pgprot_t prot)
406 prot = hv_pte_set_nc(prot);
407 #if CHIP_HAS_NC_AND_NOALLOC_BITS()
409 prot = hv_pte_set_no_alloc_l2(prot);
414 /* Temporary page table we use for staging. */
415 static pgd_t pgtables[PTRS_PER_PGD]
416 __attribute__((aligned(HV_PAGE_TABLE_ALIGN)));
419 * This maps the physical memory to kernel virtual address space, a total
420 * of max_low_pfn pages, by creating page tables starting from address
423 * This routine transitions us from using a set of compiled-in large
424 * pages to using some more precise caching, including removing access
425 * to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START)
426 * marking read-only data as locally cacheable, striping the remaining
427 * .data and .bss across all the available tiles, and removing access
428 * to pages above the top of RAM (thus ensuring a page fault from a bad
429 * virtual address rather than a hypervisor shoot down for accessing
430 * memory outside the assigned limits).
432 static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
434 unsigned long long irqmask;
435 unsigned long address, pfn;
439 const struct cpumask *my_cpu_mask = cpumask_of(smp_processor_id());
440 struct cpumask kstripe_mask;
443 #if CHIP_HAS_CBOX_HOME_MAP()
444 if (ktext_arg_seen && ktext_hash) {
445 pr_warning("warning: \"ktext\" boot argument ignored"
446 " if \"kcache_hash\" sets up text hash-for-home\n");
450 if (kdata_arg_seen && kdata_hash) {
451 pr_warning("warning: \"kdata\" boot argument ignored"
452 " if \"kcache_hash\" sets up data hash-for-home\n");
455 if (kdata_huge && !hash_default) {
456 pr_warning("warning: disabling \"kdata=huge\"; requires"
457 " kcache_hash=all or =allbutstack\n");
463 * Set up a mask for cpus to use for kernel striping.
464 * This is normally all cpus, but minus dataplane cpus if any.
465 * If the dataplane covers the whole chip, we stripe over
466 * the whole chip too.
468 cpumask_copy(&kstripe_mask, cpu_possible_mask);
470 kdata_mask = kstripe_mask;
472 /* Allocate and fill in L2 page tables */
473 for (i = 0; i < MAX_NUMNODES; ++i) {
474 #ifdef CONFIG_HIGHMEM
475 unsigned long end_pfn = node_lowmem_end_pfn[i];
477 unsigned long end_pfn = node_end_pfn[i];
479 unsigned long end_huge_pfn = 0;
481 /* Pre-shatter the last huge page to allow per-cpu pages. */
483 end_huge_pfn = end_pfn - (HPAGE_SIZE >> PAGE_SHIFT);
485 pfn = node_start_pfn[i];
487 /* Allocate enough memory to hold L2 page tables for node. */
488 init_prealloc_ptes(i, end_pfn - pfn);
490 address = (unsigned long) pfn_to_kaddr(pfn);
491 while (pfn < end_pfn) {
492 BUG_ON(address & (HPAGE_SIZE-1));
493 pmd = get_pmd(pgtables, address);
494 pte = get_prealloc_pte(pfn);
495 if (pfn < end_huge_pfn) {
496 pgprot_t prot = init_pgprot(address);
497 *(pte_t *)pmd = pte_mkhuge(pfn_pte(pfn, prot));
498 for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
499 pfn++, pte_ofs++, address += PAGE_SIZE)
500 pte[pte_ofs] = pfn_pte(pfn, prot);
503 printk(KERN_DEBUG "pre-shattered huge"
504 " page at %#lx\n", address);
505 for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
506 pfn++, pte_ofs++, address += PAGE_SIZE) {
507 pgprot_t prot = init_pgprot(address);
508 pte[pte_ofs] = pfn_pte(pfn, prot);
510 assign_pte(pmd, pte);
516 * Set or check ktext_map now that we have cpu_possible_mask
517 * and kstripe_mask to work with.
520 cpumask_copy(&ktext_mask, cpu_possible_mask);
521 else if (ktext_nondataplane)
522 ktext_mask = kstripe_mask;
523 else if (!cpumask_empty(&ktext_mask)) {
524 /* Sanity-check any mask that was requested */
526 cpumask_andnot(&bad, &ktext_mask, cpu_possible_mask);
527 cpumask_and(&ktext_mask, &ktext_mask, cpu_possible_mask);
528 if (!cpumask_empty(&bad)) {
529 char buf[NR_CPUS * 5];
530 cpulist_scnprintf(buf, sizeof(buf), &bad);
531 pr_info("ktext: not using unavailable cpus %s\n", buf);
533 if (cpumask_empty(&ktext_mask)) {
534 pr_warning("ktext: no valid cpus; caching on %d.\n",
536 cpumask_copy(&ktext_mask,
537 cpumask_of(smp_processor_id()));
541 address = MEM_SV_INTRPT;
542 pmd = get_pmd(pgtables, address);
543 pfn = 0; /* code starts at PA 0 */
545 /* Allocate an L2 PTE for the kernel text */
547 pgprot_t prot = construct_pgprot(PAGE_KERNEL_EXEC,
548 PAGE_HOME_IMMUTABLE);
552 prot = hv_pte_set_mode(prot,
553 HV_PTE_MODE_UNCACHED);
555 prot = hv_pte_set_mode(prot,
556 HV_PTE_MODE_CACHE_NO_L3);
558 prot = hv_pte_set_mode(prot,
559 HV_PTE_MODE_CACHE_TILE_L3);
560 cpu = cpumask_first(&ktext_mask);
562 prot = ktext_set_nocache(prot);
565 BUG_ON(address != (unsigned long)_text);
567 for (; address < (unsigned long)_einittext;
568 pfn++, address += PAGE_SIZE) {
569 pte_ofs = pte_index(address);
572 assign_pte(pmd++, pte);
576 prot = set_remote_cache_cpu(prot, cpu);
577 cpu = cpumask_next(cpu, &ktext_mask);
579 cpu = cpumask_first(&ktext_mask);
581 pte[pte_ofs] = pfn_pte(pfn, prot);
584 assign_pte(pmd, pte);
586 pte_t pteval = pfn_pte(0, PAGE_KERNEL_EXEC);
587 pteval = pte_mkhuge(pteval);
588 #if CHIP_HAS_CBOX_HOME_MAP()
590 pteval = hv_pte_set_mode(pteval,
591 HV_PTE_MODE_CACHE_HASH_L3);
592 pteval = ktext_set_nocache(pteval);
594 #endif /* CHIP_HAS_CBOX_HOME_MAP() */
595 if (cpumask_weight(&ktext_mask) == 1) {
596 pteval = set_remote_cache_cpu(pteval,
597 cpumask_first(&ktext_mask));
598 pteval = hv_pte_set_mode(pteval,
599 HV_PTE_MODE_CACHE_TILE_L3);
600 pteval = ktext_set_nocache(pteval);
601 } else if (ktext_nocache)
602 pteval = hv_pte_set_mode(pteval,
603 HV_PTE_MODE_UNCACHED);
605 pteval = hv_pte_set_mode(pteval,
606 HV_PTE_MODE_CACHE_NO_L3);
607 for (; address < (unsigned long)_einittext;
608 pfn += PFN_DOWN(HPAGE_SIZE), address += HPAGE_SIZE)
609 *(pte_t *)(pmd++) = pfn_pte(pfn, pteval);
612 /* Set swapper_pgprot here so it is flushed to memory right away. */
613 swapper_pgprot = init_pgprot((unsigned long)swapper_pg_dir);
616 * Since we may be changing the caching of the stack and page
617 * table itself, we invoke an assembly helper to do the
620 * - flush the cache so we start with an empty slate
621 * - install pgtables[] as the real page table
622 * - flush the TLB so the new page table takes effect
624 irqmask = interrupt_mask_save_mask();
625 interrupt_mask_set_mask(-1ULL);
626 rc = flush_and_install_context(__pa(pgtables),
627 init_pgprot((unsigned long)pgtables),
628 __get_cpu_var(current_asid),
629 cpumask_bits(my_cpu_mask));
630 interrupt_mask_restore_mask(irqmask);
633 /* Copy the page table back to the normal swapper_pg_dir. */
634 memcpy(pgd_base, pgtables, sizeof(pgtables));
635 __install_page_table(pgd_base, __get_cpu_var(current_asid),
639 * We just read swapper_pgprot and thus brought it into the cache,
640 * with its new home & caching mode. When we start the other CPUs,
641 * they're going to reference swapper_pgprot via their initial fake
642 * VA-is-PA mappings, which cache everything locally. At that
643 * time, if it's in our cache with a conflicting home, the
644 * simulator's coherence checker will complain. So, flush it out
645 * of our cache; we're not going to ever use it again anyway.
647 __insn_finv(&swapper_pgprot);
651 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
652 * is valid. The argument is a physical page number.
654 * On Tile, the only valid things for which we can just hand out unchecked
655 * PTEs are the kernel code and data. Anything else might change its
656 * homing with time, and we wouldn't know to adjust the /dev/mem PTEs.
657 * Note that init_thread_union is released to heap soon after boot,
658 * so we include it in the init data.
660 * For TILE-Gx, we might want to consider allowing access to PA
661 * regions corresponding to PCI space, etc.
663 int devmem_is_allowed(unsigned long pagenr)
665 return pagenr < kaddr_to_pfn(_end) &&
666 !(pagenr >= kaddr_to_pfn(&init_thread_union) ||
667 pagenr < kaddr_to_pfn(_einitdata)) &&
668 !(pagenr >= kaddr_to_pfn(_sinittext) ||
669 pagenr <= kaddr_to_pfn(_einittext-1));
672 #ifdef CONFIG_HIGHMEM
673 static void __init permanent_kmaps_init(pgd_t *pgd_base)
682 page_table_range_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
684 pgd = swapper_pg_dir + pgd_index(vaddr);
685 pud = pud_offset(pgd, vaddr);
686 pmd = pmd_offset(pud, vaddr);
687 pte = pte_offset_kernel(pmd, vaddr);
688 pkmap_page_table = pte;
690 #endif /* CONFIG_HIGHMEM */
694 static void __init init_free_pfn_range(unsigned long start, unsigned long end)
697 struct page *page = pfn_to_page(start);
699 for (pfn = start; pfn < end; ) {
700 /* Optimize by freeing pages in large batches */
701 int order = __ffs(pfn);
705 if (order >= MAX_ORDER)
708 while (pfn + count > end) {
712 for (p = page, i = 0; i < count; ++i, ++p) {
713 __ClearPageReserved(p);
715 * Hacky direct set to avoid unnecessary
716 * lock take/release for EVERY page here.
718 p->_count.counter = 0;
719 p->_mapcount.counter = -1;
721 init_page_count(page);
722 __free_pages(page, order);
723 adjust_managed_page_count(page, count);
730 static void __init set_non_bootmem_pages_init(void)
734 unsigned long start, end;
735 int nid = z->zone_pgdat->node_id;
736 #ifdef CONFIG_HIGHMEM
737 int idx = zone_idx(z);
740 start = z->zone_start_pfn;
741 end = start + z->spanned_pages;
742 start = max(start, node_free_pfn[nid]);
743 start = max(start, max_low_pfn);
745 #ifdef CONFIG_HIGHMEM
746 if (idx == ZONE_HIGHMEM)
747 totalhigh_pages += z->spanned_pages;
750 unsigned long percpu_pfn = node_percpu_pfn[nid];
751 if (start < percpu_pfn && end > percpu_pfn)
755 if (start <= pci_reserve_start_pfn &&
756 end > pci_reserve_start_pfn) {
757 if (end > pci_reserve_end_pfn)
758 init_free_pfn_range(pci_reserve_end_pfn, end);
759 end = pci_reserve_start_pfn;
762 init_free_pfn_range(start, end);
768 * paging_init() sets up the page tables - note that all of lowmem is
769 * already mapped by head.S.
771 void __init paging_init(void)
776 pgd_t *pgd_base = swapper_pg_dir;
778 kernel_physical_mapping_init(pgd_base);
781 * Fixed mappings, only the page table structure has to be
782 * created - mappings will be set by set_fixmap():
784 page_table_range_init(fix_to_virt(__end_of_fixed_addresses - 1),
785 FIXADDR_TOP, pgd_base);
787 #ifdef CONFIG_HIGHMEM
788 permanent_kmaps_init(pgd_base);
793 * Since GX allocates just one pmd_t array worth of vmalloc space,
794 * we go ahead and allocate it statically here, then share it
795 * globally. As a result we don't have to worry about any task
796 * changing init_mm once we get up and running, and there's no
797 * need for e.g. vmalloc_sync_all().
799 BUILD_BUG_ON(pgd_index(VMALLOC_START) != pgd_index(VMALLOC_END - 1));
800 pud = pud_offset(pgd_base + pgd_index(VMALLOC_START), VMALLOC_START);
801 assign_pmd(pud, alloc_pmd());
807 * Walk the kernel page tables and derive the page_home() from
808 * the PTEs, so that set_pte() can properly validate the caching
809 * of all PTEs it sees.
811 void __init set_page_homes(void)
815 static void __init set_max_mapnr_init(void)
817 #ifdef CONFIG_FLATMEM
818 max_mapnr = max_low_pfn;
822 void __init mem_init(void)
829 #ifdef CONFIG_FLATMEM
833 #ifdef CONFIG_HIGHMEM
834 /* check that fixmap and pkmap do not overlap */
835 if (PKMAP_ADDR(LAST_PKMAP-1) >= FIXADDR_START) {
836 pr_err("fixmap and kmap areas overlap"
837 " - this will crash\n");
838 pr_err("pkstart: %lxh pkend: %lxh fixstart %lxh\n",
839 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP-1),
845 set_max_mapnr_init();
847 /* this will put all bootmem onto the freelists */
851 /* count all remaining LOWMEM and give all HIGHMEM to page allocator */
852 set_non_bootmem_pages_init();
855 mem_init_print_info(NULL);
858 * In debug mode, dump some interesting memory mappings.
860 #ifdef CONFIG_HIGHMEM
861 printk(KERN_DEBUG " KMAP %#lx - %#lx\n",
862 FIXADDR_START, FIXADDR_TOP + PAGE_SIZE - 1);
863 printk(KERN_DEBUG " PKMAP %#lx - %#lx\n",
864 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP) - 1);
866 #ifdef CONFIG_HUGEVMAP
867 printk(KERN_DEBUG " HUGEMAP %#lx - %#lx\n",
868 HUGE_VMAP_BASE, HUGE_VMAP_END - 1);
870 printk(KERN_DEBUG " VMALLOC %#lx - %#lx\n",
871 _VMALLOC_START, _VMALLOC_END - 1);
873 for (i = MAX_NUMNODES-1; i >= 0; --i) {
874 struct pglist_data *node = &node_data[i];
875 if (node->node_present_pages) {
876 unsigned long start = (unsigned long)
877 pfn_to_kaddr(node->node_start_pfn);
878 unsigned long end = start +
879 (node->node_present_pages << PAGE_SHIFT);
880 printk(KERN_DEBUG " MEM%d %#lx - %#lx\n",
886 for (i = MAX_NUMNODES-1; i >= 0; --i) {
887 if ((unsigned long)vbase_map[i] != -1UL) {
888 printk(KERN_DEBUG " LOWMEM%d %#lx - %#lx\n",
889 i, (unsigned long) (vbase_map[i]),
890 (unsigned long) (last-1));
898 * Convert from using one lock for all atomic operations to
901 __init_atomic_per_cpu();
906 * this is for the non-NUMA, single node SMP system case.
907 * Specifically, in the case of x86, we will always add
908 * memory to the highmem for now.
910 #ifndef CONFIG_NEED_MULTIPLE_NODES
911 int arch_add_memory(u64 start, u64 size)
913 struct pglist_data *pgdata = &contig_page_data;
914 struct zone *zone = pgdata->node_zones + MAX_NR_ZONES-1;
915 unsigned long start_pfn = start >> PAGE_SHIFT;
916 unsigned long nr_pages = size >> PAGE_SHIFT;
918 return __add_pages(zone, start_pfn, nr_pages);
921 int remove_memory(u64 start, u64 size)
926 #ifdef CONFIG_MEMORY_HOTREMOVE
927 int arch_remove_memory(u64 start, u64 size)
935 struct kmem_cache *pgd_cache;
937 void __init pgtable_cache_init(void)
939 pgd_cache = kmem_cache_create("pgd", SIZEOF_PGD, SIZEOF_PGD, 0, NULL);
941 panic("pgtable_cache_init(): Cannot create pgd cache");
944 #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
946 * The __w1data area holds data that is only written during initialization,
947 * and is read-only and thus freely cacheable thereafter. Fix the page
948 * table entries that cover that region accordingly.
950 static void mark_w1data_ro(void)
952 /* Loop over page table entries */
953 unsigned long addr = (unsigned long)__w1data_begin;
954 BUG_ON((addr & (PAGE_SIZE-1)) != 0);
955 for (; addr <= (unsigned long)__w1data_end - 1; addr += PAGE_SIZE) {
956 unsigned long pfn = kaddr_to_pfn((void *)addr);
957 pte_t *ptep = virt_to_pte(NULL, addr);
958 BUG_ON(pte_huge(*ptep)); /* not relevant for kdata_huge */
959 set_pte_at(&init_mm, addr, ptep, pfn_pte(pfn, PAGE_KERNEL_RO));
964 #ifdef CONFIG_DEBUG_PAGEALLOC
965 static long __write_once initfree;
967 static long __write_once initfree = 1;
970 /* Select whether to free (1) or mark unusable (0) the __init pages. */
971 static int __init set_initfree(char *str)
974 if (strict_strtol(str, 0, &val) == 0) {
976 pr_info("initfree: %s free init pages\n",
977 initfree ? "will" : "won't");
981 __setup("initfree=", set_initfree);
983 static void free_init_pages(char *what, unsigned long begin, unsigned long end)
985 unsigned long addr = (unsigned long) begin;
987 if (kdata_huge && !initfree) {
988 pr_warning("Warning: ignoring initfree=0:"
989 " incompatible with kdata=huge\n");
992 end = (end + PAGE_SIZE - 1) & PAGE_MASK;
993 local_flush_tlb_pages(NULL, begin, PAGE_SIZE, end - begin);
994 for (addr = begin; addr < end; addr += PAGE_SIZE) {
996 * Note we just reset the home here directly in the
997 * page table. We know this is safe because our caller
998 * just flushed the caches on all the other cpus,
999 * and they won't be touching any of these pages.
1001 int pfn = kaddr_to_pfn((void *)addr);
1002 struct page *page = pfn_to_page(pfn);
1003 pte_t *ptep = virt_to_pte(NULL, addr);
1006 * If debugging page accesses then do not free
1007 * this memory but mark them not present - any
1008 * buggy init-section access will create a
1009 * kernel page fault:
1011 pte_clear(&init_mm, addr, ptep);
1014 if (pte_huge(*ptep))
1015 BUG_ON(!kdata_huge);
1017 set_pte_at(&init_mm, addr, ptep,
1018 pfn_pte(pfn, PAGE_KERNEL));
1019 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1020 free_reserved_page(page);
1022 pr_info("Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
1025 void free_initmem(void)
1027 const unsigned long text_delta = MEM_SV_INTRPT - PAGE_OFFSET;
1030 * Evict the dirty initdata on the boot cpu, evict the w1data
1031 * wherever it's homed, and evict all the init code everywhere.
1032 * We are guaranteed that no one will touch the init pages any
1033 * more, and although other cpus may be touching the w1data,
1034 * we only actually change the caching on tile64, which won't
1035 * be keeping local copies in the other tiles' caches anyway.
1037 homecache_evict(&cpu_cacheable_map);
1039 /* Free the data pages that we won't use again after init. */
1040 free_init_pages("unused kernel data",
1041 (unsigned long)_sinitdata,
1042 (unsigned long)_einitdata);
1045 * Free the pages mapped from 0xc0000000 that correspond to code
1046 * pages from MEM_SV_INTRPT that we won't use again after init.
1048 free_init_pages("unused kernel text",
1049 (unsigned long)_sinittext - text_delta,
1050 (unsigned long)_einittext - text_delta);
1052 #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
1054 * Upgrade the .w1data section to globally cached.
1055 * We don't do this on tilepro, since the cache architecture
1056 * pretty much makes it irrelevant, and in any case we end
1057 * up having racing issues with other tiles that may touch
1058 * the data after we flush the cache but before we update
1059 * the PTEs and flush the TLBs, causing sharer shootdowns
1060 * later. Even though this is to clean data, it seems like
1061 * an unnecessary complication.
1066 /* Do a global TLB flush so everyone sees the changes. */