1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_COREBOOT
17 config VENDOR_EMULATION
28 # board-specific options below
29 source "board/coreboot/Kconfig"
30 source "board/efi/Kconfig"
31 source "board/emulation/Kconfig"
32 source "board/google/Kconfig"
33 source "board/intel/Kconfig"
35 # platform-specific options below
36 source "arch/x86/cpu/baytrail/Kconfig"
37 source "arch/x86/cpu/broadwell/Kconfig"
38 source "arch/x86/cpu/coreboot/Kconfig"
39 source "arch/x86/cpu/ivybridge/Kconfig"
40 source "arch/x86/cpu/qemu/Kconfig"
41 source "arch/x86/cpu/quark/Kconfig"
42 source "arch/x86/cpu/queensbay/Kconfig"
44 # architecture-specific options below
46 config SYS_MALLOC_F_LEN
55 depends on X86_RESET_VECTOR
64 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
73 config X86_RESET_VECTOR
77 config RESET_SEG_START
79 depends on X86_RESET_VECTOR
84 depends on X86_RESET_VECTOR
89 depends on X86_RESET_VECTOR
92 config SYS_X86_START16
94 depends on X86_RESET_VECTOR
97 config BOARD_ROMSIZE_KB_512
99 config BOARD_ROMSIZE_KB_1024
101 config BOARD_ROMSIZE_KB_2048
103 config BOARD_ROMSIZE_KB_4096
105 config BOARD_ROMSIZE_KB_8192
107 config BOARD_ROMSIZE_KB_16384
111 prompt "ROM chip size"
112 depends on X86_RESET_VECTOR
113 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
114 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
115 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
116 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
117 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
118 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
120 Select the size of the ROM chip you intend to flash U-Boot on.
122 The build system will take care of creating a u-boot.rom file
123 of the matching size.
125 config UBOOT_ROMSIZE_KB_512
128 Choose this option if you have a 512 KB ROM chip.
130 config UBOOT_ROMSIZE_KB_1024
131 bool "1024 KB (1 MB)"
133 Choose this option if you have a 1024 KB (1 MB) ROM chip.
135 config UBOOT_ROMSIZE_KB_2048
136 bool "2048 KB (2 MB)"
138 Choose this option if you have a 2048 KB (2 MB) ROM chip.
140 config UBOOT_ROMSIZE_KB_4096
141 bool "4096 KB (4 MB)"
143 Choose this option if you have a 4096 KB (4 MB) ROM chip.
145 config UBOOT_ROMSIZE_KB_8192
146 bool "8192 KB (8 MB)"
148 Choose this option if you have a 8192 KB (8 MB) ROM chip.
150 config UBOOT_ROMSIZE_KB_16384
151 bool "16384 KB (16 MB)"
153 Choose this option if you have a 16384 KB (16 MB) ROM chip.
157 # Map the config names to an integer (KB).
158 config UBOOT_ROMSIZE_KB
160 default 512 if UBOOT_ROMSIZE_KB_512
161 default 1024 if UBOOT_ROMSIZE_KB_1024
162 default 2048 if UBOOT_ROMSIZE_KB_2048
163 default 4096 if UBOOT_ROMSIZE_KB_4096
164 default 8192 if UBOOT_ROMSIZE_KB_8192
165 default 16384 if UBOOT_ROMSIZE_KB_16384
167 # Map the config names to a hex value (bytes).
170 default 0x80000 if UBOOT_ROMSIZE_KB_512
171 default 0x100000 if UBOOT_ROMSIZE_KB_1024
172 default 0x200000 if UBOOT_ROMSIZE_KB_2048
173 default 0x400000 if UBOOT_ROMSIZE_KB_4096
174 default 0x800000 if UBOOT_ROMSIZE_KB_8192
175 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
176 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
179 bool "Platform requires Intel Management Engine"
181 Newer higher-end devices have an Intel Management Engine (ME)
182 which is a very large binary blob (typically 1.5MB) which is
183 required for the platform to work. This enforces a particular
184 SPI flash format. You will need to supply the me.bin file in
185 your board directory.
188 bool "Perform a simple RAM test after SDRAM initialisation"
190 If there is something wrong with SDRAM then the platform will
191 often crash within U-Boot or the kernel. This option enables a
192 very simple RAM test that quickly checks whether the SDRAM seems
193 to work correctly. It is not exhaustive but can save time by
194 detecting obvious failures.
197 bool "Add an Firmware Support Package binary"
200 Select this option to add an Firmware Support Package binary to
201 the resulting U-Boot image. It is a binary blob which U-Boot uses
202 to set up SDRAM and other chipset specific initialization.
204 Note: Without this binary U-Boot will not be able to set up its
205 SDRAM so will not boot.
208 string "Firmware Support Package binary filename"
212 The filename of the file to use as Firmware Support Package binary
213 in the board directory.
216 hex "Firmware Support Package binary location"
220 FSP is not Position Independent Code (PIC) and the whole FSP has to
221 be rebased if it is placed at a location which is different from the
222 perferred base address specified during the FSP build. Use Intel's
223 Binary Configuration Tool (BCT) to do the rebase.
225 The default base address of 0xfffc0000 indicates that the binary must
226 be located at offset 0xc0000 from the beginning of a 1MB flash device.
228 config FSP_TEMP_RAM_ADDR
233 Stack top address which is used in fsp_init() after DRAM is ready and
236 config FSP_SYS_MALLOC_F_LEN
241 Additional size of malloc() pool before relocation.
248 Most FSPs use UPD data region for some FSP customization. But there
249 are still some FSPs that might not even have UPD. For such FSPs,
250 override this to n in their platform Kconfig files.
252 config FSP_BROKEN_HOB
256 Indicate some buggy FSPs that does not report memory used by FSP
257 itself as reserved in the resource descriptor HOB. Select this to
258 tell U-Boot to do some additional work to ensure U-Boot relocation
259 do not overwrite the important boot service data which is used by
260 FSP, otherwise the subsequent call to fsp_notify() will fail.
262 config ENABLE_MRC_CACHE
263 bool "Enable MRC cache"
264 depends on !EFI && !SYS_COREBOOT
266 Enable this feature to cause MRC data to be cached in NV storage
267 to be used for speeding up boot time on future reboots and/or
271 bool "Add a System Agent binary"
274 Select this option to add a System Agent binary to
275 the resulting U-Boot image. MRC stands for Memory Reference Code.
276 It is a binary blob which U-Boot uses to set up SDRAM.
278 Note: Without this binary U-Boot will not be able to set up its
279 SDRAM so will not boot.
286 Enable caching for the memory reference code binary. This uses an
287 MTRR (memory type range register) to turn on caching for the section
288 of SPI flash that contains the memory reference code. This makes
289 SDRAM init run faster.
291 config CACHE_MRC_SIZE_KB
296 Sets the size of the cached area for the memory reference code.
297 This ends at the end of SPI flash (address 0xffffffff) and is
298 measured in KB. Typically this is set to 512, providing for 0.5MB
301 config DCACHE_RAM_BASE
305 Sets the base of the data cache area in memory space. This is the
306 start address of the cache-as-RAM (CAR) area and the address varies
307 depending on the CPU. Once CAR is set up, read/write memory becomes
308 available at this address and can be used temporarily until SDRAM
311 config DCACHE_RAM_SIZE
316 Sets the total size of the data cache area in memory space. This
317 sets the size of the cache-as-RAM (CAR) area. Note that much of the
318 CAR space is required by the MRC. The CAR space available to U-Boot
319 is normally at the start and typically extends to 1/4 or 1/2 of the
322 config DCACHE_RAM_MRC_VAR_SIZE
326 This is the amount of CAR (Cache as RAM) reserved for use by the
327 memory reference code. This depends on the implementation of the
328 memory reference code and must be set correctly or the board will
332 bool "Add a Reference Code binary"
334 Select this option to add a Reference Code binary to the resulting
335 U-Boot image. This is an Intel binary blob that handles system
336 initialisation, in this case the PCH and System Agent.
338 Note: Without this binary (on platforms that need it such as
339 broadwell) U-Boot will be missing some critical setup steps.
340 Various peripherals may fail to work.
343 bool "Enable Symmetric Multiprocessing"
346 Enable use of more than one CPU in U-Boot and the Operating System
347 when loaded. Each CPU will be started up and information can be
348 obtained using the 'cpu' command. If this option is disabled, then
349 only one CPU will be enabled regardless of the number of CPUs
353 int "Maximum number of CPUs permitted"
357 When using multi-CPU chips it is possible for U-Boot to start up
358 more than one CPU. The stack memory used by all of these CPUs is
359 pre-allocated so at present U-Boot wants to know the maximum
360 number of CPUs that may be present. Set this to at least as high
361 as the number of CPUs in your system (it uses about 4KB of RAM for
369 Each additional CPU started by U-Boot requires its own stack. This
370 option sets the stack size used by each CPU and directly affects
371 the memory used by this initialisation process. Typically 4KB is
375 bool "Add a VGA BIOS image"
377 Select this option if you have a VGA BIOS image that you would
378 like to add to your ROM.
381 string "VGA BIOS image filename"
382 depends on HAVE_VGA_BIOS
385 The filename of the VGA BIOS image in the board directory.
388 hex "VGA BIOS image location"
389 depends on HAVE_VGA_BIOS
392 The location of VGA BIOS image in the SPI flash. For example, base
393 address of 0xfff90000 indicates that the image will be put at offset
394 0x90000 from the beginning of a 1MB flash device.
397 depends on !EFI && !SYS_COREBOOT
399 config GENERATE_PIRQ_TABLE
400 bool "Generate a PIRQ table"
403 Generate a PIRQ routing table for this board. The PIRQ routing table
404 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
405 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
406 It specifies the interrupt router information as well how all the PCI
407 devices' interrupt pins are wired to PIRQs.
409 config GENERATE_SFI_TABLE
410 bool "Generate a SFI (Simple Firmware Interface) table"
412 The Simple Firmware Interface (SFI) provides a lightweight method
413 for platform firmware to pass information to the operating system
414 via static tables in memory. Kernel SFI support is required to
415 boot on SFI-only platforms. If you have ACPI tables then these are
418 U-Boot writes this table in write_sfi_table() just before booting
421 For more information, see http://simplefirmware.org
423 config GENERATE_MP_TABLE
424 bool "Generate an MP (Multi-Processor) table"
427 Generate an MP (Multi-Processor) table for this board. The MP table
428 provides a way for the operating system to support for symmetric
429 multiprocessing as well as symmetric I/O interrupt handling with
430 the local APIC and I/O APIC.
432 config GENERATE_ACPI_TABLE
433 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
436 The Advanced Configuration and Power Interface (ACPI) specification
437 provides an open standard for device configuration and management
438 by the operating system. It defines platform-independent interfaces
439 for configuration and power management monitoring.
441 config QEMU_ACPI_TABLE
442 bool "Load ACPI table from QEMU fw_cfg interface"
443 depends on GENERATE_ACPI_TABLE && QEMU
446 By default, U-Boot generates its own ACPI tables. This option, if
447 enabled, disables U-Boot's version and loads ACPI tables generated
450 config GENERATE_SMBIOS_TABLE
451 bool "Generate an SMBIOS (System Management BIOS) table"
454 The System Management BIOS (SMBIOS) specification addresses how
455 motherboard and system vendors present management information about
456 their products in a standard format by extending the BIOS interface
457 on Intel architecture systems.
459 Check http://www.dmtf.org/standards/smbios for details.
463 config MAX_PIRQ_LINKS
467 This variable specifies the number of PIRQ interrupt links which are
468 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
469 Some newer chipsets offer more than four links, commonly up to PIRQH.
471 config IRQ_SLOT_COUNT
475 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
476 which in turns forms a table of exact 4KiB. The default value 128
477 should be enough for most boards. If this does not fit your board,
478 change it according to your needs.
480 config PCIE_ECAM_BASE
484 This is the memory-mapped address of PCI configuration space, which
485 is only available through the Enhanced Configuration Access
486 Mechanism (ECAM) with PCI Express. It can be set up almost
487 anywhere. Before it is set up, it is possible to access PCI
488 configuration space through I/O access, but memory access is more
489 convenient. Using this, PCI can be scanned and configured. This
490 should be set to a region that does not conflict with memory
491 assigned to PCI devices - i.e. the memory and prefetch regions, as
492 passed to pci_set_region().
494 config PCIE_ECAM_SIZE
498 This is the size of memory-mapped address of PCI configuration space,
499 which is only available through the Enhanced Configuration Access
500 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
501 so a default 0x10000000 size covers all of the 256 buses which is the
502 maximum number of PCI buses as defined by the PCI specification.
508 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
509 slave) interrupt controllers. Include this to have U-Boot set up
510 the interrupt correctly.
516 Intel 8254 timer contains three counters which have fixed uses.
517 Include this to have U-Boot set up the timer correctly.
526 bool "Support booting SeaBIOS"
528 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
529 It can run in an emulator or natively on X86 hardware with the use
530 of coreboot/U-Boot. By turning on this option, U-Boot prepares
531 all the configuration tables that are necessary to boot SeaBIOS.
533 Check http://www.seabios.org/SeaBIOS for details.
535 source "arch/x86/lib/efi/Kconfig"