1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_CONGATEC
14 config VENDOR_COREBOOT
20 config VENDOR_EMULATION
31 # board-specific options below
32 source "board/congatec/Kconfig"
33 source "board/coreboot/Kconfig"
34 source "board/efi/Kconfig"
35 source "board/emulation/Kconfig"
36 source "board/google/Kconfig"
37 source "board/intel/Kconfig"
39 # platform-specific options below
40 source "arch/x86/cpu/baytrail/Kconfig"
41 source "arch/x86/cpu/broadwell/Kconfig"
42 source "arch/x86/cpu/coreboot/Kconfig"
43 source "arch/x86/cpu/ivybridge/Kconfig"
44 source "arch/x86/cpu/qemu/Kconfig"
45 source "arch/x86/cpu/quark/Kconfig"
46 source "arch/x86/cpu/queensbay/Kconfig"
48 # architecture-specific options below
50 config SYS_MALLOC_F_LEN
59 depends on X86_RESET_VECTOR
68 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
77 config X86_RESET_VECTOR
81 config RESET_SEG_START
83 depends on X86_RESET_VECTOR
88 depends on X86_RESET_VECTOR
93 depends on X86_RESET_VECTOR
96 config SYS_X86_START16
98 depends on X86_RESET_VECTOR
101 config BOARD_ROMSIZE_KB_512
103 config BOARD_ROMSIZE_KB_1024
105 config BOARD_ROMSIZE_KB_2048
107 config BOARD_ROMSIZE_KB_4096
109 config BOARD_ROMSIZE_KB_8192
111 config BOARD_ROMSIZE_KB_16384
115 prompt "ROM chip size"
116 depends on X86_RESET_VECTOR
117 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
118 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
119 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
120 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
121 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
122 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
124 Select the size of the ROM chip you intend to flash U-Boot on.
126 The build system will take care of creating a u-boot.rom file
127 of the matching size.
129 config UBOOT_ROMSIZE_KB_512
132 Choose this option if you have a 512 KB ROM chip.
134 config UBOOT_ROMSIZE_KB_1024
135 bool "1024 KB (1 MB)"
137 Choose this option if you have a 1024 KB (1 MB) ROM chip.
139 config UBOOT_ROMSIZE_KB_2048
140 bool "2048 KB (2 MB)"
142 Choose this option if you have a 2048 KB (2 MB) ROM chip.
144 config UBOOT_ROMSIZE_KB_4096
145 bool "4096 KB (4 MB)"
147 Choose this option if you have a 4096 KB (4 MB) ROM chip.
149 config UBOOT_ROMSIZE_KB_8192
150 bool "8192 KB (8 MB)"
152 Choose this option if you have a 8192 KB (8 MB) ROM chip.
154 config UBOOT_ROMSIZE_KB_16384
155 bool "16384 KB (16 MB)"
157 Choose this option if you have a 16384 KB (16 MB) ROM chip.
161 # Map the config names to an integer (KB).
162 config UBOOT_ROMSIZE_KB
164 default 512 if UBOOT_ROMSIZE_KB_512
165 default 1024 if UBOOT_ROMSIZE_KB_1024
166 default 2048 if UBOOT_ROMSIZE_KB_2048
167 default 4096 if UBOOT_ROMSIZE_KB_4096
168 default 8192 if UBOOT_ROMSIZE_KB_8192
169 default 16384 if UBOOT_ROMSIZE_KB_16384
171 # Map the config names to a hex value (bytes).
174 default 0x80000 if UBOOT_ROMSIZE_KB_512
175 default 0x100000 if UBOOT_ROMSIZE_KB_1024
176 default 0x200000 if UBOOT_ROMSIZE_KB_2048
177 default 0x400000 if UBOOT_ROMSIZE_KB_4096
178 default 0x800000 if UBOOT_ROMSIZE_KB_8192
179 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
180 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
183 bool "Platform requires Intel Management Engine"
185 Newer higher-end devices have an Intel Management Engine (ME)
186 which is a very large binary blob (typically 1.5MB) which is
187 required for the platform to work. This enforces a particular
188 SPI flash format. You will need to supply the me.bin file in
189 your board directory.
192 bool "Perform a simple RAM test after SDRAM initialisation"
194 If there is something wrong with SDRAM then the platform will
195 often crash within U-Boot or the kernel. This option enables a
196 very simple RAM test that quickly checks whether the SDRAM seems
197 to work correctly. It is not exhaustive but can save time by
198 detecting obvious failures.
201 bool "Add an Firmware Support Package binary"
204 Select this option to add an Firmware Support Package binary to
205 the resulting U-Boot image. It is a binary blob which U-Boot uses
206 to set up SDRAM and other chipset specific initialization.
208 Note: Without this binary U-Boot will not be able to set up its
209 SDRAM so will not boot.
212 string "Firmware Support Package binary filename"
216 The filename of the file to use as Firmware Support Package binary
217 in the board directory.
220 hex "Firmware Support Package binary location"
224 FSP is not Position Independent Code (PIC) and the whole FSP has to
225 be rebased if it is placed at a location which is different from the
226 perferred base address specified during the FSP build. Use Intel's
227 Binary Configuration Tool (BCT) to do the rebase.
229 The default base address of 0xfffc0000 indicates that the binary must
230 be located at offset 0xc0000 from the beginning of a 1MB flash device.
232 config FSP_TEMP_RAM_ADDR
237 Stack top address which is used in fsp_init() after DRAM is ready and
240 config FSP_SYS_MALLOC_F_LEN
245 Additional size of malloc() pool before relocation.
252 Most FSPs use UPD data region for some FSP customization. But there
253 are still some FSPs that might not even have UPD. For such FSPs,
254 override this to n in their platform Kconfig files.
256 config FSP_BROKEN_HOB
260 Indicate some buggy FSPs that does not report memory used by FSP
261 itself as reserved in the resource descriptor HOB. Select this to
262 tell U-Boot to do some additional work to ensure U-Boot relocation
263 do not overwrite the important boot service data which is used by
264 FSP, otherwise the subsequent call to fsp_notify() will fail.
266 config ENABLE_MRC_CACHE
267 bool "Enable MRC cache"
268 depends on !EFI && !SYS_COREBOOT
270 Enable this feature to cause MRC data to be cached in NV storage
271 to be used for speeding up boot time on future reboots and/or
275 bool "Add a System Agent binary"
278 Select this option to add a System Agent binary to
279 the resulting U-Boot image. MRC stands for Memory Reference Code.
280 It is a binary blob which U-Boot uses to set up SDRAM.
282 Note: Without this binary U-Boot will not be able to set up its
283 SDRAM so will not boot.
290 Enable caching for the memory reference code binary. This uses an
291 MTRR (memory type range register) to turn on caching for the section
292 of SPI flash that contains the memory reference code. This makes
293 SDRAM init run faster.
295 config CACHE_MRC_SIZE_KB
300 Sets the size of the cached area for the memory reference code.
301 This ends at the end of SPI flash (address 0xffffffff) and is
302 measured in KB. Typically this is set to 512, providing for 0.5MB
305 config DCACHE_RAM_BASE
309 Sets the base of the data cache area in memory space. This is the
310 start address of the cache-as-RAM (CAR) area and the address varies
311 depending on the CPU. Once CAR is set up, read/write memory becomes
312 available at this address and can be used temporarily until SDRAM
315 config DCACHE_RAM_SIZE
320 Sets the total size of the data cache area in memory space. This
321 sets the size of the cache-as-RAM (CAR) area. Note that much of the
322 CAR space is required by the MRC. The CAR space available to U-Boot
323 is normally at the start and typically extends to 1/4 or 1/2 of the
326 config DCACHE_RAM_MRC_VAR_SIZE
330 This is the amount of CAR (Cache as RAM) reserved for use by the
331 memory reference code. This depends on the implementation of the
332 memory reference code and must be set correctly or the board will
336 bool "Add a Reference Code binary"
338 Select this option to add a Reference Code binary to the resulting
339 U-Boot image. This is an Intel binary blob that handles system
340 initialisation, in this case the PCH and System Agent.
342 Note: Without this binary (on platforms that need it such as
343 broadwell) U-Boot will be missing some critical setup steps.
344 Various peripherals may fail to work.
347 bool "Enable Symmetric Multiprocessing"
350 Enable use of more than one CPU in U-Boot and the Operating System
351 when loaded. Each CPU will be started up and information can be
352 obtained using the 'cpu' command. If this option is disabled, then
353 only one CPU will be enabled regardless of the number of CPUs
357 int "Maximum number of CPUs permitted"
361 When using multi-CPU chips it is possible for U-Boot to start up
362 more than one CPU. The stack memory used by all of these CPUs is
363 pre-allocated so at present U-Boot wants to know the maximum
364 number of CPUs that may be present. Set this to at least as high
365 as the number of CPUs in your system (it uses about 4KB of RAM for
373 Each additional CPU started by U-Boot requires its own stack. This
374 option sets the stack size used by each CPU and directly affects
375 the memory used by this initialisation process. Typically 4KB is
379 bool "Add a VGA BIOS image"
381 Select this option if you have a VGA BIOS image that you would
382 like to add to your ROM.
385 string "VGA BIOS image filename"
386 depends on HAVE_VGA_BIOS
389 The filename of the VGA BIOS image in the board directory.
392 hex "VGA BIOS image location"
393 depends on HAVE_VGA_BIOS
396 The location of VGA BIOS image in the SPI flash. For example, base
397 address of 0xfff90000 indicates that the image will be put at offset
398 0x90000 from the beginning of a 1MB flash device.
401 depends on !EFI && !SYS_COREBOOT
403 config GENERATE_PIRQ_TABLE
404 bool "Generate a PIRQ table"
407 Generate a PIRQ routing table for this board. The PIRQ routing table
408 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
409 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
410 It specifies the interrupt router information as well how all the PCI
411 devices' interrupt pins are wired to PIRQs.
413 config GENERATE_SFI_TABLE
414 bool "Generate a SFI (Simple Firmware Interface) table"
416 The Simple Firmware Interface (SFI) provides a lightweight method
417 for platform firmware to pass information to the operating system
418 via static tables in memory. Kernel SFI support is required to
419 boot on SFI-only platforms. If you have ACPI tables then these are
422 U-Boot writes this table in write_sfi_table() just before booting
425 For more information, see http://simplefirmware.org
427 config GENERATE_MP_TABLE
428 bool "Generate an MP (Multi-Processor) table"
431 Generate an MP (Multi-Processor) table for this board. The MP table
432 provides a way for the operating system to support for symmetric
433 multiprocessing as well as symmetric I/O interrupt handling with
434 the local APIC and I/O APIC.
436 config GENERATE_ACPI_TABLE
437 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
440 The Advanced Configuration and Power Interface (ACPI) specification
441 provides an open standard for device configuration and management
442 by the operating system. It defines platform-independent interfaces
443 for configuration and power management monitoring.
445 config QEMU_ACPI_TABLE
446 bool "Load ACPI table from QEMU fw_cfg interface"
447 depends on GENERATE_ACPI_TABLE && QEMU
450 By default, U-Boot generates its own ACPI tables. This option, if
451 enabled, disables U-Boot's version and loads ACPI tables generated
454 config GENERATE_SMBIOS_TABLE
455 bool "Generate an SMBIOS (System Management BIOS) table"
458 The System Management BIOS (SMBIOS) specification addresses how
459 motherboard and system vendors present management information about
460 their products in a standard format by extending the BIOS interface
461 on Intel architecture systems.
463 Check http://www.dmtf.org/standards/smbios for details.
467 config MAX_PIRQ_LINKS
471 This variable specifies the number of PIRQ interrupt links which are
472 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
473 Some newer chipsets offer more than four links, commonly up to PIRQH.
475 config IRQ_SLOT_COUNT
479 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
480 which in turns forms a table of exact 4KiB. The default value 128
481 should be enough for most boards. If this does not fit your board,
482 change it according to your needs.
484 config PCIE_ECAM_BASE
488 This is the memory-mapped address of PCI configuration space, which
489 is only available through the Enhanced Configuration Access
490 Mechanism (ECAM) with PCI Express. It can be set up almost
491 anywhere. Before it is set up, it is possible to access PCI
492 configuration space through I/O access, but memory access is more
493 convenient. Using this, PCI can be scanned and configured. This
494 should be set to a region that does not conflict with memory
495 assigned to PCI devices - i.e. the memory and prefetch regions, as
496 passed to pci_set_region().
498 config PCIE_ECAM_SIZE
502 This is the size of memory-mapped address of PCI configuration space,
503 which is only available through the Enhanced Configuration Access
504 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
505 so a default 0x10000000 size covers all of the 256 buses which is the
506 maximum number of PCI buses as defined by the PCI specification.
512 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
513 slave) interrupt controllers. Include this to have U-Boot set up
514 the interrupt correctly.
520 Intel 8254 timer contains three counters which have fixed uses.
521 Include this to have U-Boot set up the timer correctly.
530 bool "Support booting SeaBIOS"
532 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
533 It can run in an emulator or natively on X86 hardware with the use
534 of coreboot/U-Boot. By turning on this option, U-Boot prepares
535 all the configuration tables that are necessary to boot SeaBIOS.
537 Check http://www.seabios.org/SeaBIOS for details.
539 source "arch/x86/lib/efi/Kconfig"