1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
11 prompt "Target select"
13 config TARGET_COREBOOT
14 bool "Support coreboot"
16 This target is used for running U-Boot on top of Coreboot. In
17 this case Coreboot does the early inititalisation, and U-Boot
18 takes over once the RAM, video and CPU are fully running.
19 U-Boot is loaded as a fallback payload from Coreboot, in
20 Coreboot terminology. This method was used for the Chromebook
23 config TARGET_CHROMEBOOK_LINK
24 bool "Support Chromebook link"
26 This is the Chromebook Pixel released in 2013. It uses an Intel
27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28 SDRAM. It has a Panther Point platform controller hub, PCIe
29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30 reader, microphone and speakers, display port and 32GB SATA
31 solid state drive. There is a Chrome OS EC connected on LPC,
32 and it provides a 2560x1700 high resolution touch-enabled LCD
58 bool "Platform requires Intel Management Engine"
60 Newer higher-end devices have an Intel Management Engine (ME)
61 which is a very large binary blob (typically 1.5MB) which is
62 required for the platform to work. This enforces a particular
63 SPI flash format. You will need to supply the me.bin file in
66 source "arch/x86/cpu/ivybridge/Kconfig"
68 source "board/chromebook-x86/coreboot/Kconfig"
70 source "board/google/chromebook_link/Kconfig"