2 * Copyright (C) 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on code from coreboot
13 #include <asm/cpu_x86.h>
14 #include <asm/lapic.h>
17 #include <asm/turbo.h>
20 static int enable_smis(struct udevice *cpu, void *unused)
25 static struct mp_flight_record mp_steps[] = {
26 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
27 /* Wait for APs to finish initialization before proceeding. */
28 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
31 static int detect_num_cpus(void)
36 * Use the algorithm described in Intel 64 and IA-32 Architectures
37 * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
38 * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
39 * of CPUID Extended Topology Leaf.
42 struct cpuid_result leaf_b;
44 leaf_b = cpuid_ext(0xb, ecx);
47 * Bay Trail doesn't have hyperthreading so just determine the
48 * number of cores by from level type (ecx[15:8] == * 2)
50 if ((leaf_b.ecx & 0xff00) == 0x0200)
51 return leaf_b.ebx & 0xffff;
56 static int baytrail_init_cpus(void)
58 struct mp_params mp_params;
62 mp_params.num_cpus = detect_num_cpus();
63 mp_params.parallel_microcode_load = 0,
64 mp_params.flight_plan = &mp_steps[0];
65 mp_params.num_records = ARRAY_SIZE(mp_steps);
66 mp_params.microcode_pointer = 0;
68 if (mp_init(&mp_params)) {
69 printf("Warning: MP init failure\n");
77 int x86_init_cpus(void)
80 debug("Init additional CPUs\n");
87 static void set_max_freq(void)
92 /* Enable speed step */
93 msr = msr_read(MSR_IA32_MISC_ENABLES);
95 msr_write(MSR_IA32_MISC_ENABLES, msr);
98 * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
101 msr = msr_read(MSR_IACORE_RATIOS);
102 perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
105 * Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
108 msr = msr_read(MSR_IACORE_VIDS);
109 perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
112 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
115 static int cpu_x86_baytrail_probe(struct udevice *dev)
117 debug("Init BayTrail core\n");
120 * On BayTrail the turbo disable bit is actually scoped at the
121 * building-block level, not package. For non-BSP cores that are
122 * within a building block, enable turbo. The cores within the BSP's
123 * building block will just see it already enabled and move on.
128 /* Dynamic L2 shrink enable and threshold */
129 msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008),
132 msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
133 msr_setbits_64(MSR_POWER_MISC, 0x44);
135 /* Set this core to max frequency ratio */
141 static unsigned bus_freq(void)
143 msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
144 switch (clk_info.lo & 0x3) {
158 static unsigned long tsc_freq(void)
161 ulong bclk = bus_freq();
166 platform_info = msr_read(MSR_PLATFORM_INFO);
168 return bclk * ((platform_info.lo >> 8) & 0xff);
171 static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
173 info->cpu_freq = tsc_freq();
174 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
179 static const struct cpu_ops cpu_x86_baytrail_ops = {
180 .get_desc = cpu_x86_get_desc,
181 .get_info = baytrail_get_info,
184 static const struct udevice_id cpu_x86_baytrail_ids[] = {
185 { .compatible = "intel,baytrail-cpu" },
189 U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
190 .name = "cpu_x86_baytrail",
192 .of_match = cpu_x86_baytrail_ids,
193 .bind = cpu_x86_bind,
194 .probe = cpu_x86_baytrail_probe,
195 .ops = &cpu_x86_baytrail_ops,