2 * Copyright (C) 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on code from the coreboot file of the same name
14 #include <asm/atomic.h>
16 #include <asm/interrupt.h>
17 #include <asm/lapic.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
23 #include <linux/linkage.h>
25 /* Total CPUs include BSP */
28 /* This also needs to match the sipi.S assembly code for saved MSR encoding */
36 struct mp_flight_plan {
38 struct mp_flight_record *records;
41 static struct mp_flight_plan mp_info;
49 static inline void barrier_wait(atomic_t *b)
51 while (atomic_read(b) == 0)
56 static inline void release_barrier(atomic_t *b)
62 /* Returns 1 if timeout waiting for APs. 0 if target APs found */
63 static int wait_for_aps(atomic_t *val, int target, int total_delay,
69 while (atomic_read(val) != target) {
71 delayed += delay_step;
72 if (delayed >= total_delay) {
81 static void ap_do_flight_plan(struct udevice *cpu)
85 for (i = 0; i < mp_info.num_records; i++) {
86 struct mp_flight_record *rec = &mp_info.records[i];
88 atomic_inc(&rec->cpus_entered);
89 barrier_wait(&rec->barrier);
91 if (rec->ap_call != NULL)
92 rec->ap_call(cpu, rec->ap_arg);
96 static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
101 for (uclass_find_first_device(UCLASS_CPU, &dev);
103 uclass_find_next_device(&dev)) {
104 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
106 if (plat->cpu_id == apic_id) {
116 * By the time APs call ap_init() caching has been setup, and microcode has
119 static void ap_init(unsigned int cpu_index)
125 /* Ensure the local apic is enabled */
129 ret = find_cpu_by_apid_id(apic_id, &dev);
131 debug("Unknown CPU apic_id %x\n", apic_id);
135 debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
136 dev ? dev->name : "(apic_id not found)");
138 /* Walk the flight plan */
139 ap_do_flight_plan(dev);
147 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
148 MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
149 MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
150 MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
151 MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
154 static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
158 msr = msr_read(index);
159 entry->index = index;
163 /* Return the next entry */
168 static int save_bsp_msrs(char *start, int size)
172 struct saved_msr *msr_entry;
176 /* Determine number of MTRRs need to be saved */
177 msr = msr_read(MTRR_CAP_MSR);
178 num_var_mtrrs = msr.lo & 0xff;
180 /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
181 msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
183 if ((msr_count * sizeof(struct saved_msr)) > size) {
184 printf("Cannot mirror all %d msrs.\n", msr_count);
188 msr_entry = (void *)start;
189 for (i = 0; i < NUM_FIXED_MTRRS; i++)
190 msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
192 for (i = 0; i < num_var_mtrrs; i++) {
193 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
194 msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
197 msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
202 static int load_sipi_vector(atomic_t **ap_countp)
204 struct sipi_params_16bit *params16;
205 struct sipi_params *params;
206 static char msr_save[512];
213 /* Copy in the code */
214 code_len = ap_start16_code_end - ap_start16;
215 debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
217 memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
219 addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
220 params16 = (struct sipi_params_16bit *)addr;
221 params16->ap_start = (uint32_t)ap_start;
222 params16->gdt = (uint32_t)gd->arch.gdt;
223 params16->gdt_limit = X86_GDT_SIZE - 1;
224 debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
226 params = (struct sipi_params *)sipi_params;
227 debug("SIPI 32-bit params at %p\n", params);
228 params->idt_ptr = (uint32_t)x86_get_idt();
230 params->stack_size = CONFIG_AP_STACK_SIZE;
231 size = params->stack_size * CONFIG_MAX_CPUS;
232 stack = memalign(size, 4096);
235 params->stack_top = (u32)(stack + size);
237 params->microcode_ptr = 0;
238 params->msr_table_ptr = (u32)msr_save;
239 ret = save_bsp_msrs(msr_save, sizeof(msr_save));
242 params->msr_count = ret;
244 params->c_handler = (uint32_t)&ap_init;
246 *ap_countp = ¶ms->ap_count;
247 atomic_set(*ap_countp, 0);
248 debug("SIPI vector is ready\n");
253 static int check_cpu_devices(int expected_cpus)
257 for (i = 0; i < expected_cpus; i++) {
261 ret = uclass_find_device(UCLASS_CPU, i, &dev);
263 debug("Cannot find CPU %d in device tree\n", i);
271 /* Returns 1 for timeout. 0 on success */
272 static int apic_wait_timeout(int total_delay, int delay_step)
277 while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
280 if (total >= total_delay) {
289 static int start_aps(int ap_count, atomic_t *num_aps)
292 /* Max location is 4KiB below 1MiB */
293 const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
298 /* The vector is sent as a 4k aligned address in one byte */
299 sipi_vector = AP_DEFAULT_BASE >> 12;
301 if (sipi_vector > max_vector_loc) {
302 printf("SIPI vector too large! 0x%08x\n",
307 debug("Attempting to start %d APs\n", ap_count);
309 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
310 debug("Waiting for ICR not to be busy...");
311 if (apic_wait_timeout(1000, 50)) {
312 debug("timed out. Aborting.\n");
319 /* Send INIT IPI to all but self */
320 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
321 lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
323 debug("Waiting for 10ms after sending INIT.\n");
327 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
328 debug("Waiting for ICR not to be busy...");
329 if (apic_wait_timeout(1000, 50)) {
330 debug("timed out. Aborting.\n");
337 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
338 lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
339 LAPIC_DM_STARTUP | sipi_vector);
340 debug("Waiting for 1st SIPI to complete...");
341 if (apic_wait_timeout(10000, 50)) {
342 debug("timed out.\n");
348 /* Wait for CPUs to check in up to 200 us */
349 wait_for_aps(num_aps, ap_count, 200, 15);
352 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
353 debug("Waiting for ICR not to be busy...");
354 if (apic_wait_timeout(1000, 50)) {
355 debug("timed out. Aborting.\n");
362 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
363 lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
364 LAPIC_DM_STARTUP | sipi_vector);
365 debug("Waiting for 2nd SIPI to complete...");
366 if (apic_wait_timeout(10000, 50)) {
367 debug("timed out.\n");
373 /* Wait for CPUs to check in */
374 if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
375 debug("Not all APs checked in: %d/%d.\n",
376 atomic_read(num_aps), ap_count);
383 static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
387 const int timeout_us = 100000;
388 const int step_us = 100;
389 int num_aps = num_cpus - 1;
391 for (i = 0; i < mp_params->num_records; i++) {
392 struct mp_flight_record *rec = &mp_params->flight_plan[i];
394 /* Wait for APs if the record is not released */
395 if (atomic_read(&rec->barrier) == 0) {
396 /* Wait for the APs to check in */
397 if (wait_for_aps(&rec->cpus_entered, num_aps,
398 timeout_us, step_us)) {
399 debug("MP record %d timeout.\n", i);
404 if (rec->bsp_call != NULL)
405 rec->bsp_call(cpu, rec->bsp_arg);
407 release_barrier(&rec->barrier);
412 static int init_bsp(struct udevice **devp)
414 char processor_name[CPU_MAX_NAME_LEN];
418 cpu_get_name(processor_name);
419 debug("CPU: %s.\n", processor_name);
424 ret = find_cpu_by_apid_id(apic_id, devp);
426 printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
433 int mp_init(struct mp_params *p)
440 /* This will cause the CPUs devices to be bound */
442 ret = uclass_get(UCLASS_CPU, &uc);
446 ret = init_bsp(&cpu);
448 debug("Cannot init boot CPU: err=%d\n", ret);
452 if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
453 printf("Invalid MP parameters\n");
457 num_cpus = cpu_get_count(cpu);
459 debug("Cannot get number of CPUs: err=%d\n", num_cpus);
464 debug("Warning: Only 1 CPU is detected\n");
466 ret = check_cpu_devices(num_cpus);
468 debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
470 /* Copy needed parameters so that APs have a reference to the plan */
471 mp_info.num_records = p->num_records;
472 mp_info.records = p->flight_plan;
474 /* Load the SIPI vector */
475 ret = load_sipi_vector(&ap_count);
476 if (ap_count == NULL)
480 * Make sure SIPI data hits RAM so the APs that come up will see
481 * the startup code even if the caches are disabled
485 /* Start the APs providing number of APs and the cpus_entered field */
486 num_aps = num_cpus - 1;
487 ret = start_aps(num_aps, ap_count);
490 debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
495 /* Walk the flight plan for the BSP */
496 ret = bsp_do_flight_plan(cpu, p);
498 debug("CPU init failed: err=%d\n", ret);
505 int mp_init_cpu(struct udevice *cpu, void *unused)
507 return device_probe(cpu);