arch/x86/dts/crownbay.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 /include/ "skeleton.dtsi"
  10 /include/ "serial.dtsi"
  11
  12 / {
  13         model = "Intel Crown Bay";
  14         compatible = "intel,crownbay", "intel,queensbay";
  15
  16         aliases {
  17                 spi0 = "/spi";
  18         };
  19
  20         config {
  21                 silent_console = <0>;
  22         };
  23
  24         gpioa {
  25                 compatible = "intel,ich6-gpio";
  26                 u-boot,dm-pre-reloc;
  27                 reg = <0 0x20>;
  28                 bank-name = "A";
  29         };
  30
  31         gpiob {
  32                 compatible = "intel,ich6-gpio";
  33                 u-boot,dm-pre-reloc;
  34                 reg = <0x20 0x20>;
  35                 bank-name = "B";
  36         };
  37
  38         chosen {
  39                 /*
  40                  * By default the legacy superio serial port is used as the
  41                  * U-Boot serial console. If we want to use UART from Topcliff
  42                  * PCH as the console, change this property to &pciuart#.
  43                  *
  44                  * For example, stdout-path = &pciuart0 will use the first
  45                  * UART on Topcliff PCH.
  46                  */
  47                 stdout-path = "/serial";
  48         };
  49
  50         spi {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53                 compatible = "intel,ich-spi";
  54                 spi-flash@0 {
  55                         reg = <0>;
  56                         compatible = "sst,25vf016b", "spi-flash";
  57                         memory-map = <0xffe00000 0x00200000>;
  58                 };
  59         };
  60
  61         microcode {
  62                 update@0 {
  63 #include "microcode/m0220661105_cv.dtsi"
  64                 };
  65         };
  66
  67         pci {
  68                 #address-cells = <3>;
  69                 #size-cells = <2>;
  70                 compatible = "intel,pci";
  71                 device_type = "pci";
  72
  73                 pcie@17,0 {
  74                         #address-cells = <3>;
  75                         #size-cells = <2>;
  76                         compatible = "intel,pci";
  77                         device_type = "pci";
  78
  79                         topcliff@0,0 {
  80                                 #address-cells = <3>;
  81                                 #size-cells = <2>;
  82                                 compatible = "intel,pci";
  83                                 device_type = "pci";
  84
  85                                 pciuart0: uart@a,1 {
  86                                         compatible = "pci8086,8811.00",
  87                                                         "pci8086,8811",
  88                                                         "pciclass,070002",
  89                                                         "pciclass,0700",
  90                                                         "x86-uart";
  91                                         reg = <0x00025100 0x0 0x0 0x0 0x0
  92                                                0x01025110 0x0 0x0 0x0 0x0>;
  93                                         reg-shift = <0>;
  94                                         clock-frequency = <1843200>;
  95                                         current-speed = <115200>;
  96                                 };
  97
  98                                 pciuart1: uart@a,2 {
  99                                         compatible = "pci8086,8812.00",
 100                                                         "pci8086,8812",
 101                                                         "pciclass,070002",
 102                                                         "pciclass,0700",
 103                                                         "x86-uart";
 104                                         reg = <0x00025200 0x0 0x0 0x0 0x0
 105                                                0x01025210 0x0 0x0 0x0 0x0>;
 106                                         reg-shift = <0>;
 107                                         clock-frequency = <1843200>;
 108                                         current-speed = <115200>;
 109                                 };
 110
 111                                 pciuart2: uart@a,3 {
 112                                         compatible = "pci8086,8813.00",
 113                                                         "pci8086,8813",
 114                                                         "pciclass,070002",
 115                                                         "pciclass,0700",
 116                                                         "x86-uart";
 117                                         reg = <0x00025300 0x0 0x0 0x0 0x0
 118                                                0x01025310 0x0 0x0 0x0 0x0>;
 119                                         reg-shift = <0>;
 120                                         clock-frequency = <1843200>;
 121                                         current-speed = <115200>;
 122                                 };
 123
 124                                 pciuart3: uart@a,4 {
 125                                         compatible = "pci8086,8814.00",
 126                                                         "pci8086,8814",
 127                                                         "pciclass,070002",
 128                                                         "pciclass,0700",
 129                                                         "x86-uart";
 130                                         reg = <0x00025400 0x0 0x0 0x0 0x0
 131                                                0x01025410 0x0 0x0 0x0 0x0>;
 132                                         reg-shift = <0>;
 133                                         clock-frequency = <1843200>;
 134                                         current-speed = <115200>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140 };