arch/x86/dts/link.dts

   1 /dts-v1/;
   2
   3 /include/ "coreboot.dtsi"
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         model = "Google Link";
   9         compatible = "google,link", "intel,celeron-ivybridge";
  10
  11         config {
  12                silent_console = <0>;
  13         };
  14
  15         gpioa {
  16                 compatible = "intel,ich6-gpio";
  17                 u-boot,dm-pre-reloc;
  18                 reg = <0 0x10>;
  19                 bank-name = "A";
  20         };
  21
  22         gpiob {
  23                 compatible = "intel,ich6-gpio";
  24                 u-boot,dm-pre-reloc;
  25                 reg = <0x30 0x10>;
  26                 bank-name = "B";
  27         };
  28
  29         gpioc {
  30                 compatible = "intel,ich6-gpio";
  31                 u-boot,dm-pre-reloc;
  32                 reg = <0x40 0x10>;
  33                 bank-name = "C";
  34         };
  35
  36         serial {
  37                 reg = <0x3f8 8>;
  38                 clock-frequency = <115200>;
  39         };
  40
  41         chosen { };
  42         memory { device_type = "memory"; reg = <0 0>; };
  43
  44         spi {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 compatible = "intel,ich9";
  48                 spi-flash@0 {
  49                         reg = <0>;
  50                         compatible = "winbond,w25q64", "spi-flash";
  51                         memory-map = <0xff800000 0x00800000>;
  52                 };
  53         };
  54
  55         lpc {
  56                 compatible = "intel,lpc";
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 gen-dec = <0x800 0xfc 0x900 0xfc>;
  60                 cros-ec@200 {
  61                         compatible = "google,cros-ec";
  62                         reg = <0x204 1 0x200 1 0x880 0x80>;
  63
  64                         /* This describes the flash memory within the EC */
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         flash@8000000 {
  68                                 reg = <0x08000000 0x20000>;
  69                                 erase-value = <0xff>;
  70                         };
  71                 };
  72         };
  73
  74         microcode {
  75                 update@0 {
  76 #include "m12206a7_00000028.dtsi"
  77                 };
  78                 update@1 {
  79 #include "m12306a9_00000017.dtsi"
  80                 };
  81         };
  82
  83 };