2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/timer.h>
40 #include "perf_event.h"
42 struct x86_pmu x86_pmu __read_mostly;
44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
50 u64 __read_mostly hw_cache_event_ids
51 [PERF_COUNT_HW_CACHE_MAX]
52 [PERF_COUNT_HW_CACHE_OP_MAX]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX];
54 u64 __read_mostly hw_cache_extra_regs
55 [PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX];
60 * Propagate event elapsed time into the generic event.
61 * Can only be executed on the CPU where the event is active.
62 * Returns the delta events processed.
64 u64 x86_perf_event_update(struct perf_event *event)
66 struct hw_perf_event *hwc = &event->hw;
67 int shift = 64 - x86_pmu.cntval_bits;
68 u64 prev_raw_count, new_raw_count;
72 if (idx == INTEL_PMC_IDX_FIXED_BTS)
76 * Careful: an NMI might modify the previous event value.
78 * Our tactic to handle this is to first atomically read and
79 * exchange a new raw count - then add that new-prev delta
80 * count to the generic event atomically:
83 prev_raw_count = local64_read(&hwc->prev_count);
84 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
86 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
87 new_raw_count) != prev_raw_count)
91 * Now we have the new raw value and have updated the prev
92 * timestamp already. We can now calculate the elapsed delta
93 * (event-)time and add that to the generic event.
95 * Careful, not all hw sign-extends above the physical width
98 delta = (new_raw_count << shift) - (prev_raw_count << shift);
101 local64_add(delta, &event->count);
102 local64_sub(delta, &hwc->period_left);
104 return new_raw_count;
108 * Find and validate any extra registers to set up.
110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
112 struct hw_perf_event_extra *reg;
113 struct extra_reg *er;
115 reg = &event->hw.extra_reg;
117 if (!x86_pmu.extra_regs)
120 for (er = x86_pmu.extra_regs; er->msr; er++) {
121 if (er->event != (config & er->config_mask))
123 if (event->attr.config1 & ~er->valid_mask)
125 /* Check if the extra msrs can be safely accessed*/
126 if (!er->extra_msr_access)
130 reg->config = event->attr.config1;
137 static atomic_t active_events;
138 static atomic_t pmc_refcount;
139 static DEFINE_MUTEX(pmc_reserve_mutex);
141 #ifdef CONFIG_X86_LOCAL_APIC
143 static bool reserve_pmc_hardware(void)
147 for (i = 0; i < x86_pmu.num_counters; i++) {
148 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
152 for (i = 0; i < x86_pmu.num_counters; i++) {
153 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
160 for (i--; i >= 0; i--)
161 release_evntsel_nmi(x86_pmu_config_addr(i));
163 i = x86_pmu.num_counters;
166 for (i--; i >= 0; i--)
167 release_perfctr_nmi(x86_pmu_event_addr(i));
172 static void release_pmc_hardware(void)
176 for (i = 0; i < x86_pmu.num_counters; i++) {
177 release_perfctr_nmi(x86_pmu_event_addr(i));
178 release_evntsel_nmi(x86_pmu_config_addr(i));
184 static bool reserve_pmc_hardware(void) { return true; }
185 static void release_pmc_hardware(void) {}
189 static bool check_hw_exists(void)
191 u64 val, val_fail, val_new= ~0;
192 int i, reg, reg_fail, ret = 0;
197 * Check to see if the BIOS enabled any of the counters, if so
200 for (i = 0; i < x86_pmu.num_counters; i++) {
201 reg = x86_pmu_config_addr(i);
202 ret = rdmsrl_safe(reg, &val);
205 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
214 if (x86_pmu.num_counters_fixed) {
215 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
216 ret = rdmsrl_safe(reg, &val);
219 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
220 if (val & (0x03 << i*4)) {
229 * If all the counters are enabled, the below test will always
230 * fail. The tools will also become useless in this scenario.
231 * Just fail and disable the hardware counters.
234 if (reg_safe == -1) {
240 * Read the current value, change it and read it back to see if it
241 * matches, this is needed to detect certain hardware emulators
242 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
244 reg = x86_pmu_event_addr(reg_safe);
245 if (rdmsrl_safe(reg, &val))
248 ret = wrmsrl_safe(reg, val);
249 ret |= rdmsrl_safe(reg, &val_new);
250 if (ret || val != val_new)
254 * We still allow the PMU driver to operate:
257 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
258 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
265 pr_cont("Broken PMU hardware detected, using software events only.\n");
266 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
267 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
273 static void hw_perf_event_destroy(struct perf_event *event)
275 x86_release_hardware();
276 atomic_dec(&active_events);
279 void hw_perf_lbr_event_destroy(struct perf_event *event)
281 hw_perf_event_destroy(event);
283 /* undo the lbr/bts event accounting */
284 x86_del_exclusive(x86_lbr_exclusive_lbr);
287 static inline int x86_pmu_initialized(void)
289 return x86_pmu.handle_irq != NULL;
293 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
295 struct perf_event_attr *attr = &event->attr;
296 unsigned int cache_type, cache_op, cache_result;
299 config = attr->config;
301 cache_type = (config >> 0) & 0xff;
302 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
305 cache_op = (config >> 8) & 0xff;
306 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
309 cache_result = (config >> 16) & 0xff;
310 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
313 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
322 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
323 return x86_pmu_extra_regs(val, event);
326 int x86_reserve_hardware(void)
330 if (!atomic_inc_not_zero(&pmc_refcount)) {
331 mutex_lock(&pmc_reserve_mutex);
332 if (atomic_read(&pmc_refcount) == 0) {
333 if (!reserve_pmc_hardware())
336 reserve_ds_buffers();
339 atomic_inc(&pmc_refcount);
340 mutex_unlock(&pmc_reserve_mutex);
346 void x86_release_hardware(void)
348 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
349 release_pmc_hardware();
350 release_ds_buffers();
351 mutex_unlock(&pmc_reserve_mutex);
356 * Check if we can create event of a certain type (that no conflicting events
359 int x86_add_exclusive(unsigned int what)
363 if (x86_pmu.lbr_pt_coexist)
366 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
367 mutex_lock(&pmc_reserve_mutex);
368 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
369 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
372 atomic_inc(&x86_pmu.lbr_exclusive[what]);
373 mutex_unlock(&pmc_reserve_mutex);
376 atomic_inc(&active_events);
380 mutex_unlock(&pmc_reserve_mutex);
384 void x86_del_exclusive(unsigned int what)
386 if (x86_pmu.lbr_pt_coexist)
389 atomic_dec(&x86_pmu.lbr_exclusive[what]);
390 atomic_dec(&active_events);
393 int x86_setup_perfctr(struct perf_event *event)
395 struct perf_event_attr *attr = &event->attr;
396 struct hw_perf_event *hwc = &event->hw;
399 if (!is_sampling_event(event)) {
400 hwc->sample_period = x86_pmu.max_period;
401 hwc->last_period = hwc->sample_period;
402 local64_set(&hwc->period_left, hwc->sample_period);
405 if (attr->type == PERF_TYPE_RAW)
406 return x86_pmu_extra_regs(event->attr.config, event);
408 if (attr->type == PERF_TYPE_HW_CACHE)
409 return set_ext_hw_attr(hwc, event);
411 if (attr->config >= x86_pmu.max_events)
417 config = x86_pmu.event_map(attr->config);
428 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
429 !attr->freq && hwc->sample_period == 1) {
430 /* BTS is not supported by this architecture. */
431 if (!x86_pmu.bts_active)
434 /* BTS is currently only allowed for user-mode. */
435 if (!attr->exclude_kernel)
438 /* disallow bts if conflicting events are present */
439 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
442 event->destroy = hw_perf_lbr_event_destroy;
445 hwc->config |= config;
451 * check that branch_sample_type is compatible with
452 * settings needed for precise_ip > 1 which implies
453 * using the LBR to capture ALL taken branches at the
454 * priv levels of the measurement
456 static inline int precise_br_compat(struct perf_event *event)
458 u64 m = event->attr.branch_sample_type;
461 /* must capture all branches */
462 if (!(m & PERF_SAMPLE_BRANCH_ANY))
465 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
467 if (!event->attr.exclude_user)
468 b |= PERF_SAMPLE_BRANCH_USER;
470 if (!event->attr.exclude_kernel)
471 b |= PERF_SAMPLE_BRANCH_KERNEL;
474 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
480 int x86_pmu_hw_config(struct perf_event *event)
482 if (event->attr.precise_ip) {
485 /* Support for constant skid */
486 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
489 /* Support for IP fixup */
490 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
493 if (x86_pmu.pebs_prec_dist)
497 if (event->attr.precise_ip > precise)
501 * check that PEBS LBR correction does not conflict with
502 * whatever the user is asking with attr->branch_sample_type
504 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
505 u64 *br_type = &event->attr.branch_sample_type;
507 if (has_branch_stack(event)) {
508 if (!precise_br_compat(event))
511 /* branch_sample_type is compatible */
515 * user did not specify branch_sample_type
517 * For PEBS fixups, we capture all
518 * the branches at the priv level of the
521 *br_type = PERF_SAMPLE_BRANCH_ANY;
523 if (!event->attr.exclude_user)
524 *br_type |= PERF_SAMPLE_BRANCH_USER;
526 if (!event->attr.exclude_kernel)
527 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
531 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
532 event->attach_state |= PERF_ATTACH_TASK_DATA;
536 * (keep 'enabled' bit clear for now)
538 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
541 * Count user and OS events unless requested not to
543 if (!event->attr.exclude_user)
544 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
545 if (!event->attr.exclude_kernel)
546 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
548 if (event->attr.type == PERF_TYPE_RAW)
549 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
551 if (event->attr.sample_period && x86_pmu.limit_period) {
552 if (x86_pmu.limit_period(event, event->attr.sample_period) >
553 event->attr.sample_period)
557 return x86_setup_perfctr(event);
561 * Setup the hardware configuration for a given attr_type
563 static int __x86_pmu_event_init(struct perf_event *event)
567 if (!x86_pmu_initialized())
570 err = x86_reserve_hardware();
574 atomic_inc(&active_events);
575 event->destroy = hw_perf_event_destroy;
578 event->hw.last_cpu = -1;
579 event->hw.last_tag = ~0ULL;
582 event->hw.extra_reg.idx = EXTRA_REG_NONE;
583 event->hw.branch_reg.idx = EXTRA_REG_NONE;
585 return x86_pmu.hw_config(event);
588 void x86_pmu_disable_all(void)
590 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
593 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
596 if (!test_bit(idx, cpuc->active_mask))
598 rdmsrl(x86_pmu_config_addr(idx), val);
599 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
601 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
602 wrmsrl(x86_pmu_config_addr(idx), val);
607 * There may be PMI landing after enabled=0. The PMI hitting could be before or
610 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
611 * It will not be re-enabled in the NMI handler again, because enabled=0. After
612 * handling the NMI, disable_all will be called, which will not change the
613 * state either. If PMI hits after disable_all, the PMU is already disabled
614 * before entering NMI handler. The NMI handler will not change the state
617 * So either situation is harmless.
619 static void x86_pmu_disable(struct pmu *pmu)
621 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
623 if (!x86_pmu_initialized())
633 x86_pmu.disable_all();
636 void x86_pmu_enable_all(int added)
638 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
641 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
642 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
644 if (!test_bit(idx, cpuc->active_mask))
647 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
651 static struct pmu pmu;
653 static inline int is_x86_event(struct perf_event *event)
655 return event->pmu == &pmu;
659 * Event scheduler state:
661 * Assign events iterating over all events and counters, beginning
662 * with events with least weights first. Keep the current iterator
663 * state in struct sched_state.
667 int event; /* event index */
668 int counter; /* counter index */
669 int unassigned; /* number of events to be assigned left */
670 int nr_gp; /* number of GP counters used */
671 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
674 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
675 #define SCHED_STATES_MAX 2
682 struct event_constraint **constraints;
683 struct sched_state state;
684 struct sched_state saved[SCHED_STATES_MAX];
688 * Initialize interator that runs through all events and counters.
690 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
691 int num, int wmin, int wmax, int gpmax)
695 memset(sched, 0, sizeof(*sched));
696 sched->max_events = num;
697 sched->max_weight = wmax;
698 sched->max_gp = gpmax;
699 sched->constraints = constraints;
701 for (idx = 0; idx < num; idx++) {
702 if (constraints[idx]->weight == wmin)
706 sched->state.event = idx; /* start with min weight */
707 sched->state.weight = wmin;
708 sched->state.unassigned = num;
711 static void perf_sched_save_state(struct perf_sched *sched)
713 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
716 sched->saved[sched->saved_states] = sched->state;
717 sched->saved_states++;
720 static bool perf_sched_restore_state(struct perf_sched *sched)
722 if (!sched->saved_states)
725 sched->saved_states--;
726 sched->state = sched->saved[sched->saved_states];
728 /* continue with next counter: */
729 clear_bit(sched->state.counter++, sched->state.used);
735 * Select a counter for the current event to schedule. Return true on
738 static bool __perf_sched_find_counter(struct perf_sched *sched)
740 struct event_constraint *c;
743 if (!sched->state.unassigned)
746 if (sched->state.event >= sched->max_events)
749 c = sched->constraints[sched->state.event];
750 /* Prefer fixed purpose counters */
751 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
752 idx = INTEL_PMC_IDX_FIXED;
753 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
754 if (!__test_and_set_bit(idx, sched->state.used))
759 /* Grab the first unused counter starting with idx */
760 idx = sched->state.counter;
761 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
762 if (!__test_and_set_bit(idx, sched->state.used)) {
763 if (sched->state.nr_gp++ >= sched->max_gp)
773 sched->state.counter = idx;
776 perf_sched_save_state(sched);
781 static bool perf_sched_find_counter(struct perf_sched *sched)
783 while (!__perf_sched_find_counter(sched)) {
784 if (!perf_sched_restore_state(sched))
792 * Go through all unassigned events and find the next one to schedule.
793 * Take events with the least weight first. Return true on success.
795 static bool perf_sched_next_event(struct perf_sched *sched)
797 struct event_constraint *c;
799 if (!sched->state.unassigned || !--sched->state.unassigned)
804 sched->state.event++;
805 if (sched->state.event >= sched->max_events) {
807 sched->state.event = 0;
808 sched->state.weight++;
809 if (sched->state.weight > sched->max_weight)
812 c = sched->constraints[sched->state.event];
813 } while (c->weight != sched->state.weight);
815 sched->state.counter = 0; /* start with first counter */
821 * Assign a counter for each event.
823 int perf_assign_events(struct event_constraint **constraints, int n,
824 int wmin, int wmax, int gpmax, int *assign)
826 struct perf_sched sched;
828 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
831 if (!perf_sched_find_counter(&sched))
834 assign[sched.state.event] = sched.state.counter;
835 } while (perf_sched_next_event(&sched));
837 return sched.state.unassigned;
839 EXPORT_SYMBOL_GPL(perf_assign_events);
841 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
843 struct event_constraint *c;
844 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
845 struct perf_event *e;
846 int i, wmin, wmax, unsched = 0;
847 struct hw_perf_event *hwc;
849 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
851 if (x86_pmu.start_scheduling)
852 x86_pmu.start_scheduling(cpuc);
854 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
855 cpuc->event_constraint[i] = NULL;
856 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
857 cpuc->event_constraint[i] = c;
859 wmin = min(wmin, c->weight);
860 wmax = max(wmax, c->weight);
864 * fastpath, try to reuse previous register
866 for (i = 0; i < n; i++) {
867 hwc = &cpuc->event_list[i]->hw;
868 c = cpuc->event_constraint[i];
874 /* constraint still honored */
875 if (!test_bit(hwc->idx, c->idxmsk))
878 /* not already used */
879 if (test_bit(hwc->idx, used_mask))
882 __set_bit(hwc->idx, used_mask);
884 assign[i] = hwc->idx;
889 int gpmax = x86_pmu.num_counters;
892 * Do not allow scheduling of more than half the available
895 * This helps avoid counter starvation of sibling thread by
896 * ensuring at most half the counters cannot be in exclusive
897 * mode. There is no designated counters for the limits. Any
898 * N/2 counters can be used. This helps with events with
899 * specific counter constraints.
901 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
902 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
905 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
906 wmax, gpmax, assign);
910 * In case of success (unsched = 0), mark events as committed,
911 * so we do not put_constraint() in case new events are added
912 * and fail to be scheduled
914 * We invoke the lower level commit callback to lock the resource
916 * We do not need to do all of this in case we are called to
917 * validate an event group (assign == NULL)
919 if (!unsched && assign) {
920 for (i = 0; i < n; i++) {
921 e = cpuc->event_list[i];
922 e->hw.flags |= PERF_X86_EVENT_COMMITTED;
923 if (x86_pmu.commit_scheduling)
924 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
927 for (i = 0; i < n; i++) {
928 e = cpuc->event_list[i];
930 * do not put_constraint() on comitted events,
931 * because they are good to go
933 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
937 * release events that failed scheduling
939 if (x86_pmu.put_event_constraints)
940 x86_pmu.put_event_constraints(cpuc, e);
944 if (x86_pmu.stop_scheduling)
945 x86_pmu.stop_scheduling(cpuc);
947 return unsched ? -EINVAL : 0;
951 * dogrp: true if must collect siblings events (group)
952 * returns total number of events and error code
954 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
956 struct perf_event *event;
959 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
961 /* current number of events already accepted */
964 if (is_x86_event(leader)) {
967 cpuc->event_list[n] = leader;
973 list_for_each_entry(event, &leader->sibling_list, group_entry) {
974 if (!is_x86_event(event) ||
975 event->state <= PERF_EVENT_STATE_OFF)
981 cpuc->event_list[n] = event;
987 static inline void x86_assign_hw_event(struct perf_event *event,
988 struct cpu_hw_events *cpuc, int i)
990 struct hw_perf_event *hwc = &event->hw;
992 hwc->idx = cpuc->assign[i];
993 hwc->last_cpu = smp_processor_id();
994 hwc->last_tag = ++cpuc->tags[i];
996 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
997 hwc->config_base = 0;
999 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1000 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1001 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1002 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1004 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1005 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1006 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1010 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1011 struct cpu_hw_events *cpuc,
1014 return hwc->idx == cpuc->assign[i] &&
1015 hwc->last_cpu == smp_processor_id() &&
1016 hwc->last_tag == cpuc->tags[i];
1019 static void x86_pmu_start(struct perf_event *event, int flags);
1021 static void x86_pmu_enable(struct pmu *pmu)
1023 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1024 struct perf_event *event;
1025 struct hw_perf_event *hwc;
1026 int i, added = cpuc->n_added;
1028 if (!x86_pmu_initialized())
1034 if (cpuc->n_added) {
1035 int n_running = cpuc->n_events - cpuc->n_added;
1037 * apply assignment obtained either from
1038 * hw_perf_group_sched_in() or x86_pmu_enable()
1040 * step1: save events moving to new counters
1042 for (i = 0; i < n_running; i++) {
1043 event = cpuc->event_list[i];
1047 * we can avoid reprogramming counter if:
1048 * - assigned same counter as last time
1049 * - running on same CPU as last time
1050 * - no other event has used the counter since
1052 if (hwc->idx == -1 ||
1053 match_prev_assignment(hwc, cpuc, i))
1057 * Ensure we don't accidentally enable a stopped
1058 * counter simply because we rescheduled.
1060 if (hwc->state & PERF_HES_STOPPED)
1061 hwc->state |= PERF_HES_ARCH;
1063 x86_pmu_stop(event, PERF_EF_UPDATE);
1067 * step2: reprogram moved events into new counters
1069 for (i = 0; i < cpuc->n_events; i++) {
1070 event = cpuc->event_list[i];
1073 if (!match_prev_assignment(hwc, cpuc, i))
1074 x86_assign_hw_event(event, cpuc, i);
1075 else if (i < n_running)
1078 if (hwc->state & PERF_HES_ARCH)
1081 x86_pmu_start(event, PERF_EF_RELOAD);
1084 perf_events_lapic_init();
1090 x86_pmu.enable_all(added);
1093 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1096 * Set the next IRQ period, based on the hwc->period_left value.
1097 * To be called with the event disabled in hw:
1099 int x86_perf_event_set_period(struct perf_event *event)
1101 struct hw_perf_event *hwc = &event->hw;
1102 s64 left = local64_read(&hwc->period_left);
1103 s64 period = hwc->sample_period;
1104 int ret = 0, idx = hwc->idx;
1106 if (idx == INTEL_PMC_IDX_FIXED_BTS)
1110 * If we are way outside a reasonable range then just skip forward:
1112 if (unlikely(left <= -period)) {
1114 local64_set(&hwc->period_left, left);
1115 hwc->last_period = period;
1119 if (unlikely(left <= 0)) {
1121 local64_set(&hwc->period_left, left);
1122 hwc->last_period = period;
1126 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1128 if (unlikely(left < 2))
1131 if (left > x86_pmu.max_period)
1132 left = x86_pmu.max_period;
1134 if (x86_pmu.limit_period)
1135 left = x86_pmu.limit_period(event, left);
1137 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1139 if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
1140 local64_read(&hwc->prev_count) != (u64)-left) {
1142 * The hw event starts counting from this event offset,
1143 * mark it to be able to extra future deltas:
1145 local64_set(&hwc->prev_count, (u64)-left);
1147 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1151 * Due to erratum on certan cpu we need
1152 * a second write to be sure the register
1153 * is updated properly
1155 if (x86_pmu.perfctr_second_write) {
1156 wrmsrl(hwc->event_base,
1157 (u64)(-left) & x86_pmu.cntval_mask);
1160 perf_event_update_userpage(event);
1165 void x86_pmu_enable_event(struct perf_event *event)
1167 if (__this_cpu_read(cpu_hw_events.enabled))
1168 __x86_pmu_enable_event(&event->hw,
1169 ARCH_PERFMON_EVENTSEL_ENABLE);
1173 * Add a single event to the PMU.
1175 * The event is added to the group of enabled events
1176 * but only if it can be scehduled with existing events.
1178 static int x86_pmu_add(struct perf_event *event, int flags)
1180 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1181 struct hw_perf_event *hwc;
1182 int assign[X86_PMC_IDX_MAX];
1187 n0 = cpuc->n_events;
1188 ret = n = collect_events(cpuc, event, false);
1192 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1193 if (!(flags & PERF_EF_START))
1194 hwc->state |= PERF_HES_ARCH;
1197 * If group events scheduling transaction was started,
1198 * skip the schedulability test here, it will be performed
1199 * at commit time (->commit_txn) as a whole.
1201 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1204 ret = x86_pmu.schedule_events(cpuc, n, assign);
1208 * copy new assignment, now we know it is possible
1209 * will be used by hw_perf_enable()
1211 memcpy(cpuc->assign, assign, n*sizeof(int));
1215 * Commit the collect_events() state. See x86_pmu_del() and
1219 cpuc->n_added += n - n0;
1220 cpuc->n_txn += n - n0;
1227 static void x86_pmu_start(struct perf_event *event, int flags)
1229 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1230 int idx = event->hw.idx;
1232 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1235 if (WARN_ON_ONCE(idx == -1))
1238 if (flags & PERF_EF_RELOAD) {
1239 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1240 x86_perf_event_set_period(event);
1243 event->hw.state = 0;
1245 cpuc->events[idx] = event;
1246 __set_bit(idx, cpuc->active_mask);
1247 __set_bit(idx, cpuc->running);
1248 x86_pmu.enable(event);
1249 perf_event_update_userpage(event);
1252 void perf_event_print_debug(void)
1254 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1256 struct cpu_hw_events *cpuc;
1257 unsigned long flags;
1260 if (!x86_pmu.num_counters)
1263 local_irq_save(flags);
1265 cpu = smp_processor_id();
1266 cpuc = &per_cpu(cpu_hw_events, cpu);
1268 if (x86_pmu.version >= 2) {
1269 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1270 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1271 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1272 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1275 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1276 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1277 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1278 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1279 if (x86_pmu.pebs_constraints) {
1280 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1281 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1283 if (x86_pmu.lbr_nr) {
1284 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1285 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1288 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1290 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1291 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1292 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1294 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1296 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1297 cpu, idx, pmc_ctrl);
1298 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1299 cpu, idx, pmc_count);
1300 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1301 cpu, idx, prev_left);
1303 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1304 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1306 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1307 cpu, idx, pmc_count);
1309 local_irq_restore(flags);
1312 void x86_pmu_stop(struct perf_event *event, int flags)
1314 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1315 struct hw_perf_event *hwc = &event->hw;
1317 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1318 x86_pmu.disable(event);
1319 cpuc->events[hwc->idx] = NULL;
1320 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1321 hwc->state |= PERF_HES_STOPPED;
1324 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1326 * Drain the remaining delta count out of a event
1327 * that we are disabling:
1329 x86_perf_event_update(event);
1330 hwc->state |= PERF_HES_UPTODATE;
1334 static void x86_pmu_del(struct perf_event *event, int flags)
1336 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1340 * event is descheduled
1342 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1345 * If we're called during a txn, we don't need to do anything.
1346 * The events never got scheduled and ->cancel_txn will truncate
1349 * XXX assumes any ->del() called during a TXN will only be on
1350 * an event added during that same TXN.
1352 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1356 * Not a TXN, therefore cleanup properly.
1358 x86_pmu_stop(event, PERF_EF_UPDATE);
1360 for (i = 0; i < cpuc->n_events; i++) {
1361 if (event == cpuc->event_list[i])
1365 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1368 /* If we have a newly added event; make sure to decrease n_added. */
1369 if (i >= cpuc->n_events - cpuc->n_added)
1372 if (x86_pmu.put_event_constraints)
1373 x86_pmu.put_event_constraints(cpuc, event);
1375 /* Delete the array entry. */
1376 while (++i < cpuc->n_events) {
1377 cpuc->event_list[i-1] = cpuc->event_list[i];
1378 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1382 perf_event_update_userpage(event);
1385 int x86_pmu_handle_irq(struct pt_regs *regs)
1387 struct perf_sample_data data;
1388 struct cpu_hw_events *cpuc;
1389 struct perf_event *event;
1390 int idx, handled = 0;
1393 cpuc = this_cpu_ptr(&cpu_hw_events);
1396 * Some chipsets need to unmask the LVTPC in a particular spot
1397 * inside the nmi handler. As a result, the unmasking was pushed
1398 * into all the nmi handlers.
1400 * This generic handler doesn't seem to have any issues where the
1401 * unmasking occurs so it was left at the top.
1403 apic_write(APIC_LVTPC, APIC_DM_NMI);
1405 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1406 if (!test_bit(idx, cpuc->active_mask)) {
1408 * Though we deactivated the counter some cpus
1409 * might still deliver spurious interrupts still
1410 * in flight. Catch them:
1412 if (__test_and_clear_bit(idx, cpuc->running))
1417 event = cpuc->events[idx];
1419 val = x86_perf_event_update(event);
1420 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1427 perf_sample_data_init(&data, 0, event->hw.last_period);
1429 if (!x86_perf_event_set_period(event))
1432 if (perf_event_overflow(event, &data, regs))
1433 x86_pmu_stop(event, 0);
1437 inc_irq_stat(apic_perf_irqs);
1442 void perf_events_lapic_init(void)
1444 if (!x86_pmu.apic || !x86_pmu_initialized())
1448 * Always use NMI for PMU
1450 apic_write(APIC_LVTPC, APIC_DM_NMI);
1454 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1461 * All PMUs/events that share this PMI handler should make sure to
1462 * increment active_events for their events.
1464 if (!atomic_read(&active_events))
1467 start_clock = sched_clock();
1468 ret = x86_pmu.handle_irq(regs);
1469 finish_clock = sched_clock();
1471 perf_sample_event_took(finish_clock - start_clock);
1475 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1477 struct event_constraint emptyconstraint;
1478 struct event_constraint unconstrained;
1480 static int x86_pmu_prepare_cpu(unsigned int cpu)
1482 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1485 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1486 cpuc->kfree_on_online[i] = NULL;
1487 if (x86_pmu.cpu_prepare)
1488 return x86_pmu.cpu_prepare(cpu);
1492 static int x86_pmu_dead_cpu(unsigned int cpu)
1494 if (x86_pmu.cpu_dead)
1495 x86_pmu.cpu_dead(cpu);
1499 static int x86_pmu_online_cpu(unsigned int cpu)
1501 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1504 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1505 kfree(cpuc->kfree_on_online[i]);
1506 cpuc->kfree_on_online[i] = NULL;
1511 static int x86_pmu_starting_cpu(unsigned int cpu)
1513 if (x86_pmu.cpu_starting)
1514 x86_pmu.cpu_starting(cpu);
1518 static int x86_pmu_dying_cpu(unsigned int cpu)
1520 if (x86_pmu.cpu_dying)
1521 x86_pmu.cpu_dying(cpu);
1525 static void __init pmu_check_apic(void)
1527 if (boot_cpu_has(X86_FEATURE_APIC))
1531 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1532 pr_info("no hardware sampling interrupt available.\n");
1535 * If we have a PMU initialized but no APIC
1536 * interrupts, we cannot sample hardware
1537 * events (user-space has to fall back and
1538 * sample via a hrtimer based software event):
1540 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1544 static struct attribute_group x86_pmu_format_group = {
1550 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1551 * out of events_attr attributes.
1553 static void __init filter_events(struct attribute **attrs)
1555 struct device_attribute *d;
1556 struct perf_pmu_events_attr *pmu_attr;
1560 for (i = 0; attrs[i]; i++) {
1561 d = (struct device_attribute *)attrs[i];
1562 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1564 if (pmu_attr->event_str)
1566 if (x86_pmu.event_map(i + offset))
1569 for (j = i; attrs[j]; j++)
1570 attrs[j] = attrs[j + 1];
1572 /* Check the shifted attr. */
1576 * event_map() is index based, the attrs array is organized
1577 * by increasing event index. If we shift the events, then
1578 * we need to compensate for the event_map(), otherwise
1579 * we are looking up the wrong event in the map
1585 /* Merge two pointer arrays */
1586 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1588 struct attribute **new;
1591 for (j = 0; a[j]; j++)
1593 for (i = 0; b[i]; i++)
1597 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1602 for (i = 0; a[i]; i++)
1604 for (i = 0; b[i]; i++)
1611 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1613 struct perf_pmu_events_attr *pmu_attr = \
1614 container_of(attr, struct perf_pmu_events_attr, attr);
1615 u64 config = x86_pmu.event_map(pmu_attr->id);
1617 /* string trumps id */
1618 if (pmu_attr->event_str)
1619 return sprintf(page, "%s", pmu_attr->event_str);
1621 return x86_pmu.events_sysfs_show(page, config);
1623 EXPORT_SYMBOL_GPL(events_sysfs_show);
1625 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1628 struct perf_pmu_events_ht_attr *pmu_attr =
1629 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1632 * Report conditional events depending on Hyper-Threading.
1634 * This is overly conservative as usually the HT special
1635 * handling is not needed if the other CPU thread is idle.
1637 * Note this does not (and cannot) handle the case when thread
1638 * siblings are invisible, for example with virtualization
1639 * if they are owned by some other guest. The user tool
1640 * has to re-read when a thread sibling gets onlined later.
1642 return sprintf(page, "%s",
1643 topology_max_smt_threads() > 1 ?
1644 pmu_attr->event_str_ht :
1645 pmu_attr->event_str_noht);
1648 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1649 EVENT_ATTR(instructions, INSTRUCTIONS );
1650 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1651 EVENT_ATTR(cache-misses, CACHE_MISSES );
1652 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1653 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1654 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1655 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1656 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1657 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1659 static struct attribute *empty_attrs;
1661 static struct attribute *events_attr[] = {
1662 EVENT_PTR(CPU_CYCLES),
1663 EVENT_PTR(INSTRUCTIONS),
1664 EVENT_PTR(CACHE_REFERENCES),
1665 EVENT_PTR(CACHE_MISSES),
1666 EVENT_PTR(BRANCH_INSTRUCTIONS),
1667 EVENT_PTR(BRANCH_MISSES),
1668 EVENT_PTR(BUS_CYCLES),
1669 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1670 EVENT_PTR(STALLED_CYCLES_BACKEND),
1671 EVENT_PTR(REF_CPU_CYCLES),
1675 static struct attribute_group x86_pmu_events_group = {
1677 .attrs = events_attr,
1680 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1682 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1683 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1684 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1685 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1686 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1687 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1691 * We have whole page size to spend and just little data
1692 * to write, so we can safely use sprintf.
1694 ret = sprintf(page, "event=0x%02llx", event);
1697 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1700 ret += sprintf(page + ret, ",edge");
1703 ret += sprintf(page + ret, ",pc");
1706 ret += sprintf(page + ret, ",any");
1709 ret += sprintf(page + ret, ",inv");
1712 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1714 ret += sprintf(page + ret, "\n");
1719 static int __init init_hw_perf_events(void)
1721 struct x86_pmu_quirk *quirk;
1724 pr_info("Performance Events: ");
1726 switch (boot_cpu_data.x86_vendor) {
1727 case X86_VENDOR_INTEL:
1728 err = intel_pmu_init();
1730 case X86_VENDOR_AMD:
1731 err = amd_pmu_init();
1737 pr_cont("no PMU driver, software events only.\n");
1743 /* sanity check that the hardware exists or is emulated */
1744 if (!check_hw_exists())
1747 pr_cont("%s PMU driver.\n", x86_pmu.name);
1749 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1751 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1754 if (!x86_pmu.intel_ctrl)
1755 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1757 perf_events_lapic_init();
1758 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1760 unconstrained = (struct event_constraint)
1761 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1762 0, x86_pmu.num_counters, 0, 0);
1764 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1766 if (x86_pmu.event_attrs)
1767 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1769 if (!x86_pmu.events_sysfs_show)
1770 x86_pmu_events_group.attrs = &empty_attrs;
1772 filter_events(x86_pmu_events_group.attrs);
1774 if (x86_pmu.cpu_events) {
1775 struct attribute **tmp;
1777 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1779 x86_pmu_events_group.attrs = tmp;
1782 pr_info("... version: %d\n", x86_pmu.version);
1783 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1784 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1785 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1786 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1787 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1788 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1791 * Install callbacks. Core will call them for each online
1794 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "PERF_X86_PREPARE",
1795 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1799 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1800 "AP_PERF_X86_STARTING", x86_pmu_starting_cpu,
1805 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "AP_PERF_X86_ONLINE",
1806 x86_pmu_online_cpu, NULL);
1810 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1817 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1819 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1821 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1824 early_initcall(init_hw_perf_events);
1826 static inline void x86_pmu_read(struct perf_event *event)
1828 x86_perf_event_update(event);
1832 * Start group events scheduling transaction
1833 * Set the flag to make pmu::enable() not perform the
1834 * schedulability test, it will be performed at commit time
1836 * We only support PERF_PMU_TXN_ADD transactions. Save the
1837 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1840 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1842 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1844 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
1846 cpuc->txn_flags = txn_flags;
1847 if (txn_flags & ~PERF_PMU_TXN_ADD)
1850 perf_pmu_disable(pmu);
1851 __this_cpu_write(cpu_hw_events.n_txn, 0);
1855 * Stop group events scheduling transaction
1856 * Clear the flag and pmu::enable() will perform the
1857 * schedulability test.
1859 static void x86_pmu_cancel_txn(struct pmu *pmu)
1861 unsigned int txn_flags;
1862 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1864 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1866 txn_flags = cpuc->txn_flags;
1867 cpuc->txn_flags = 0;
1868 if (txn_flags & ~PERF_PMU_TXN_ADD)
1872 * Truncate collected array by the number of events added in this
1873 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1875 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1876 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1877 perf_pmu_enable(pmu);
1881 * Commit group events scheduling transaction
1882 * Perform the group schedulability test as a whole
1883 * Return 0 if success
1885 * Does not cancel the transaction on failure; expects the caller to do this.
1887 static int x86_pmu_commit_txn(struct pmu *pmu)
1889 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1890 int assign[X86_PMC_IDX_MAX];
1893 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1895 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1896 cpuc->txn_flags = 0;
1902 if (!x86_pmu_initialized())
1905 ret = x86_pmu.schedule_events(cpuc, n, assign);
1910 * copy new assignment, now we know it is possible
1911 * will be used by hw_perf_enable()
1913 memcpy(cpuc->assign, assign, n*sizeof(int));
1915 cpuc->txn_flags = 0;
1916 perf_pmu_enable(pmu);
1920 * a fake_cpuc is used to validate event groups. Due to
1921 * the extra reg logic, we need to also allocate a fake
1922 * per_core and per_cpu structure. Otherwise, group events
1923 * using extra reg may conflict without the kernel being
1924 * able to catch this when the last event gets added to
1927 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1929 kfree(cpuc->shared_regs);
1933 static struct cpu_hw_events *allocate_fake_cpuc(void)
1935 struct cpu_hw_events *cpuc;
1936 int cpu = raw_smp_processor_id();
1938 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1940 return ERR_PTR(-ENOMEM);
1942 /* only needed, if we have extra_regs */
1943 if (x86_pmu.extra_regs) {
1944 cpuc->shared_regs = allocate_shared_regs(cpu);
1945 if (!cpuc->shared_regs)
1951 free_fake_cpuc(cpuc);
1952 return ERR_PTR(-ENOMEM);
1956 * validate that we can schedule this event
1958 static int validate_event(struct perf_event *event)
1960 struct cpu_hw_events *fake_cpuc;
1961 struct event_constraint *c;
1964 fake_cpuc = allocate_fake_cpuc();
1965 if (IS_ERR(fake_cpuc))
1966 return PTR_ERR(fake_cpuc);
1968 c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1970 if (!c || !c->weight)
1973 if (x86_pmu.put_event_constraints)
1974 x86_pmu.put_event_constraints(fake_cpuc, event);
1976 free_fake_cpuc(fake_cpuc);
1982 * validate a single event group
1984 * validation include:
1985 * - check events are compatible which each other
1986 * - events do not compete for the same counter
1987 * - number of events <= number of counters
1989 * validation ensures the group can be loaded onto the
1990 * PMU if it was the only group available.
1992 static int validate_group(struct perf_event *event)
1994 struct perf_event *leader = event->group_leader;
1995 struct cpu_hw_events *fake_cpuc;
1996 int ret = -EINVAL, n;
1998 fake_cpuc = allocate_fake_cpuc();
1999 if (IS_ERR(fake_cpuc))
2000 return PTR_ERR(fake_cpuc);
2002 * the event is not yet connected with its
2003 * siblings therefore we must first collect
2004 * existing siblings, then add the new event
2005 * before we can simulate the scheduling
2007 n = collect_events(fake_cpuc, leader, true);
2011 fake_cpuc->n_events = n;
2012 n = collect_events(fake_cpuc, event, false);
2016 fake_cpuc->n_events = n;
2018 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2021 free_fake_cpuc(fake_cpuc);
2025 static int x86_pmu_event_init(struct perf_event *event)
2030 switch (event->attr.type) {
2032 case PERF_TYPE_HARDWARE:
2033 case PERF_TYPE_HW_CACHE:
2040 err = __x86_pmu_event_init(event);
2043 * we temporarily connect event to its pmu
2044 * such that validate_group() can classify
2045 * it as an x86 event using is_x86_event()
2050 if (event->group_leader != event)
2051 err = validate_group(event);
2053 err = validate_event(event);
2059 event->destroy(event);
2062 if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
2063 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2068 static void refresh_pce(void *ignored)
2071 load_mm_cr4(current->mm);
2074 static void x86_pmu_event_mapped(struct perf_event *event)
2076 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2079 if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1)
2080 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2083 static void x86_pmu_event_unmapped(struct perf_event *event)
2088 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2091 if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed))
2092 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2095 static int x86_pmu_event_idx(struct perf_event *event)
2097 int idx = event->hw.idx;
2099 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2102 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2103 idx -= INTEL_PMC_IDX_FIXED;
2110 static ssize_t get_attr_rdpmc(struct device *cdev,
2111 struct device_attribute *attr,
2114 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2117 static ssize_t set_attr_rdpmc(struct device *cdev,
2118 struct device_attribute *attr,
2119 const char *buf, size_t count)
2124 ret = kstrtoul(buf, 0, &val);
2131 if (x86_pmu.attr_rdpmc_broken)
2134 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2136 * Changing into or out of always available, aka
2137 * perf-event-bypassing mode. This path is extremely slow,
2138 * but only root can trigger it, so it's okay.
2141 static_key_slow_inc(&rdpmc_always_available);
2143 static_key_slow_dec(&rdpmc_always_available);
2144 on_each_cpu(refresh_pce, NULL, 1);
2147 x86_pmu.attr_rdpmc = val;
2152 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2154 static struct attribute *x86_pmu_attrs[] = {
2155 &dev_attr_rdpmc.attr,
2159 static struct attribute_group x86_pmu_attr_group = {
2160 .attrs = x86_pmu_attrs,
2163 static const struct attribute_group *x86_pmu_attr_groups[] = {
2164 &x86_pmu_attr_group,
2165 &x86_pmu_format_group,
2166 &x86_pmu_events_group,
2170 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2172 if (x86_pmu.sched_task)
2173 x86_pmu.sched_task(ctx, sched_in);
2176 void perf_check_microcode(void)
2178 if (x86_pmu.check_microcode)
2179 x86_pmu.check_microcode();
2181 EXPORT_SYMBOL_GPL(perf_check_microcode);
2183 static struct pmu pmu = {
2184 .pmu_enable = x86_pmu_enable,
2185 .pmu_disable = x86_pmu_disable,
2187 .attr_groups = x86_pmu_attr_groups,
2189 .event_init = x86_pmu_event_init,
2191 .event_mapped = x86_pmu_event_mapped,
2192 .event_unmapped = x86_pmu_event_unmapped,
2196 .start = x86_pmu_start,
2197 .stop = x86_pmu_stop,
2198 .read = x86_pmu_read,
2200 .start_txn = x86_pmu_start_txn,
2201 .cancel_txn = x86_pmu_cancel_txn,
2202 .commit_txn = x86_pmu_commit_txn,
2204 .event_idx = x86_pmu_event_idx,
2205 .sched_task = x86_pmu_sched_task,
2206 .task_ctx_size = sizeof(struct x86_perf_task_context),
2209 void arch_perf_update_userpage(struct perf_event *event,
2210 struct perf_event_mmap_page *userpg, u64 now)
2212 struct cyc2ns_data *data;
2214 userpg->cap_user_time = 0;
2215 userpg->cap_user_time_zero = 0;
2216 userpg->cap_user_rdpmc =
2217 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2218 userpg->pmc_width = x86_pmu.cntval_bits;
2220 if (!sched_clock_stable())
2223 data = cyc2ns_read_begin();
2226 * Internal timekeeping for enabled/running/stopped times
2227 * is always in the local_clock domain.
2229 userpg->cap_user_time = 1;
2230 userpg->time_mult = data->cyc2ns_mul;
2231 userpg->time_shift = data->cyc2ns_shift;
2232 userpg->time_offset = data->cyc2ns_offset - now;
2235 * cap_user_time_zero doesn't make sense when we're using a different
2236 * time base for the records.
2238 if (!event->attr.use_clockid) {
2239 userpg->cap_user_time_zero = 1;
2240 userpg->time_zero = data->cyc2ns_offset;
2243 cyc2ns_read_end(data);
2250 static int backtrace_stack(void *data, char *name)
2255 static int backtrace_address(void *data, unsigned long addr, int reliable)
2257 struct perf_callchain_entry_ctx *entry = data;
2259 return perf_callchain_store(entry, addr);
2262 static const struct stacktrace_ops backtrace_ops = {
2263 .stack = backtrace_stack,
2264 .address = backtrace_address,
2265 .walk_stack = print_context_stack_bp,
2269 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2271 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2272 /* TODO: We don't support guest os callchain now */
2276 perf_callchain_store(entry, regs->ip);
2278 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2282 valid_user_frame(const void __user *fp, unsigned long size)
2284 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2287 static unsigned long get_segment_base(unsigned int segment)
2289 struct desc_struct *desc;
2290 int idx = segment >> 3;
2292 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2293 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2294 struct ldt_struct *ldt;
2296 if (idx > LDT_ENTRIES)
2299 /* IRQs are off, so this synchronizes with smp_store_release */
2300 ldt = lockless_dereference(current->active_mm->context.ldt);
2301 if (!ldt || idx > ldt->size)
2304 desc = &ldt->entries[idx];
2309 if (idx > GDT_ENTRIES)
2312 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2315 return get_desc_base(desc);
2318 #ifdef CONFIG_IA32_EMULATION
2320 #include <asm/compat.h>
2323 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2325 /* 32-bit process in 64-bit kernel. */
2326 unsigned long ss_base, cs_base;
2327 struct stack_frame_ia32 frame;
2328 const void __user *fp;
2330 if (!test_thread_flag(TIF_IA32))
2333 cs_base = get_segment_base(regs->cs);
2334 ss_base = get_segment_base(regs->ss);
2336 fp = compat_ptr(ss_base + regs->bp);
2337 pagefault_disable();
2338 while (entry->nr < entry->max_stack) {
2339 unsigned long bytes;
2340 frame.next_frame = 0;
2341 frame.return_address = 0;
2343 if (!access_ok(VERIFY_READ, fp, 8))
2346 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2349 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2353 if (!valid_user_frame(fp, sizeof(frame)))
2356 perf_callchain_store(entry, cs_base + frame.return_address);
2357 fp = compat_ptr(ss_base + frame.next_frame);
2364 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2371 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2373 struct stack_frame frame;
2374 const unsigned long __user *fp;
2376 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2377 /* TODO: We don't support guest os callchain now */
2382 * We don't know what to do with VM86 stacks.. ignore them for now.
2384 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2387 fp = (unsigned long __user *)regs->bp;
2389 perf_callchain_store(entry, regs->ip);
2394 if (perf_callchain_user32(regs, entry))
2397 pagefault_disable();
2398 while (entry->nr < entry->max_stack) {
2399 unsigned long bytes;
2401 frame.next_frame = NULL;
2402 frame.return_address = 0;
2404 if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2))
2407 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2410 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2414 if (!valid_user_frame(fp, sizeof(frame)))
2417 perf_callchain_store(entry, frame.return_address);
2418 fp = (void __user *)frame.next_frame;
2424 * Deal with code segment offsets for the various execution modes:
2426 * VM86 - the good olde 16 bit days, where the linear address is
2427 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2429 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2430 * to figure out what the 32bit base address is.
2432 * X32 - has TIF_X32 set, but is running in x86_64
2434 * X86_64 - CS,DS,SS,ES are all zero based.
2436 static unsigned long code_segment_base(struct pt_regs *regs)
2439 * For IA32 we look at the GDT/LDT segment base to convert the
2440 * effective IP to a linear address.
2443 #ifdef CONFIG_X86_32
2445 * If we are in VM86 mode, add the segment offset to convert to a
2448 if (regs->flags & X86_VM_MASK)
2449 return 0x10 * regs->cs;
2451 if (user_mode(regs) && regs->cs != __USER_CS)
2452 return get_segment_base(regs->cs);
2454 if (user_mode(regs) && !user_64bit_mode(regs) &&
2455 regs->cs != __USER32_CS)
2456 return get_segment_base(regs->cs);
2461 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2463 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2464 return perf_guest_cbs->get_guest_ip();
2466 return regs->ip + code_segment_base(regs);
2469 unsigned long perf_misc_flags(struct pt_regs *regs)
2473 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2474 if (perf_guest_cbs->is_user_mode())
2475 misc |= PERF_RECORD_MISC_GUEST_USER;
2477 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2479 if (user_mode(regs))
2480 misc |= PERF_RECORD_MISC_USER;
2482 misc |= PERF_RECORD_MISC_KERNEL;
2485 if (regs->flags & PERF_EFLAGS_EXACT)
2486 misc |= PERF_RECORD_MISC_EXACT_IP;
2491 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2493 cap->version = x86_pmu.version;
2494 cap->num_counters_gp = x86_pmu.num_counters;
2495 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2496 cap->bit_width_gp = x86_pmu.cntval_bits;
2497 cap->bit_width_fixed = x86_pmu.cntval_bits;
2498 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2499 cap->events_mask_len = x86_pmu.events_mask_len;
2501 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);