2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
23 #include <linux/types.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
28 * some size calculation constants
30 #define DEV_TABLE_ENTRY_SIZE 32
31 #define ALIAS_TABLE_ENTRY_SIZE 2
32 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
34 /* Length of the MMIO region for the AMD IOMMU */
35 #define MMIO_REGION_LENGTH 0x4000
37 /* Capability offsets used by the driver */
38 #define MMIO_CAP_HDR_OFFSET 0x00
39 #define MMIO_RANGE_OFFSET 0x0c
40 #define MMIO_MISC_OFFSET 0x10
42 /* Masks, shifts and macros to parse the device range capability */
43 #define MMIO_RANGE_LD_MASK 0xff000000
44 #define MMIO_RANGE_FD_MASK 0x00ff0000
45 #define MMIO_RANGE_BUS_MASK 0x0000ff00
46 #define MMIO_RANGE_LD_SHIFT 24
47 #define MMIO_RANGE_FD_SHIFT 16
48 #define MMIO_RANGE_BUS_SHIFT 8
49 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
50 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
51 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
52 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
54 /* Flag masks for the AMD IOMMU exclusion range */
55 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
56 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
58 /* Used offsets into the MMIO space */
59 #define MMIO_DEV_TABLE_OFFSET 0x0000
60 #define MMIO_CMD_BUF_OFFSET 0x0008
61 #define MMIO_EVT_BUF_OFFSET 0x0010
62 #define MMIO_CONTROL_OFFSET 0x0018
63 #define MMIO_EXCL_BASE_OFFSET 0x0020
64 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
65 #define MMIO_CMD_HEAD_OFFSET 0x2000
66 #define MMIO_CMD_TAIL_OFFSET 0x2008
67 #define MMIO_EVT_HEAD_OFFSET 0x2010
68 #define MMIO_EVT_TAIL_OFFSET 0x2018
69 #define MMIO_STATUS_OFFSET 0x2020
71 /* MMIO status bits */
72 #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
74 /* event logging constants */
75 #define EVENT_ENTRY_SIZE 0x10
76 #define EVENT_TYPE_SHIFT 28
77 #define EVENT_TYPE_MASK 0xf
78 #define EVENT_TYPE_ILL_DEV 0x1
79 #define EVENT_TYPE_IO_FAULT 0x2
80 #define EVENT_TYPE_DEV_TAB_ERR 0x3
81 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
82 #define EVENT_TYPE_ILL_CMD 0x5
83 #define EVENT_TYPE_CMD_HARD_ERR 0x6
84 #define EVENT_TYPE_IOTLB_INV_TO 0x7
85 #define EVENT_TYPE_INV_DEV_REQ 0x8
86 #define EVENT_DEVID_MASK 0xffff
87 #define EVENT_DEVID_SHIFT 0
88 #define EVENT_DOMID_MASK 0xffff
89 #define EVENT_DOMID_SHIFT 0
90 #define EVENT_FLAGS_MASK 0xfff
91 #define EVENT_FLAGS_SHIFT 0x10
93 /* feature control bits */
94 #define CONTROL_IOMMU_EN 0x00ULL
95 #define CONTROL_HT_TUN_EN 0x01ULL
96 #define CONTROL_EVT_LOG_EN 0x02ULL
97 #define CONTROL_EVT_INT_EN 0x03ULL
98 #define CONTROL_COMWAIT_EN 0x04ULL
99 #define CONTROL_PASSPW_EN 0x08ULL
100 #define CONTROL_RESPASSPW_EN 0x09ULL
101 #define CONTROL_COHERENT_EN 0x0aULL
102 #define CONTROL_ISOC_EN 0x0bULL
103 #define CONTROL_CMDBUF_EN 0x0cULL
104 #define CONTROL_PPFLOG_EN 0x0dULL
105 #define CONTROL_PPFINT_EN 0x0eULL
107 /* command specific defines */
108 #define CMD_COMPL_WAIT 0x01
109 #define CMD_INV_DEV_ENTRY 0x02
110 #define CMD_INV_IOMMU_PAGES 0x03
112 #define CMD_COMPL_WAIT_STORE_MASK 0x01
113 #define CMD_COMPL_WAIT_INT_MASK 0x02
114 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
115 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
117 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
119 /* macros and definitions for device table entries */
120 #define DEV_ENTRY_VALID 0x00
121 #define DEV_ENTRY_TRANSLATION 0x01
122 #define DEV_ENTRY_IR 0x3d
123 #define DEV_ENTRY_IW 0x3e
124 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
125 #define DEV_ENTRY_EX 0x67
126 #define DEV_ENTRY_SYSMGT1 0x68
127 #define DEV_ENTRY_SYSMGT2 0x69
128 #define DEV_ENTRY_INIT_PASS 0xb8
129 #define DEV_ENTRY_EINT_PASS 0xb9
130 #define DEV_ENTRY_NMI_PASS 0xba
131 #define DEV_ENTRY_LINT0_PASS 0xbe
132 #define DEV_ENTRY_LINT1_PASS 0xbf
133 #define DEV_ENTRY_MODE_MASK 0x07
134 #define DEV_ENTRY_MODE_SHIFT 0x09
136 /* constants to configure the command buffer */
137 #define CMD_BUFFER_SIZE 8192
138 #define CMD_BUFFER_ENTRIES 512
139 #define MMIO_CMD_SIZE_SHIFT 56
140 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
142 /* constants for event buffer handling */
143 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
144 #define EVT_LEN_MASK (0x9ULL << 56)
146 #define PAGE_MODE_NONE 0x00
147 #define PAGE_MODE_1_LEVEL 0x01
148 #define PAGE_MODE_2_LEVEL 0x02
149 #define PAGE_MODE_3_LEVEL 0x03
150 #define PAGE_MODE_4_LEVEL 0x04
151 #define PAGE_MODE_5_LEVEL 0x05
152 #define PAGE_MODE_6_LEVEL 0x06
154 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
155 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
156 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
157 (0xffffffffffffffffULL))
158 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
159 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
160 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
161 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
162 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
165 #define PM_ADDR_MASK 0x000ffffffffff000ULL
166 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
167 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
168 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
170 #define IOMMU_PTE_P (1ULL << 0)
171 #define IOMMU_PTE_TV (1ULL << 1)
172 #define IOMMU_PTE_U (1ULL << 59)
173 #define IOMMU_PTE_FC (1ULL << 60)
174 #define IOMMU_PTE_IR (1ULL << 61)
175 #define IOMMU_PTE_IW (1ULL << 62)
177 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
178 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
179 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
180 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
182 #define IOMMU_PROT_MASK 0x03
183 #define IOMMU_PROT_IR 0x01
184 #define IOMMU_PROT_IW 0x02
186 /* IOMMU capabilities */
187 #define IOMMU_CAP_IOTLB 24
188 #define IOMMU_CAP_NPCACHE 26
190 #define MAX_DOMAIN_ID 65536
192 /* FIXME: move this macro to <linux/pci.h> */
193 #define PCI_BUS(x) (((x) >> 8) & 0xff)
195 /* Protection domain flags */
196 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
197 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
198 domain for an IOMMU */
199 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
202 extern bool amd_iommu_dump;
203 #define DUMP_printk(format, arg...) \
205 if (amd_iommu_dump) \
206 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
210 * Make iterating over all IOMMUs easier
212 #define for_each_iommu(iommu) \
213 list_for_each_entry((iommu), &amd_iommu_list, list)
214 #define for_each_iommu_safe(iommu, next) \
215 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
217 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
218 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
219 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
220 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
221 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
222 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
225 * This structure contains generic data for IOMMU protection domains
226 * independent of their use.
228 struct protection_domain {
229 spinlock_t lock; /* mostly used to lock the page table*/
230 u16 id; /* the domain id written to the device table */
231 int mode; /* paging mode (0-6 levels) */
232 u64 *pt_root; /* page table root pointer */
233 unsigned long flags; /* flags to find out type of domain */
234 bool updated; /* complete domain flush required */
235 unsigned dev_cnt; /* devices assigned to this domain */
236 void *priv; /* private data */
240 * For dynamic growth the aperture size is split into ranges of 128MB of
241 * DMA address space each. This struct represents one such range.
243 struct aperture_range {
245 /* address allocation bitmap */
246 unsigned long *bitmap;
249 * Array of PTE pages for the aperture. In this array we save all the
250 * leaf pages of the domain page table used for the aperture. This way
251 * we don't need to walk the page table to find a specific PTE. We can
252 * just calculate its address in constant time.
256 unsigned long offset;
260 * Data container for a dma_ops specific protection domain
262 struct dma_ops_domain {
263 struct list_head list;
265 /* generic protection domain information */
266 struct protection_domain domain;
268 /* size of the aperture for the mappings */
269 unsigned long aperture_size;
271 /* address we start to search for free addresses */
272 unsigned long next_address;
274 /* address space relevant data */
275 struct aperture_range *aperture[APERTURE_MAX_RANGES];
277 /* This will be set to true when TLB needs to be flushed */
281 * if this is a preallocated domain, keep the device for which it was
282 * preallocated in this variable
288 * Structure where we save information about one hardware AMD IOMMU in the
292 struct list_head list;
294 /* locks the accesses to the hardware */
297 /* Pointer to PCI device of this IOMMU */
300 /* physical address of MMIO space */
302 /* virtual address of MMIO space */
305 /* capabilities of that IOMMU read from ACPI */
309 * Capability pointer. There could be more than one IOMMU per PCI
310 * device function if there are more than one AMD IOMMU capability
315 /* pci domain of this IOMMU */
318 /* first device this IOMMU handles. read from PCI */
320 /* last device this IOMMU handles. read from PCI */
323 /* start of exclusion range of that IOMMU */
325 /* length of exclusion range of that IOMMU */
326 u64 exclusion_length;
328 /* command buffer virtual address */
330 /* size of command buffer */
333 /* size of event buffer */
335 /* event buffer virtual address */
337 /* MSI number for event interrupt */
340 /* true if interrupts for this IOMMU are already enabled */
343 /* if one, we need to send a completion wait command */
346 /* becomes true if a command buffer reset is running */
347 bool reset_in_progress;
349 /* default dma_ops domain for that IOMMU */
350 struct dma_ops_domain *default_dom;
354 * List with all IOMMUs in the system. This list is not locked because it is
355 * only written and read at driver initialization or suspend time
357 extern struct list_head amd_iommu_list;
360 * Structure defining one entry in the device table
362 struct dev_table_entry {
367 * One entry for unity mappings parsed out of the ACPI table.
369 struct unity_map_entry {
370 struct list_head list;
372 /* starting device id this entry is used for (including) */
374 /* end device id this entry is used for (including) */
377 /* start address to unity map (including) */
379 /* end address to unity map (including) */
382 /* required protection */
387 * List of all unity mappings. It is not locked because as runtime it is only
388 * read. It is created at ACPI table parsing time.
390 extern struct list_head amd_iommu_unity_map;
393 * Data structures for device handling
397 * Device table used by hardware. Read and write accesses by software are
398 * locked with the amd_iommu_pd_table lock.
400 extern struct dev_table_entry *amd_iommu_dev_table;
403 * Alias table to find requestor ids to device ids. Not locked because only
406 extern u16 *amd_iommu_alias_table;
409 * Reverse lookup table to find the IOMMU which translates a specific device.
411 extern struct amd_iommu **amd_iommu_rlookup_table;
413 /* size of the dma_ops aperture as power of 2 */
414 extern unsigned amd_iommu_aperture_order;
416 /* largest PCI device id we expect translation requests for */
417 extern u16 amd_iommu_last_bdf;
419 /* data structures for protection domain handling */
420 extern struct protection_domain **amd_iommu_pd_table;
422 /* allocation bitmap for domain ids */
423 extern unsigned long *amd_iommu_pd_alloc_bitmap;
425 /* will be 1 if device isolation is enabled */
426 extern bool amd_iommu_isolate;
429 * If true, the addresses will be flushed on unmap time, not when
432 extern bool amd_iommu_unmap_flush;
434 /* takes bus and device/function and returns the device id
435 * FIXME: should that be in generic PCI code? */
436 static inline u16 calc_devid(u8 bus, u8 devfn)
438 return (((u16)bus) << 8) | devfn;
441 #ifdef CONFIG_AMD_IOMMU_STATS
443 struct __iommu_counter {
449 #define DECLARE_STATS_COUNTER(nm) \
450 static struct __iommu_counter nm = { \
454 #define INC_STATS_COUNTER(name) name.value += 1
455 #define ADD_STATS_COUNTER(name, x) name.value += (x)
456 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
458 #else /* CONFIG_AMD_IOMMU_STATS */
460 #define DECLARE_STATS_COUNTER(name)
461 #define INC_STATS_COUNTER(name)
462 #define ADD_STATS_COUNTER(name, x)
463 #define SUB_STATS_COUNTER(name, x)
465 static inline void amd_iommu_stats_init(void) { }
467 #endif /* CONFIG_AMD_IOMMU_STATS */
469 /* some function prototypes */
470 extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
472 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */