1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <asm/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
14 #include <asm/system.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
27 * Define the default level of output to be very little
28 * This can be turned up by using apic=verbose for more
29 * information and apic=debug for _lots_ of information.
30 * apic_verbosity is defined in apic.c
32 #define apic_printk(v, s, a...) do { \
33 if ((v) <= apic_verbosity) \
38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
39 extern void generic_apic_probe(void);
41 static inline void generic_apic_probe(void)
46 #ifdef CONFIG_X86_LOCAL_APIC
48 extern unsigned int apic_verbosity;
49 extern int local_apic_timer_c2_ok;
51 extern int disable_apic;
54 extern void __inquire_remote_apic(int apicid);
55 #else /* CONFIG_SMP */
56 static inline void __inquire_remote_apic(int apicid)
59 #endif /* CONFIG_SMP */
61 static inline void default_inquire_remote_apic(int apicid)
63 if (apic_verbosity >= APIC_DEBUG)
64 __inquire_remote_apic(apicid);
68 * With 82489DX we can't rely on apic feature bit
69 * retrieved via cpuid but still have to deal with
70 * such an apic chip so we assume that SMP configuration
71 * is found from MP table (64bit case uses ACPI mostly
72 * which set smp presence flag as well so we are safe
73 * to use this helper too).
75 static inline bool apic_from_smp_config(void)
77 return smp_found_config && !disable_apic;
81 * Basic functions accessing APICs.
83 #ifdef CONFIG_PARAVIRT
84 #include <asm/paravirt.h>
88 extern int is_vsmp_box(void);
90 static inline int is_vsmp_box(void)
95 extern void xapic_wait_icr_idle(void);
96 extern u32 safe_xapic_wait_icr_idle(void);
97 extern void xapic_icr_write(u32, u32);
98 extern int setup_profiling_timer(unsigned int);
100 static inline void native_apic_mem_write(u32 reg, u32 v)
102 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
104 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
105 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
106 ASM_OUTPUT2("0" (v), "m" (*addr)));
109 static inline u32 native_apic_mem_read(u32 reg)
111 return *((volatile u32 *)(APIC_BASE + reg));
114 extern void native_apic_wait_icr_idle(void);
115 extern u32 native_safe_apic_wait_icr_idle(void);
116 extern void native_apic_icr_write(u32 low, u32 id);
117 extern u64 native_apic_icr_read(void);
119 extern int x2apic_mode;
121 #ifdef CONFIG_X86_X2APIC
123 * Make previous memory operations globally visible before
124 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
127 static inline void x2apic_wrmsr_fence(void)
129 asm volatile("mfence" : : : "memory");
132 static inline void native_apic_msr_write(u32 reg, u32 v)
134 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
138 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
141 static inline u32 native_apic_msr_read(u32 reg)
148 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
152 static inline void native_x2apic_wait_icr_idle(void)
154 /* no need to wait for icr idle in x2apic */
158 static inline u32 native_safe_x2apic_wait_icr_idle(void)
160 /* no need to wait for icr idle in x2apic */
164 static inline void native_x2apic_icr_write(u32 low, u32 id)
166 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
169 static inline u64 native_x2apic_icr_read(void)
173 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
177 extern int x2apic_phys;
178 extern void check_x2apic(void);
179 extern void enable_x2apic(void);
180 extern void x2apic_icr_write(u32 low, u32 id);
181 static inline int x2apic_enabled(void)
188 rdmsrl(MSR_IA32_APICBASE, msr);
189 if (msr & X2APIC_ENABLE)
194 #define x2apic_supported() (cpu_has_x2apic)
195 static inline void x2apic_force_phys(void)
200 static inline void check_x2apic(void)
203 static inline void enable_x2apic(void)
206 static inline int x2apic_enabled(void)
210 static inline void x2apic_force_phys(void)
214 #define x2apic_preenabled 0
215 #define x2apic_supported() 0
218 extern void enable_IR_x2apic(void);
220 extern int get_physical_broadcast(void);
222 extern int lapic_get_maxlvt(void);
223 extern void clear_local_APIC(void);
224 extern void connect_bsp_APIC(void);
225 extern void disconnect_bsp_APIC(int virt_wire_setup);
226 extern void disable_local_APIC(void);
227 extern void lapic_shutdown(void);
228 extern int verify_local_APIC(void);
229 extern void sync_Arb_IDs(void);
230 extern void init_bsp_APIC(void);
231 extern void setup_local_APIC(void);
232 extern void end_local_APIC_setup(void);
233 extern void bsp_end_local_APIC_setup(void);
234 extern void init_apic_mappings(void);
235 void register_lapic_address(unsigned long address);
236 extern void setup_boot_APIC_clock(void);
237 extern void setup_secondary_APIC_clock(void);
238 extern int APIC_init_uniprocessor(void);
239 extern int apic_force_enable(unsigned long addr);
242 * On 32bit this is mach-xxx local
245 extern int apic_is_clustered_box(void);
247 static inline int apic_is_clustered_box(void)
253 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
255 #else /* !CONFIG_X86_LOCAL_APIC */
256 static inline void lapic_shutdown(void) { }
257 #define local_apic_timer_c2_ok 1
258 static inline void init_apic_mappings(void) { }
259 static inline void disable_local_APIC(void) { }
260 # define setup_boot_APIC_clock x86_init_noop
261 # define setup_secondary_APIC_clock x86_init_noop
262 #endif /* !CONFIG_X86_LOCAL_APIC */
265 #define SET_APIC_ID(x) (apic->set_apic_id(x))
271 * Copyright 2004 James Cleverdon, IBM.
272 * Subject to the GNU Public License, v.2
274 * Generic APIC sub-arch data struct.
276 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
277 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
284 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
285 int (*apic_id_registered)(void);
287 u32 irq_delivery_mode;
290 const struct cpumask *(*target_cpus)(void);
295 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
296 unsigned long (*check_apicid_present)(int apicid);
298 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
299 void (*init_apic_ldr)(void);
301 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
303 void (*setup_apic_routing)(void);
304 int (*multi_timer_check)(int apic, int irq);
305 int (*cpu_present_to_apicid)(int mps_cpu);
306 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
307 void (*setup_portio_remap)(void);
308 int (*check_phys_apicid_present)(int phys_apicid);
309 void (*enable_apic_mode)(void);
310 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
313 * When one of the next two hooks returns 1 the apic
314 * is switched to this. Essentially they are additional
317 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
319 unsigned int (*get_apic_id)(unsigned long x);
320 unsigned long (*set_apic_id)(unsigned int id);
321 unsigned long apic_id_mask;
323 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
324 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
325 const struct cpumask *andmask);
328 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
329 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
331 void (*send_IPI_allbutself)(int vector);
332 void (*send_IPI_all)(int vector);
333 void (*send_IPI_self)(int vector);
335 /* wakeup_secondary_cpu */
336 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
338 int trampoline_phys_low;
339 int trampoline_phys_high;
341 void (*wait_for_init_deassert)(atomic_t *deassert);
342 void (*smp_callin_clear_local_apic)(void);
343 void (*inquire_remote_apic)(int apicid);
346 u32 (*read)(u32 reg);
347 void (*write)(u32 reg, u32 v);
348 u64 (*icr_read)(void);
349 void (*icr_write)(u32 low, u32 high);
350 void (*wait_icr_idle)(void);
351 u32 (*safe_wait_icr_idle)(void);
355 * Called very early during boot from get_smp_config(). It should
356 * return the logical apicid. x86_[bios]_cpu_to_apicid is
357 * initialized before this function is called.
359 * If logical apicid can't be determined that early, the function
360 * may return BAD_APICID. Logical apicid will be configured after
361 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
362 * won't be applied properly during early boot in this case.
364 int (*x86_32_early_logical_apicid)(int cpu);
367 * Optional method called from setup_local_APIC() after logical
368 * apicid is guaranteed to be known to initialize apicid -> node
369 * mapping if NUMA initialization hasn't done so already. Don't
372 int (*x86_32_numa_cpu_node)(int cpu);
377 * Pointer to the local APIC driver in use on this system (there's
378 * always just one such driver in use - the kernel decides via an
379 * early probing process which one it picks - and then sticks to it):
381 extern struct apic *apic;
384 * APIC drivers are probed based on how they are listed in the .apicdrivers
385 * section. So the order is important and enforced by the ordering
386 * of different apic driver files in the Makefile.
388 * For the files having two apic drivers, we use apic_drivers()
389 * to enforce the order with in them.
391 #define apic_driver(sym) \
392 static struct apic *__apicdrivers_##sym __used \
393 __aligned(sizeof(struct apic *)) \
394 __section(.apicdrivers) = { &sym }
396 #define apic_drivers(sym1, sym2) \
397 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
398 __aligned(sizeof(struct apic *)) \
399 __section(.apicdrivers) = { &sym1, &sym2 }
401 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
404 * APIC functionality to boot other CPUs - only used on SMP:
407 extern atomic_t init_deasserted;
408 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
411 #ifdef CONFIG_X86_LOCAL_APIC
412 static inline u32 apic_read(u32 reg)
414 return apic->read(reg);
417 static inline void apic_write(u32 reg, u32 val)
419 apic->write(reg, val);
422 static inline u64 apic_icr_read(void)
424 return apic->icr_read();
427 static inline void apic_icr_write(u32 low, u32 high)
429 apic->icr_write(low, high);
432 static inline void apic_wait_icr_idle(void)
434 apic->wait_icr_idle();
437 static inline u32 safe_apic_wait_icr_idle(void)
439 return apic->safe_wait_icr_idle();
442 #else /* CONFIG_X86_LOCAL_APIC */
444 static inline u32 apic_read(u32 reg) { return 0; }
445 static inline void apic_write(u32 reg, u32 val) { }
446 static inline u64 apic_icr_read(void) { return 0; }
447 static inline void apic_icr_write(u32 low, u32 high) { }
448 static inline void apic_wait_icr_idle(void) { }
449 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
451 #endif /* CONFIG_X86_LOCAL_APIC */
453 static inline void ack_APIC_irq(void)
456 * ack_APIC_irq() actually gets compiled as a single instruction
460 /* Docs say use 0 for future compatibility */
461 apic_write(APIC_EOI, 0);
464 static inline unsigned default_get_apic_id(unsigned long x)
466 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
468 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
469 return (x >> 24) & 0xFF;
471 return (x >> 24) & 0x0F;
475 * Warm reset vector default position:
477 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
478 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
481 extern int default_acpi_madt_oem_check(char *, char *);
483 extern void apic_send_IPI_self(int vector);
485 DECLARE_PER_CPU(int, x2apic_extra_bits);
487 extern int default_cpu_present_to_apicid(int mps_cpu);
488 extern int default_check_phys_apicid_present(int phys_apicid);
491 static inline void default_wait_for_init_deassert(atomic_t *deassert)
493 while (!atomic_read(deassert))
498 extern struct apic *generic_bigsmp_probe(void);
501 #ifdef CONFIG_X86_LOCAL_APIC
505 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
507 static inline const struct cpumask *default_target_cpus(void)
510 return cpu_online_mask;
512 return cpumask_of(0);
516 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
519 static inline unsigned int read_apic_id(void)
523 reg = apic_read(APIC_ID);
525 return apic->get_apic_id(reg);
528 extern void default_setup_apic_routing(void);
530 extern struct apic apic_noop;
534 static inline int noop_x86_32_early_logical_apicid(int cpu)
540 * Set up the logical destination ID.
542 * Intel recommends to set DFR, LDR and TPR before enabling
543 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
544 * document number 292116). So here it goes...
546 extern void default_init_apic_ldr(void);
548 static inline int default_apic_id_registered(void)
550 return physid_isset(read_apic_id(), phys_cpu_present_map);
553 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
555 return cpuid_apic >> index_msb;
560 static inline unsigned int
561 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
563 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
566 static inline unsigned int
567 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
568 const struct cpumask *andmask)
570 unsigned long mask1 = cpumask_bits(cpumask)[0];
571 unsigned long mask2 = cpumask_bits(andmask)[0];
572 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
574 return (unsigned int)(mask1 & mask2 & mask3);
577 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
579 return physid_isset(apicid, *map);
582 static inline unsigned long default_check_apicid_present(int bit)
584 return physid_isset(bit, phys_cpu_present_map);
587 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
592 static inline int __default_cpu_present_to_apicid(int mps_cpu)
594 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
595 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
601 __default_check_phys_apicid_present(int phys_apicid)
603 return physid_isset(phys_apicid, phys_cpu_present_map);
607 static inline int default_cpu_present_to_apicid(int mps_cpu)
609 return __default_cpu_present_to_apicid(mps_cpu);
613 default_check_phys_apicid_present(int phys_apicid)
615 return __default_check_phys_apicid_present(phys_apicid);
618 extern int default_cpu_present_to_apicid(int mps_cpu);
619 extern int default_check_phys_apicid_present(int phys_apicid);
622 #endif /* CONFIG_X86_LOCAL_APIC */
624 #endif /* _ASM_X86_APIC_H */