1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
22 #define APIC_VERBOSE 1
25 /* Macros for apic_extnmi which controls external NMI masking */
26 #define APIC_EXTNMI_BSP 0 /* Default */
27 #define APIC_EXTNMI_ALL 1
28 #define APIC_EXTNMI_NONE 2
31 * Define the default level of output to be very little
32 * This can be turned up by using apic=verbose for more
33 * information and apic=debug for _lots_ of information.
34 * apic_verbosity is defined in apic.c
36 #define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43 extern void generic_apic_probe(void);
45 static inline void generic_apic_probe(void)
50 #ifdef CONFIG_X86_LOCAL_APIC
52 extern unsigned int apic_verbosity;
53 extern int local_apic_timer_c2_ok;
55 extern int disable_apic;
56 extern unsigned int lapic_timer_frequency;
59 extern void __inquire_remote_apic(int apicid);
60 #else /* CONFIG_SMP */
61 static inline void __inquire_remote_apic(int apicid)
64 #endif /* CONFIG_SMP */
66 static inline void default_inquire_remote_apic(int apicid)
68 if (apic_verbosity >= APIC_DEBUG)
69 __inquire_remote_apic(apicid);
73 * With 82489DX we can't rely on apic feature bit
74 * retrieved via cpuid but still have to deal with
75 * such an apic chip so we assume that SMP configuration
76 * is found from MP table (64bit case uses ACPI mostly
77 * which set smp presence flag as well so we are safe
78 * to use this helper too).
80 static inline bool apic_from_smp_config(void)
82 return smp_found_config && !disable_apic;
86 * Basic functions accessing APICs.
88 #ifdef CONFIG_PARAVIRT
89 #include <asm/paravirt.h>
92 extern int setup_profiling_timer(unsigned int);
94 static inline void native_apic_mem_write(u32 reg, u32 v)
96 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
98 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
99 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
100 ASM_OUTPUT2("0" (v), "m" (*addr)));
103 static inline u32 native_apic_mem_read(u32 reg)
105 return *((volatile u32 *)(APIC_BASE + reg));
108 extern void native_apic_wait_icr_idle(void);
109 extern u32 native_safe_apic_wait_icr_idle(void);
110 extern void native_apic_icr_write(u32 low, u32 id);
111 extern u64 native_apic_icr_read(void);
113 static inline bool apic_is_x2apic_enabled(void)
117 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
119 return msr & X2APIC_ENABLE;
122 extern void enable_IR_x2apic(void);
124 extern int get_physical_broadcast(void);
126 extern int lapic_get_maxlvt(void);
127 extern void clear_local_APIC(void);
128 extern void disconnect_bsp_APIC(int virt_wire_setup);
129 extern void disable_local_APIC(void);
130 extern void lapic_shutdown(void);
131 extern void sync_Arb_IDs(void);
132 extern void init_bsp_APIC(void);
133 extern void setup_local_APIC(void);
134 extern void init_apic_mappings(void);
135 void register_lapic_address(unsigned long address);
136 extern void setup_boot_APIC_clock(void);
137 extern void setup_secondary_APIC_clock(void);
138 extern void lapic_update_tsc_freq(void);
139 extern int APIC_init_uniprocessor(void);
142 static inline int apic_force_enable(unsigned long addr)
147 extern int apic_force_enable(unsigned long addr);
150 extern int apic_bsp_setup(bool upmode);
151 extern void apic_ap_setup(void);
154 * On 32bit this is mach-xxx local
157 extern int apic_is_clustered_box(void);
159 static inline int apic_is_clustered_box(void)
165 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
167 #else /* !CONFIG_X86_LOCAL_APIC */
168 static inline void lapic_shutdown(void) { }
169 #define local_apic_timer_c2_ok 1
170 static inline void init_apic_mappings(void) { }
171 static inline void disable_local_APIC(void) { }
172 # define setup_boot_APIC_clock x86_init_noop
173 # define setup_secondary_APIC_clock x86_init_noop
174 static inline void lapic_update_tsc_freq(void) { }
175 #endif /* !CONFIG_X86_LOCAL_APIC */
177 #ifdef CONFIG_X86_X2APIC
179 * Make previous memory operations globally visible before
180 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
183 static inline void x2apic_wrmsr_fence(void)
185 asm volatile("mfence" : : : "memory");
188 static inline void native_apic_msr_write(u32 reg, u32 v)
190 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
194 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
197 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
199 wrmsr_notrace(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
202 static inline u32 native_apic_msr_read(u32 reg)
209 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
213 static inline void native_x2apic_wait_icr_idle(void)
215 /* no need to wait for icr idle in x2apic */
219 static inline u32 native_safe_x2apic_wait_icr_idle(void)
221 /* no need to wait for icr idle in x2apic */
225 static inline void native_x2apic_icr_write(u32 low, u32 id)
227 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
230 static inline u64 native_x2apic_icr_read(void)
234 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
238 extern int x2apic_mode;
239 extern int x2apic_phys;
240 extern void __init check_x2apic(void);
241 extern void x2apic_setup(void);
242 static inline int x2apic_enabled(void)
244 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
247 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
248 #else /* !CONFIG_X86_X2APIC */
249 static inline void check_x2apic(void) { }
250 static inline void x2apic_setup(void) { }
251 static inline int x2apic_enabled(void) { return 0; }
253 #define x2apic_mode (0)
254 #define x2apic_supported() (0)
255 #endif /* !CONFIG_X86_X2APIC */
258 #define SET_APIC_ID(x) (apic->set_apic_id(x))
264 * Copyright 2004 James Cleverdon, IBM.
265 * Subject to the GNU Public License, v.2
267 * Generic APIC sub-arch data struct.
269 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
270 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
277 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
278 int (*apic_id_valid)(int apicid);
279 int (*apic_id_registered)(void);
281 u32 irq_delivery_mode;
284 const struct cpumask *(*target_cpus)(void);
289 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
291 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
292 const struct cpumask *mask);
293 void (*init_apic_ldr)(void);
295 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
297 void (*setup_apic_routing)(void);
298 int (*cpu_present_to_apicid)(int mps_cpu);
299 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
300 int (*check_phys_apicid_present)(int phys_apicid);
301 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
303 unsigned int (*get_apic_id)(unsigned long x);
304 unsigned long (*set_apic_id)(unsigned int id);
306 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
307 const struct cpumask *andmask,
308 unsigned int *apicid);
311 void (*send_IPI)(int cpu, int vector);
312 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
313 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
315 void (*send_IPI_allbutself)(int vector);
316 void (*send_IPI_all)(int vector);
317 void (*send_IPI_self)(int vector);
319 /* wakeup_secondary_cpu */
320 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
322 void (*inquire_remote_apic)(int apicid);
325 u32 (*read)(u32 reg);
326 void (*write)(u32 reg, u32 v);
328 * ->eoi_write() has the same signature as ->write().
330 * Drivers can support both ->eoi_write() and ->write() by passing the same
331 * callback value. Kernel can override ->eoi_write() and fall back
334 void (*eoi_write)(u32 reg, u32 v);
335 void (*native_eoi_write)(u32 reg, u32 v);
336 u64 (*icr_read)(void);
337 void (*icr_write)(u32 low, u32 high);
338 void (*wait_icr_idle)(void);
339 u32 (*safe_wait_icr_idle)(void);
343 * Called very early during boot from get_smp_config(). It should
344 * return the logical apicid. x86_[bios]_cpu_to_apicid is
345 * initialized before this function is called.
347 * If logical apicid can't be determined that early, the function
348 * may return BAD_APICID. Logical apicid will be configured after
349 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
350 * won't be applied properly during early boot in this case.
352 int (*x86_32_early_logical_apicid)(int cpu);
357 * Pointer to the local APIC driver in use on this system (there's
358 * always just one such driver in use - the kernel decides via an
359 * early probing process which one it picks - and then sticks to it):
361 extern struct apic *apic;
364 * APIC drivers are probed based on how they are listed in the .apicdrivers
365 * section. So the order is important and enforced by the ordering
366 * of different apic driver files in the Makefile.
368 * For the files having two apic drivers, we use apic_drivers()
369 * to enforce the order with in them.
371 #define apic_driver(sym) \
372 static const struct apic *__apicdrivers_##sym __used \
373 __aligned(sizeof(struct apic *)) \
374 __section(.apicdrivers) = { &sym }
376 #define apic_drivers(sym1, sym2) \
377 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
378 __aligned(sizeof(struct apic *)) \
379 __section(.apicdrivers) = { &sym1, &sym2 }
381 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
384 * APIC functionality to boot other CPUs - only used on SMP:
387 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
390 #ifdef CONFIG_X86_LOCAL_APIC
392 static inline u32 apic_read(u32 reg)
394 return apic->read(reg);
397 static inline void apic_write(u32 reg, u32 val)
399 apic->write(reg, val);
402 static inline void apic_eoi(void)
404 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
407 static inline u64 apic_icr_read(void)
409 return apic->icr_read();
412 static inline void apic_icr_write(u32 low, u32 high)
414 apic->icr_write(low, high);
417 static inline void apic_wait_icr_idle(void)
419 apic->wait_icr_idle();
422 static inline u32 safe_apic_wait_icr_idle(void)
424 return apic->safe_wait_icr_idle();
427 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
429 #else /* CONFIG_X86_LOCAL_APIC */
431 static inline u32 apic_read(u32 reg) { return 0; }
432 static inline void apic_write(u32 reg, u32 val) { }
433 static inline void apic_eoi(void) { }
434 static inline u64 apic_icr_read(void) { return 0; }
435 static inline void apic_icr_write(u32 low, u32 high) { }
436 static inline void apic_wait_icr_idle(void) { }
437 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
438 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
440 #endif /* CONFIG_X86_LOCAL_APIC */
442 static inline void ack_APIC_irq(void)
445 * ack_APIC_irq() actually gets compiled as a single instruction
451 static inline unsigned default_get_apic_id(unsigned long x)
453 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
455 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
456 return (x >> 24) & 0xFF;
458 return (x >> 24) & 0x0F;
462 * Warm reset vector position:
464 #define TRAMPOLINE_PHYS_LOW 0x467
465 #define TRAMPOLINE_PHYS_HIGH 0x469
468 extern void apic_send_IPI_self(int vector);
470 DECLARE_PER_CPU(int, x2apic_extra_bits);
472 extern int default_cpu_present_to_apicid(int mps_cpu);
473 extern int default_check_phys_apicid_present(int phys_apicid);
476 extern void generic_bigsmp_probe(void);
479 #ifdef CONFIG_X86_LOCAL_APIC
483 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
485 static inline const struct cpumask *default_target_cpus(void)
488 return cpu_online_mask;
490 return cpumask_of(0);
494 static inline const struct cpumask *online_target_cpus(void)
496 return cpu_online_mask;
499 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
502 static inline unsigned int read_apic_id(void)
506 reg = apic_read(APIC_ID);
508 return apic->get_apic_id(reg);
511 static inline int default_apic_id_valid(int apicid)
513 return (apicid < 255);
516 extern int default_acpi_madt_oem_check(char *, char *);
518 extern void default_setup_apic_routing(void);
520 extern struct apic apic_noop;
524 static inline int noop_x86_32_early_logical_apicid(int cpu)
530 * Set up the logical destination ID.
532 * Intel recommends to set DFR, LDR and TPR before enabling
533 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
534 * document number 292116). So here it goes...
536 extern void default_init_apic_ldr(void);
538 static inline int default_apic_id_registered(void)
540 return physid_isset(read_apic_id(), phys_cpu_present_map);
543 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
545 return cpuid_apic >> index_msb;
551 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
552 const struct cpumask *andmask,
553 unsigned int *apicid)
555 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
556 cpumask_bits(andmask)[0] &
557 cpumask_bits(cpu_online_mask)[0] &
560 if (likely(cpu_mask)) {
561 *apicid = (unsigned int)cpu_mask;
569 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
570 const struct cpumask *andmask,
571 unsigned int *apicid);
574 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
575 const struct cpumask *mask)
577 /* Careful. Some cpus do not strictly honor the set of cpus
578 * specified in the interrupt destination when using lowest
579 * priority interrupt delivery mode.
581 * In particular there was a hyperthreading cpu observed to
582 * deliver interrupts to the wrong hyperthread when only one
583 * hyperthread was specified in the interrupt desitination.
585 cpumask_clear(retmask);
586 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
590 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
591 const struct cpumask *mask)
593 cpumask_copy(retmask, cpumask_of(cpu));
596 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
598 return physid_isset(apicid, *map);
601 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
606 static inline int __default_cpu_present_to_apicid(int mps_cpu)
608 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
609 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
615 __default_check_phys_apicid_present(int phys_apicid)
617 return physid_isset(phys_apicid, phys_cpu_present_map);
621 static inline int default_cpu_present_to_apicid(int mps_cpu)
623 return __default_cpu_present_to_apicid(mps_cpu);
627 default_check_phys_apicid_present(int phys_apicid)
629 return __default_check_phys_apicid_present(phys_apicid);
632 extern int default_cpu_present_to_apicid(int mps_cpu);
633 extern int default_check_phys_apicid_present(int phys_apicid);
636 #endif /* CONFIG_X86_LOCAL_APIC */
637 extern void irq_enter(void);
638 extern void irq_exit(void);
640 static inline void entering_irq(void)
646 static inline void entering_ack_irq(void)
652 static inline void ipi_entering_ack_irq(void)
658 static inline void exiting_irq(void)
663 static inline void exiting_ack_irq(void)
669 extern void ioapic_zap_locks(void);
671 #endif /* _ASM_X86_APIC_H */