1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
5 #include <linux/delay.h>
8 #include <asm/alternative.h>
9 #include <asm/cpufeature.h>
10 #include <asm/processor.h>
11 #include <asm/apicdef.h>
12 #include <asm/atomic.h>
13 #include <asm/fixmap.h>
14 #include <asm/mpspec.h>
15 #include <asm/system.h>
18 #define ARCH_APICTIMER_STOPS_ON_C3 1
24 #define APIC_VERBOSE 1
28 * Define the default level of output to be very little
29 * This can be turned up by using apic=verbose for more
30 * information and apic=debug for _lots_ of information.
31 * apic_verbosity is defined in apic.c
33 #define apic_printk(v, s, a...) do { \
34 if ((v) <= apic_verbosity) \
39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
40 extern void generic_apic_probe(void);
42 static inline void generic_apic_probe(void)
47 #ifdef CONFIG_X86_LOCAL_APIC
49 extern unsigned int apic_verbosity;
50 extern int local_apic_timer_c2_ok;
52 extern int disable_apic;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
76 static inline bool apic_from_smp_config(void)
78 return smp_found_config && !disable_apic;
82 * Basic functions accessing APICs.
84 #ifdef CONFIG_PARAVIRT
85 #include <asm/paravirt.h>
89 extern int is_vsmp_box(void);
91 static inline int is_vsmp_box(void)
96 extern void xapic_wait_icr_idle(void);
97 extern u32 safe_xapic_wait_icr_idle(void);
98 extern void xapic_icr_write(u32, u32);
99 extern int setup_profiling_timer(unsigned int);
101 static inline void native_apic_mem_write(u32 reg, u32 v)
103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
106 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
107 ASM_OUTPUT2("0" (v), "m" (*addr)));
110 static inline u32 native_apic_mem_read(u32 reg)
112 return *((volatile u32 *)(APIC_BASE + reg));
115 extern void native_apic_wait_icr_idle(void);
116 extern u32 native_safe_apic_wait_icr_idle(void);
117 extern void native_apic_icr_write(u32 low, u32 id);
118 extern u64 native_apic_icr_read(void);
120 extern int x2apic_mode;
122 #ifdef CONFIG_X86_X2APIC
124 * Make previous memory operations globally visible before
125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
128 static inline void x2apic_wrmsr_fence(void)
130 asm volatile("mfence" : : : "memory");
133 static inline void native_apic_msr_write(u32 reg, u32 v)
135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
142 static inline u32 native_apic_msr_read(u32 reg)
149 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
153 static inline void native_x2apic_wait_icr_idle(void)
155 /* no need to wait for icr idle in x2apic */
159 static inline u32 native_safe_x2apic_wait_icr_idle(void)
161 /* no need to wait for icr idle in x2apic */
165 static inline void native_x2apic_icr_write(u32 low, u32 id)
167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
170 static inline u64 native_x2apic_icr_read(void)
174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
178 extern int x2apic_phys;
179 extern void check_x2apic(void);
180 extern void enable_x2apic(void);
181 extern void x2apic_icr_write(u32 low, u32 id);
182 static inline int x2apic_enabled(void)
189 rdmsr(MSR_IA32_APICBASE, msr, msr2);
190 if (msr & X2APIC_ENABLE)
195 #define x2apic_supported() (cpu_has_x2apic)
196 static inline void x2apic_force_phys(void)
201 static inline void check_x2apic(void)
204 static inline void enable_x2apic(void)
207 static inline int x2apic_enabled(void)
211 static inline void x2apic_force_phys(void)
215 #define x2apic_preenabled 0
216 #define x2apic_supported() 0
219 extern void enable_IR_x2apic(void);
221 extern int get_physical_broadcast(void);
223 extern void apic_disable(void);
224 extern int lapic_get_maxlvt(void);
225 extern void clear_local_APIC(void);
226 extern void connect_bsp_APIC(void);
227 extern void disconnect_bsp_APIC(int virt_wire_setup);
228 extern void disable_local_APIC(void);
229 extern void lapic_shutdown(void);
230 extern int verify_local_APIC(void);
231 extern void cache_APIC_registers(void);
232 extern void sync_Arb_IDs(void);
233 extern void init_bsp_APIC(void);
234 extern void setup_local_APIC(void);
235 extern void end_local_APIC_setup(void);
236 extern void init_apic_mappings(void);
237 extern void setup_boot_APIC_clock(void);
238 extern void setup_secondary_APIC_clock(void);
239 extern int APIC_init_uniprocessor(void);
240 extern void enable_NMI_through_LVT0(void);
243 * On 32bit this is mach-xxx local
246 extern void early_init_lapic_mapping(void);
247 extern int apic_is_clustered_box(void);
249 static inline int apic_is_clustered_box(void)
255 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
256 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
259 #else /* !CONFIG_X86_LOCAL_APIC */
260 static inline void lapic_shutdown(void) { }
261 #define local_apic_timer_c2_ok 1
262 static inline void init_apic_mappings(void) { }
263 static inline void disable_local_APIC(void) { }
264 static inline void apic_disable(void) { }
265 # define setup_boot_APIC_clock x86_init_noop
266 # define setup_secondary_APIC_clock x86_init_noop
267 #endif /* !CONFIG_X86_LOCAL_APIC */
270 #define SET_APIC_ID(x) (apic->set_apic_id(x))
276 * Copyright 2004 James Cleverdon, IBM.
277 * Subject to the GNU Public License, v.2
279 * Generic APIC sub-arch data struct.
281 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
282 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
289 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
290 int (*apic_id_registered)(void);
292 u32 irq_delivery_mode;
295 const struct cpumask *(*target_cpus)(void);
300 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
301 unsigned long (*check_apicid_present)(int apicid);
303 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
304 void (*init_apic_ldr)(void);
306 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
308 void (*setup_apic_routing)(void);
309 int (*multi_timer_check)(int apic, int irq);
310 int (*apicid_to_node)(int logical_apicid);
311 int (*cpu_to_logical_apicid)(int cpu);
312 int (*cpu_present_to_apicid)(int mps_cpu);
313 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
314 void (*setup_portio_remap)(void);
315 int (*check_phys_apicid_present)(int phys_apicid);
316 void (*enable_apic_mode)(void);
317 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
320 * When one of the next two hooks returns 1 the apic
321 * is switched to this. Essentially they are additional
324 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
326 unsigned int (*get_apic_id)(unsigned long x);
327 unsigned long (*set_apic_id)(unsigned int id);
328 unsigned long apic_id_mask;
330 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
331 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
332 const struct cpumask *andmask);
335 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
336 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
338 void (*send_IPI_allbutself)(int vector);
339 void (*send_IPI_all)(int vector);
340 void (*send_IPI_self)(int vector);
342 /* wakeup_secondary_cpu */
343 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
345 int trampoline_phys_low;
346 int trampoline_phys_high;
348 void (*wait_for_init_deassert)(atomic_t *deassert);
349 void (*smp_callin_clear_local_apic)(void);
350 void (*inquire_remote_apic)(int apicid);
353 u32 (*read)(u32 reg);
354 void (*write)(u32 reg, u32 v);
355 u64 (*icr_read)(void);
356 void (*icr_write)(u32 low, u32 high);
357 void (*wait_icr_idle)(void);
358 u32 (*safe_wait_icr_idle)(void);
362 * Pointer to the local APIC driver in use on this system (there's
363 * always just one such driver in use - the kernel decides via an
364 * early probing process which one it picks - and then sticks to it):
366 extern struct apic *apic;
369 * APIC functionality to boot other CPUs - only used on SMP:
372 extern atomic_t init_deasserted;
373 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
376 #ifdef CONFIG_X86_LOCAL_APIC
377 static inline u32 apic_read(u32 reg)
379 return apic->read(reg);
382 static inline void apic_write(u32 reg, u32 val)
384 apic->write(reg, val);
387 static inline u64 apic_icr_read(void)
389 return apic->icr_read();
392 static inline void apic_icr_write(u32 low, u32 high)
394 apic->icr_write(low, high);
397 static inline void apic_wait_icr_idle(void)
399 apic->wait_icr_idle();
402 static inline u32 safe_apic_wait_icr_idle(void)
404 return apic->safe_wait_icr_idle();
407 #else /* CONFIG_X86_LOCAL_APIC */
409 static inline u32 apic_read(u32 reg) { return 0; }
410 static inline void apic_write(u32 reg, u32 val) { }
411 static inline u64 apic_icr_read(void) { return 0; }
412 static inline void apic_icr_write(u32 low, u32 high) { }
413 static inline void apic_wait_icr_idle(void) { }
414 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
416 #endif /* CONFIG_X86_LOCAL_APIC */
418 static inline void ack_APIC_irq(void)
421 * ack_APIC_irq() actually gets compiled as a single instruction
425 /* Docs say use 0 for future compatibility */
426 apic_write(APIC_EOI, 0);
429 static inline unsigned default_get_apic_id(unsigned long x)
431 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
433 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
434 return (x >> 24) & 0xFF;
436 return (x >> 24) & 0x0F;
440 * Warm reset vector default position:
442 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
443 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
446 extern struct apic apic_flat;
447 extern struct apic apic_physflat;
448 extern struct apic apic_x2apic_cluster;
449 extern struct apic apic_x2apic_phys;
450 extern int default_acpi_madt_oem_check(char *, char *);
452 extern void apic_send_IPI_self(int vector);
454 extern struct apic apic_x2apic_uv_x;
455 DECLARE_PER_CPU(int, x2apic_extra_bits);
457 extern int default_cpu_present_to_apicid(int mps_cpu);
458 extern int default_check_phys_apicid_present(int phys_apicid);
461 static inline void default_wait_for_init_deassert(atomic_t *deassert)
463 while (!atomic_read(deassert))
468 extern void generic_bigsmp_probe(void);
471 #ifdef CONFIG_X86_LOCAL_APIC
475 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
477 static inline const struct cpumask *default_target_cpus(void)
480 return cpu_online_mask;
482 return cpumask_of(0);
486 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
489 static inline unsigned int read_apic_id(void)
493 reg = apic_read(APIC_ID);
495 return apic->get_apic_id(reg);
498 extern void default_setup_apic_routing(void);
500 extern struct apic apic_noop;
504 extern struct apic apic_default;
507 * Set up the logical destination ID.
509 * Intel recommends to set DFR, LDR and TPR before enabling
510 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
511 * document number 292116). So here it goes...
513 extern void default_init_apic_ldr(void);
515 static inline int default_apic_id_registered(void)
517 return physid_isset(read_apic_id(), phys_cpu_present_map);
520 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
522 return cpuid_apic >> index_msb;
525 extern int default_apicid_to_node(int logical_apicid);
529 static inline unsigned int
530 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
532 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
535 static inline unsigned int
536 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
537 const struct cpumask *andmask)
539 unsigned long mask1 = cpumask_bits(cpumask)[0];
540 unsigned long mask2 = cpumask_bits(andmask)[0];
541 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
543 return (unsigned int)(mask1 & mask2 & mask3);
546 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
548 return physid_isset(apicid, *map);
551 static inline unsigned long default_check_apicid_present(int bit)
553 return physid_isset(bit, phys_cpu_present_map);
556 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
561 /* Mapping from cpu number to logical apicid */
562 static inline int default_cpu_to_logical_apicid(int cpu)
567 static inline int __default_cpu_present_to_apicid(int mps_cpu)
569 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
570 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
576 __default_check_phys_apicid_present(int phys_apicid)
578 return physid_isset(phys_apicid, phys_cpu_present_map);
582 static inline int default_cpu_present_to_apicid(int mps_cpu)
584 return __default_cpu_present_to_apicid(mps_cpu);
588 default_check_phys_apicid_present(int phys_apicid)
590 return __default_check_phys_apicid_present(phys_apicid);
593 extern int default_cpu_present_to_apicid(int mps_cpu);
594 extern int default_check_phys_apicid_present(int phys_apicid);
597 #endif /* CONFIG_X86_LOCAL_APIC */
600 extern u8 cpu_2_logical_apicid[NR_CPUS];
603 #endif /* _ASM_X86_APIC_H */