2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _FPU_INTERNAL_H
11 #define _FPU_INTERNAL_H
13 #include <linux/kernel_stat.h>
14 #include <linux/regset.h>
15 #include <linux/compat.h>
16 #include <linux/slab.h>
18 #include <asm/cpufeature.h>
19 #include <asm/processor.h>
20 #include <asm/sigcontext.h>
22 #include <asm/uaccess.h>
23 #include <asm/xsave.h>
27 # include <asm/sigcontext32.h>
28 # include <asm/user32.h>
30 int ia32_setup_rt_frame(int sig, struct ksignal *ksig,
31 compat_sigset_t *set, struct pt_regs *regs);
32 int ia32_setup_frame(int sig, struct ksignal *ksig,
33 compat_sigset_t *set, struct pt_regs *regs);
35 # define user_i387_ia32_struct user_i387_struct
36 # define user32_fxsr_struct user_fxsr_struct
37 # define ia32_setup_frame __setup_frame
38 # define ia32_setup_rt_frame __setup_rt_frame
41 extern unsigned int mxcsr_feature_mask;
42 extern void fpu_init(void);
43 extern void eager_fpu_init(void);
45 DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
47 extern void convert_from_fxsr(struct user_i387_ia32_struct *env,
48 struct task_struct *tsk);
49 extern void convert_to_fxsr(struct task_struct *tsk,
50 const struct user_i387_ia32_struct *env);
52 extern user_regset_active_fn fpregs_active, xfpregs_active;
53 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
55 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
59 * xstateregs_active == fpregs_active. Please refer to the comment
60 * at the definition of fpregs_active.
62 #define xstateregs_active fpregs_active
64 #ifdef CONFIG_MATH_EMULATION
65 # define HAVE_HWFP (boot_cpu_data.hard_math)
66 extern void finit_soft_fpu(struct i387_soft_struct *soft);
69 static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
72 static inline int is_ia32_compat_frame(void)
74 return config_enabled(CONFIG_IA32_EMULATION) &&
75 test_thread_flag(TIF_IA32);
78 static inline int is_ia32_frame(void)
80 return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame();
83 static inline int is_x32_frame(void)
85 return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32);
88 #define X87_FSW_ES (1 << 7) /* Exception Summary */
90 static __always_inline __pure bool use_eager_fpu(void)
92 return static_cpu_has(X86_FEATURE_EAGER_FPU);
95 static __always_inline __pure bool use_xsaveopt(void)
97 return static_cpu_has(X86_FEATURE_XSAVEOPT);
100 static __always_inline __pure bool use_xsave(void)
102 return static_cpu_has(X86_FEATURE_XSAVE);
105 static __always_inline __pure bool use_fxsr(void)
107 return static_cpu_has(X86_FEATURE_FXSR);
110 static inline void fx_finit(struct i387_fxsave_struct *fx)
112 memset(fx, 0, xstate_size);
114 fx->mxcsr = MXCSR_DEFAULT;
117 extern void __sanitize_i387_state(struct task_struct *);
119 static inline void sanitize_i387_state(struct task_struct *tsk)
123 __sanitize_i387_state(tsk);
126 #define user_insn(insn, output, input...) \
129 asm volatile(ASM_STAC "\n" \
131 "2: " ASM_CLAC "\n" \
132 ".section .fixup,\"ax\"\n" \
133 "3: movl $-1,%[err]\n" \
136 _ASM_EXTABLE(1b, 3b) \
137 : [err] "=r" (err), output \
142 #define check_insn(insn, output, input...) \
145 asm volatile("1:" #insn "\n\t" \
147 ".section .fixup,\"ax\"\n" \
148 "3: movl $-1,%[err]\n" \
151 _ASM_EXTABLE(1b, 3b) \
152 : [err] "=r" (err), output \
157 static inline int fsave_user(struct i387_fsave_struct __user *fx)
159 return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
162 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
164 if (config_enabled(CONFIG_X86_32))
165 return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
166 else if (config_enabled(CONFIG_AS_FXSAVEQ))
167 return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
169 /* See comment in fpu_fxsave() below. */
170 return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
173 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
175 if (config_enabled(CONFIG_X86_32))
176 return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
177 else if (config_enabled(CONFIG_AS_FXSAVEQ))
178 return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
180 /* See comment in fpu_fxsave() below. */
181 return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
185 static inline int fxrstor_user(struct i387_fxsave_struct __user *fx)
187 if (config_enabled(CONFIG_X86_32))
188 return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
189 else if (config_enabled(CONFIG_AS_FXSAVEQ))
190 return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
192 /* See comment in fpu_fxsave() below. */
193 return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
197 static inline int frstor_checking(struct i387_fsave_struct *fx)
199 return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
202 static inline int frstor_user(struct i387_fsave_struct __user *fx)
204 return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
207 static inline void fpu_fxsave(struct fpu *fpu)
209 if (config_enabled(CONFIG_X86_32))
210 asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave));
211 else if (config_enabled(CONFIG_AS_FXSAVEQ))
212 asm volatile("fxsaveq %0" : "=m" (fpu->state->fxsave));
214 /* Using "rex64; fxsave %0" is broken because, if the memory
215 * operand uses any extended registers for addressing, a second
216 * REX prefix will be generated (to the assembler, rex64
217 * followed by semicolon is a separate instruction), and hence
218 * the 64-bitness is lost.
220 * Using "fxsaveq %0" would be the ideal choice, but is only
221 * supported starting with gas 2.16.
223 * Using, as a workaround, the properly prefixed form below
224 * isn't accepted by any binutils version so far released,
225 * complaining that the same type of prefix is used twice if
226 * an extended register is needed for addressing (fix submitted
227 * to mainline 2005-11-21).
229 * asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave));
231 * This, however, we can work around by forcing the compiler to
232 * select an addressing mode that doesn't require extended
235 asm volatile( "rex64/fxsave (%[fx])"
236 : "=m" (fpu->state->fxsave)
237 : [fx] "R" (&fpu->state->fxsave));
242 * These must be called with preempt disabled. Returns
243 * 'true' if the FPU state is still intact.
245 static inline int fpu_save_init(struct fpu *fpu)
251 * xsave header may indicate the init state of the FP.
253 if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
255 } else if (use_fxsr()) {
258 asm volatile("fnsave %[fx]; fwait"
259 : [fx] "=m" (fpu->state->fsave));
264 * If exceptions are pending, we need to clear them so
265 * that we don't randomly get exceptions later.
267 * FIXME! Is this perhaps only true for the old-style
268 * irq13 case? Maybe we could leave the x87 state
271 if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
272 asm volatile("fnclex");
278 static inline int __save_init_fpu(struct task_struct *tsk)
280 return fpu_save_init(&tsk->thread.fpu);
283 static inline int fpu_restore_checking(struct fpu *fpu)
286 return fpu_xrstor_checking(&fpu->state->xsave);
288 return fxrstor_checking(&fpu->state->fxsave);
290 return frstor_checking(&fpu->state->fsave);
293 static inline int restore_fpu_checking(struct task_struct *tsk)
295 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
296 is pending. Clear the x87 state here by setting it to fixed
297 values. "m" is a random variable that should be in L1 */
300 "emms\n\t" /* clear stack tags */
301 "fildl %P[addr]", /* set F?P to defined value */
302 X86_FEATURE_FXSAVE_LEAK,
303 [addr] "m" (tsk->thread.fpu.has_fpu));
305 return fpu_restore_checking(&tsk->thread.fpu);
309 * Software FPU state helpers. Careful: these need to
310 * be preemption protection *and* they need to be
311 * properly paired with the CR0.TS changes!
313 static inline int __thread_has_fpu(struct task_struct *tsk)
315 return tsk->thread.fpu.has_fpu;
318 /* Must be paired with an 'stts' after! */
319 static inline void __thread_clear_has_fpu(struct task_struct *tsk)
321 tsk->thread.fpu.has_fpu = 0;
322 this_cpu_write(fpu_owner_task, NULL);
325 /* Must be paired with a 'clts' before! */
326 static inline void __thread_set_has_fpu(struct task_struct *tsk)
328 tsk->thread.fpu.has_fpu = 1;
329 this_cpu_write(fpu_owner_task, tsk);
333 * Encapsulate the CR0.TS handling together with the
336 * These generally need preemption protection to work,
337 * do try to avoid using these on their own.
339 static inline void __thread_fpu_end(struct task_struct *tsk)
341 __thread_clear_has_fpu(tsk);
342 if (!use_eager_fpu())
346 static inline void __thread_fpu_begin(struct task_struct *tsk)
348 if (!use_eager_fpu())
350 __thread_set_has_fpu(tsk);
353 static inline void __drop_fpu(struct task_struct *tsk)
355 if (__thread_has_fpu(tsk)) {
356 /* Ignore delayed exceptions from user space */
357 asm volatile("1: fwait\n"
359 _ASM_EXTABLE(1b, 2b));
360 __thread_fpu_end(tsk);
364 static inline void drop_fpu(struct task_struct *tsk)
367 * Forget coprocessor state..
370 tsk->fpu_counter = 0;
376 static inline void drop_init_fpu(struct task_struct *tsk)
378 if (!use_eager_fpu())
382 xrstor_state(init_xstate_buf, -1);
384 fxrstor_checking(&init_xstate_buf->i387);
389 * FPU state switching for scheduling.
391 * This is a two-stage process:
393 * - switch_fpu_prepare() saves the old state and
394 * sets the new state of the CR0.TS bit. This is
395 * done within the context of the old process.
397 * - switch_fpu_finish() restores the new state as
400 typedef struct { int preload; } fpu_switch_t;
403 * Must be run with preemption disabled: this clears the fpu_owner_task,
406 * This will disable any lazy FPU state restore of the current FPU state,
407 * but if the current thread owns the FPU, it will still be saved by.
409 static inline void __cpu_disable_lazy_restore(unsigned int cpu)
411 per_cpu(fpu_owner_task, cpu) = NULL;
414 static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
416 return new == this_cpu_read_stable(fpu_owner_task) &&
417 cpu == new->thread.fpu.last_cpu;
420 static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
425 * If the task has used the math, pre-load the FPU on xsave processors
426 * or if the past 5 consecutive context-switches used math.
428 fpu.preload = tsk_used_math(new) && (use_eager_fpu() ||
429 new->fpu_counter > 5);
430 if (__thread_has_fpu(old)) {
431 if (!__save_init_fpu(old))
433 old->thread.fpu.last_cpu = cpu;
434 old->thread.fpu.has_fpu = 0; /* But leave fpu_owner_task! */
436 /* Don't change CR0.TS if we just switch! */
439 __thread_set_has_fpu(new);
440 prefetch(new->thread.fpu.state);
441 } else if (!use_eager_fpu())
444 old->fpu_counter = 0;
445 old->thread.fpu.last_cpu = ~0;
448 if (!use_eager_fpu() && fpu_lazy_restore(new, cpu))
451 prefetch(new->thread.fpu.state);
452 __thread_fpu_begin(new);
459 * By the time this gets called, we've already cleared CR0.TS and
460 * given the process the FPU if we are going to preload the FPU
461 * state - all we need to do is to conditionally restore the register
464 static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
467 if (unlikely(restore_fpu_checking(new)))
473 * Signal frame handlers...
475 extern int save_xstate_sig(void __user *buf, void __user *fx, int size);
476 extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size);
478 static inline int xstate_sigframe_size(void)
480 return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size;
483 static inline int restore_xstate_sig(void __user *buf, int ia32_frame)
485 void __user *buf_fx = buf;
486 int size = xstate_sigframe_size();
488 if (ia32_frame && use_fxsr()) {
489 buf_fx = buf + sizeof(struct i387_fsave_struct);
490 size += sizeof(struct i387_fsave_struct);
493 return __restore_xstate_sig(buf, buf_fx, size);
497 * Need to be preemption-safe.
499 * NOTE! user_fpu_begin() must be used only immediately before restoring
500 * it. This function does not do any save/restore on their own.
502 static inline void user_fpu_begin(void)
506 __thread_fpu_begin(current);
510 static inline void __save_fpu(struct task_struct *tsk)
513 xsave_state(&tsk->thread.fpu.state->xsave, -1);
515 fpu_fxsave(&tsk->thread.fpu);
519 * These disable preemption on their own and are safe
521 static inline void save_init_fpu(struct task_struct *tsk)
523 WARN_ON_ONCE(!__thread_has_fpu(tsk));
525 if (use_eager_fpu()) {
531 __save_init_fpu(tsk);
532 __thread_fpu_end(tsk);
537 * i387 state interaction
539 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
542 return tsk->thread.fpu.state->fxsave.cwd;
544 return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
548 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
551 return tsk->thread.fpu.state->fxsave.swd;
553 return (unsigned short)tsk->thread.fpu.state->fsave.swd;
557 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
560 return tsk->thread.fpu.state->fxsave.mxcsr;
562 return MXCSR_DEFAULT;
566 static bool fpu_allocated(struct fpu *fpu)
568 return fpu->state != NULL;
571 static inline int fpu_alloc(struct fpu *fpu)
573 if (fpu_allocated(fpu))
575 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
578 WARN_ON((unsigned long)fpu->state & 15);
582 static inline void fpu_free(struct fpu *fpu)
585 kmem_cache_free(task_xstate_cachep, fpu->state);
590 static inline void fpu_copy(struct task_struct *dst, struct task_struct *src)
592 if (use_eager_fpu()) {
593 memset(&dst->thread.fpu.state->xsave, 0, xstate_size);
596 struct fpu *dfpu = &dst->thread.fpu;
597 struct fpu *sfpu = &src->thread.fpu;
600 memcpy(dfpu->state, sfpu->state, xstate_size);
604 static inline unsigned long
605 alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx,
608 unsigned long frame_size = xstate_sigframe_size();
610 *buf_fx = sp = round_down(sp - frame_size, 64);
611 if (ia32_frame && use_fxsr()) {
612 frame_size += sizeof(struct i387_fsave_struct);
613 sp -= sizeof(struct i387_fsave_struct);