2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
21 #include <asm/cpufeature.h>
22 #include <asm/processor.h>
23 #include <asm/sigcontext.h>
25 #include <asm/uaccess.h>
26 #include <asm/xsave.h>
28 extern unsigned int sig_xstate_size;
29 extern void fpu_init(void);
30 extern void mxcsr_feature_mask_init(void);
31 extern int init_fpu(struct task_struct *child);
32 extern void __math_state_restore(struct task_struct *);
33 extern void math_state_restore(void);
34 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
36 extern user_regset_active_fn fpregs_active, xfpregs_active;
37 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
39 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
43 * xstateregs_active == fpregs_active. Please refer to the comment
44 * at the definition of fpregs_active.
46 #define xstateregs_active fpregs_active
48 extern struct _fpx_sw_bytes fx_sw_reserved;
49 #ifdef CONFIG_IA32_EMULATION
50 extern unsigned int sig_xstate_ia32_size;
51 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
54 extern int save_i387_xstate_ia32(void __user *buf);
55 extern int restore_i387_xstate_ia32(void __user *buf);
58 #ifdef CONFIG_MATH_EMULATION
59 extern void finit_soft_fpu(struct i387_soft_struct *soft);
61 static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
64 #define X87_FSW_ES (1 << 7) /* Exception Summary */
66 static __always_inline __pure bool use_xsaveopt(void)
68 return static_cpu_has(X86_FEATURE_XSAVEOPT);
71 static __always_inline __pure bool use_xsave(void)
73 return static_cpu_has(X86_FEATURE_XSAVE);
76 static __always_inline __pure bool use_fxsr(void)
78 return static_cpu_has(X86_FEATURE_FXSR);
81 extern void __sanitize_i387_state(struct task_struct *);
83 static inline void sanitize_i387_state(struct task_struct *tsk)
87 __sanitize_i387_state(tsk);
91 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
95 /* See comment in fxsave() below. */
96 #ifdef CONFIG_AS_FXSAVEQ
97 asm volatile("1: fxrstorq %[fx]\n\t"
99 ".section .fixup,\"ax\"\n"
100 "3: movl $-1,%[err]\n"
105 : [fx] "m" (*fx), "0" (0));
107 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
109 ".section .fixup,\"ax\"\n"
110 "3: movl $-1,%[err]\n"
115 : [fx] "R" (fx), "m" (*fx), "0" (0));
120 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
125 * Clear the bytes not touched by the fxsave and reserved
128 err = __clear_user(&fx->sw_reserved,
129 sizeof(struct _fpx_sw_bytes));
133 /* See comment in fxsave() below. */
134 #ifdef CONFIG_AS_FXSAVEQ
135 asm volatile("1: fxsaveq %[fx]\n\t"
137 ".section .fixup,\"ax\"\n"
138 "3: movl $-1,%[err]\n"
142 : [err] "=r" (err), [fx] "=m" (*fx)
145 asm volatile("1: rex64/fxsave (%[fx])\n\t"
147 ".section .fixup,\"ax\"\n"
148 "3: movl $-1,%[err]\n"
152 : [err] "=r" (err), "=m" (*fx)
153 : [fx] "R" (fx), "0" (0));
156 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
158 /* No need to clear here because the caller clears USED_MATH */
162 static inline void fpu_fxsave(struct fpu *fpu)
164 /* Using "rex64; fxsave %0" is broken because, if the memory operand
165 uses any extended registers for addressing, a second REX prefix
166 will be generated (to the assembler, rex64 followed by semicolon
167 is a separate instruction), and hence the 64-bitness is lost. */
169 #ifdef CONFIG_AS_FXSAVEQ
170 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
171 starting with gas 2.16. */
172 __asm__ __volatile__("fxsaveq %0"
173 : "=m" (fpu->state->fxsave));
175 /* Using, as a workaround, the properly prefixed form below isn't
176 accepted by any binutils version so far released, complaining that
177 the same type of prefix is used twice if an extended register is
178 needed for addressing (fix submitted to mainline 2005-11-21).
179 asm volatile("rex64/fxsave %0"
180 : "=m" (fpu->state->fxsave));
181 This, however, we can work around by forcing the compiler to select
182 an addressing mode that doesn't require extended registers. */
183 asm volatile("rex64/fxsave (%[fx])"
184 : "=m" (fpu->state->fxsave)
185 : [fx] "R" (&fpu->state->fxsave));
189 #else /* CONFIG_X86_32 */
191 /* perform fxrstor iff the processor has extended states, otherwise frstor */
192 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
195 * The "nop" is needed to make the instructions the same
207 static inline void fpu_fxsave(struct fpu *fpu)
209 asm volatile("fxsave %[fx]"
210 : [fx] "=m" (fpu->state->fxsave));
213 #endif /* CONFIG_X86_64 */
216 * These must be called with preempt disabled. Returns
217 * 'true' if the FPU state is still intact.
219 static inline int fpu_save_init(struct fpu *fpu)
225 * xsave header may indicate the init state of the FP.
227 if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
229 } else if (use_fxsr()) {
232 asm volatile("fnsave %[fx]; fwait"
233 : [fx] "=m" (fpu->state->fsave));
238 * If exceptions are pending, we need to clear them so
239 * that we don't randomly get exceptions later.
241 * FIXME! Is this perhaps only true for the old-style
242 * irq13 case? Maybe we could leave the x87 state
245 if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
246 asm volatile("fnclex");
252 static inline int __save_init_fpu(struct task_struct *tsk)
254 return fpu_save_init(&tsk->thread.fpu);
257 static inline int fpu_fxrstor_checking(struct fpu *fpu)
259 return fxrstor_checking(&fpu->state->fxsave);
262 static inline int fpu_restore_checking(struct fpu *fpu)
265 return fpu_xrstor_checking(fpu);
267 return fpu_fxrstor_checking(fpu);
270 static inline int restore_fpu_checking(struct task_struct *tsk)
272 return fpu_restore_checking(&tsk->thread.fpu);
276 * Software FPU state helpers. Careful: these need to
277 * be preemption protection *and* they need to be
278 * properly paired with the CR0.TS changes!
280 static inline int __thread_has_fpu(struct task_struct *tsk)
282 return tsk->thread.has_fpu;
285 /* Must be paired with an 'stts' after! */
286 static inline void __thread_clear_has_fpu(struct task_struct *tsk)
288 tsk->thread.has_fpu = 0;
291 /* Must be paired with a 'clts' before! */
292 static inline void __thread_set_has_fpu(struct task_struct *tsk)
294 tsk->thread.has_fpu = 1;
298 * Encapsulate the CR0.TS handling together with the
301 * These generally need preemption protection to work,
302 * do try to avoid using these on their own.
304 static inline void __thread_fpu_end(struct task_struct *tsk)
306 __thread_clear_has_fpu(tsk);
310 static inline void __thread_fpu_begin(struct task_struct *tsk)
313 __thread_set_has_fpu(tsk);
317 * FPU state switching for scheduling.
319 * This is a two-stage process:
321 * - switch_fpu_prepare() saves the old state and
322 * sets the new state of the CR0.TS bit. This is
323 * done within the context of the old process.
325 * - switch_fpu_finish() restores the new state as
328 typedef struct { int preload; } fpu_switch_t;
331 * FIXME! We could do a totally lazy restore, but we need to
332 * add a per-cpu "this was the task that last touched the FPU
333 * on this CPU" variable, and the task needs to have a "I last
334 * touched the FPU on this CPU" and check them.
336 * We don't do that yet, so "fpu_lazy_restore()" always returns
337 * false, but some day..
339 #define fpu_lazy_restore(tsk) (0)
340 #define fpu_lazy_state_intact(tsk) do { } while (0)
342 static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new)
346 fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
347 if (__thread_has_fpu(old)) {
348 if (__save_init_fpu(old))
349 fpu_lazy_state_intact(old);
350 __thread_clear_has_fpu(old);
352 /* Don't change CR0.TS if we just switch! */
355 __thread_set_has_fpu(new);
356 prefetch(new->thread.fpu.state);
360 old->fpu_counter = 0;
363 if (fpu_lazy_restore(new))
366 prefetch(new->thread.fpu.state);
367 __thread_fpu_begin(new);
374 * By the time this gets called, we've already cleared CR0.TS and
375 * given the process the FPU if we are going to preload the FPU
376 * state - all we need to do is to conditionally restore the register
379 static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
382 __math_state_restore(new);
386 * Signal frame handlers...
388 extern int save_i387_xstate(void __user *buf);
389 extern int restore_i387_xstate(void __user *buf);
391 static inline void __clear_fpu(struct task_struct *tsk)
393 if (__thread_has_fpu(tsk)) {
394 /* Ignore delayed exceptions from user space */
395 asm volatile("1: fwait\n"
397 _ASM_EXTABLE(1b, 2b));
398 __thread_fpu_end(tsk);
403 * Were we in an interrupt that interrupted kernel mode?
405 * We can do a kernel_fpu_begin/end() pair *ONLY* if that
406 * pair does nothing at all: the thread must not have fpu (so
407 * that we don't try to save the FPU state), and TS must
408 * be set (so that the clts/stts pair does nothing that is
409 * visible in the interrupted kernel thread).
411 static inline bool interrupted_kernel_fpu_idle(void)
413 return !__thread_has_fpu(current) &&
414 (read_cr0() & X86_CR0_TS);
418 * Were we in user mode (or vm86 mode) when we were
421 * Doing kernel_fpu_begin/end() is ok if we are running
422 * in an interrupt context from user mode - we'll just
423 * save the FPU state as required.
425 static inline bool interrupted_user_mode(void)
427 struct pt_regs *regs = get_irq_regs();
428 return regs && user_mode_vm(regs);
432 * Can we use the FPU in kernel mode with the
433 * whole "kernel_fpu_begin/end()" sequence?
435 * It's always ok in process context (ie "not interrupt")
436 * but it is sometimes ok even from an irq.
438 static inline bool irq_fpu_usable(void)
440 return !in_interrupt() ||
441 interrupted_user_mode() ||
442 interrupted_kernel_fpu_idle();
445 static inline void kernel_fpu_begin(void)
447 struct task_struct *me = current;
449 WARN_ON_ONCE(!irq_fpu_usable());
451 if (__thread_has_fpu(me)) {
453 __thread_clear_has_fpu(me);
454 /* We do 'stts()' in kernel_fpu_end() */
459 static inline void kernel_fpu_end(void)
466 * Some instructions like VIA's padlock instructions generate a spurious
467 * DNA fault but don't modify SSE registers. And these instructions
468 * get used from interrupt context as well. To prevent these kernel instructions
469 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
470 * should use them only in the context of irq_ts_save/restore()
472 static inline int irq_ts_save(void)
475 * If in process context and not atomic, we can take a spurious DNA fault.
476 * Otherwise, doing clts() in process context requires disabling preemption
477 * or some heavy lifting like kernel_fpu_begin()
482 if (read_cr0() & X86_CR0_TS) {
490 static inline void irq_ts_restore(int TS_state)
497 * The question "does this thread have fpu access?"
498 * is slightly racy, since preemption could come in
499 * and revoke it immediately after the test.
501 * However, even in that very unlikely scenario,
502 * we can just assume we have FPU access - typically
503 * to save the FP state - we'll just take a #NM
504 * fault and get the FPU access back.
506 * The actual user_fpu_begin/end() functions
507 * need to be preemption-safe, though.
509 * NOTE! user_fpu_end() must be used only after you
510 * have saved the FP state, and user_fpu_begin() must
511 * be used only immediately before restoring it.
512 * These functions do not do any save/restore on
515 static inline int user_has_fpu(void)
517 return __thread_has_fpu(current);
520 static inline void user_fpu_end(void)
523 __thread_fpu_end(current);
527 static inline void user_fpu_begin(void)
531 __thread_fpu_begin(current);
536 * These disable preemption on their own and are safe
538 static inline void save_init_fpu(struct task_struct *tsk)
540 WARN_ON_ONCE(!__thread_has_fpu(tsk));
542 __save_init_fpu(tsk);
543 __thread_fpu_end(tsk);
547 static inline void unlazy_fpu(struct task_struct *tsk)
550 if (__thread_has_fpu(tsk)) {
551 __save_init_fpu(tsk);
552 __thread_fpu_end(tsk);
554 tsk->fpu_counter = 0;
558 static inline void clear_fpu(struct task_struct *tsk)
566 * i387 state interaction
568 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
571 return tsk->thread.fpu.state->fxsave.cwd;
573 return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
577 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
580 return tsk->thread.fpu.state->fxsave.swd;
582 return (unsigned short)tsk->thread.fpu.state->fsave.swd;
586 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
589 return tsk->thread.fpu.state->fxsave.mxcsr;
591 return MXCSR_DEFAULT;
595 static bool fpu_allocated(struct fpu *fpu)
597 return fpu->state != NULL;
600 static inline int fpu_alloc(struct fpu *fpu)
602 if (fpu_allocated(fpu))
604 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
607 WARN_ON((unsigned long)fpu->state & 15);
611 static inline void fpu_free(struct fpu *fpu)
614 kmem_cache_free(task_xstate_cachep, fpu->state);
619 static inline void fpu_copy(struct fpu *dst, struct fpu *src)
621 memcpy(dst->state, src->state, xstate_size);
624 extern void fpu_finit(struct fpu *fpu);
626 #endif /* __ASSEMBLY__ */
628 #endif /* _ASM_X86_I387_H */