2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
20 #include <asm/processor.h>
21 #include <asm/sigcontext.h>
23 #include <asm/uaccess.h>
24 #include <asm/xsave.h>
26 extern unsigned int sig_xstate_size;
27 extern void fpu_init(void);
28 extern void mxcsr_feature_mask_init(void);
29 extern int init_fpu(struct task_struct *child);
30 extern asmlinkage void math_state_restore(void);
31 extern void __math_state_restore(void);
32 extern void init_thread_xstate(void);
33 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
35 extern user_regset_active_fn fpregs_active, xfpregs_active;
36 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
37 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
39 extern struct _fpx_sw_bytes fx_sw_reserved;
40 #ifdef CONFIG_IA32_EMULATION
41 extern unsigned int sig_xstate_ia32_size;
42 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
45 extern int save_i387_xstate_ia32(void __user *buf);
46 extern int restore_i387_xstate_ia32(void __user *buf);
49 #define X87_FSW_ES (1 << 7) /* Exception Summary */
53 /* Ignore delayed exceptions from user space */
54 static inline void tolerant_fwait(void)
56 asm volatile("1: fwait\n"
58 _ASM_EXTABLE(1b, 2b));
61 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
65 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
67 ".section .fixup,\"ax\"\n"
68 "3: movl $-1,%[err]\n"
73 #if 0 /* See comment in fxsave() below. */
74 : [fx] "r" (fx), "m" (*fx), "0" (0));
76 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
81 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
82 is pending. Clear the x87 state here by setting it to fixed
83 values. The kernel data segment can be sometimes 0 and sometimes
84 new user value. Both should be ok.
85 Use the PDA as safe address because it should be already in L1. */
86 static inline void clear_fpu_state(struct task_struct *tsk)
88 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
89 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
92 * xsave header may indicate the init state of the FP.
94 if ((task_thread_info(tsk)->status & TS_XSAVE) &&
95 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
98 if (unlikely(fx->swd & X87_FSW_ES))
99 asm volatile("fnclex");
100 alternative_input(ASM_NOP8 ASM_NOP2,
101 " emms\n" /* clear stack tags */
102 " fildl %%gs:0", /* load to clear state */
103 X86_FEATURE_FXSAVE_LEAK);
106 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
110 asm volatile("1: rex64/fxsave (%[fx])\n\t"
112 ".section .fixup,\"ax\"\n"
113 "3: movl $-1,%[err]\n"
117 : [err] "=r" (err), "=m" (*fx)
118 #if 0 /* See comment in fxsave() below. */
119 : [fx] "r" (fx), "0" (0));
121 : [fx] "cdaSDb" (fx), "0" (0));
124 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
126 /* No need to clear here because the caller clears USED_MATH */
130 static inline void fxsave(struct task_struct *tsk)
132 /* Using "rex64; fxsave %0" is broken because, if the memory operand
133 uses any extended registers for addressing, a second REX prefix
134 will be generated (to the assembler, rex64 followed by semicolon
135 is a separate instruction), and hence the 64-bitness is lost. */
137 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
138 starting with gas 2.16. */
139 __asm__ __volatile__("fxsaveq %0"
140 : "=m" (tsk->thread.xstate->fxsave));
142 /* Using, as a workaround, the properly prefixed form below isn't
143 accepted by any binutils version so far released, complaining that
144 the same type of prefix is used twice if an extended register is
145 needed for addressing (fix submitted to mainline 2005-11-21). */
146 __asm__ __volatile__("rex64/fxsave %0"
147 : "=m" (tsk->thread.xstate->fxsave));
149 /* This, however, we can work around by forcing the compiler to select
150 an addressing mode that doesn't require extended registers. */
151 __asm__ __volatile__("rex64/fxsave (%1)"
152 : "=m" (tsk->thread.xstate->fxsave)
153 : "cdaSDb" (&tsk->thread.xstate->fxsave));
157 static inline void __save_init_fpu(struct task_struct *tsk)
159 if (task_thread_info(tsk)->status & TS_XSAVE)
164 clear_fpu_state(tsk);
165 task_thread_info(tsk)->status &= ~TS_USEDFPU;
168 #else /* CONFIG_X86_32 */
170 #ifdef CONFIG_MATH_EMULATION
171 extern void finit_task(struct task_struct *tsk);
173 static inline void finit_task(struct task_struct *tsk)
178 static inline void tolerant_fwait(void)
180 asm volatile("fnclex ; fwait");
183 /* perform fxrstor iff the processor has extended states, otherwise frstor */
184 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
187 * The "nop" is needed to make the instructions the same
199 /* We need a safe address that is cheap to find and that is already
200 in L1 during context switch. The best choices are unfortunately
201 different for UP and SMP */
203 #define safe_address (__per_cpu_offset[0])
205 #define safe_address (kstat_cpu(0).cpustat.user)
209 * These must be called with preempt disabled
211 static inline void __save_init_fpu(struct task_struct *tsk)
213 if (task_thread_info(tsk)->status & TS_XSAVE) {
214 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
215 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
220 * xsave header may indicate the init state of the FP.
222 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
225 if (unlikely(fx->swd & X87_FSW_ES))
226 asm volatile("fnclex");
229 * we can do a simple return here or be paranoid :)
234 /* Use more nops than strictly needed in case the compiler
237 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
239 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
241 [fx] "m" (tsk->thread.xstate->fxsave),
242 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
244 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
245 is pending. Clear the x87 state here by setting it to fixed
246 values. safe_address is a random variable that should be in L1 */
248 GENERIC_NOP8 GENERIC_NOP2,
249 "emms\n\t" /* clear stack tags */
250 "fildl %[addr]", /* set F?P to defined value */
251 X86_FEATURE_FXSAVE_LEAK,
252 [addr] "m" (safe_address));
254 task_thread_info(tsk)->status &= ~TS_USEDFPU;
257 #endif /* CONFIG_X86_64 */
259 static inline int restore_fpu_checking(struct task_struct *tsk)
261 if (task_thread_info(tsk)->status & TS_XSAVE)
262 return xrstor_checking(&tsk->thread.xstate->xsave);
264 return fxrstor_checking(&tsk->thread.xstate->fxsave);
268 * Signal frame handlers...
270 extern int save_i387_xstate(void __user *buf);
271 extern int restore_i387_xstate(void __user *buf);
273 static inline void __unlazy_fpu(struct task_struct *tsk)
275 if (task_thread_info(tsk)->status & TS_USEDFPU) {
276 __save_init_fpu(tsk);
279 tsk->fpu_counter = 0;
282 static inline void __clear_fpu(struct task_struct *tsk)
284 if (task_thread_info(tsk)->status & TS_USEDFPU) {
286 task_thread_info(tsk)->status &= ~TS_USEDFPU;
291 static inline void kernel_fpu_begin(void)
293 struct thread_info *me = current_thread_info();
295 if (me->status & TS_USEDFPU)
296 __save_init_fpu(me->task);
301 static inline void kernel_fpu_end(void)
307 static inline bool irq_fpu_usable(void)
309 struct pt_regs *regs;
311 return !in_interrupt() || !(regs = get_irq_regs()) || \
312 user_mode(regs) || (read_cr0() & X86_CR0_TS);
316 * Some instructions like VIA's padlock instructions generate a spurious
317 * DNA fault but don't modify SSE registers. And these instructions
318 * get used from interrupt context as well. To prevent these kernel instructions
319 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
320 * should use them only in the context of irq_ts_save/restore()
322 static inline int irq_ts_save(void)
325 * If in process context and not atomic, we can take a spurious DNA fault.
326 * Otherwise, doing clts() in process context requires disabling preemption
327 * or some heavy lifting like kernel_fpu_begin()
332 if (read_cr0() & X86_CR0_TS) {
340 static inline void irq_ts_restore(int TS_state)
348 static inline void save_init_fpu(struct task_struct *tsk)
350 __save_init_fpu(tsk);
354 #define unlazy_fpu __unlazy_fpu
355 #define clear_fpu __clear_fpu
357 #else /* CONFIG_X86_32 */
360 * These disable preemption on their own and are safe
362 static inline void save_init_fpu(struct task_struct *tsk)
365 __save_init_fpu(tsk);
370 static inline void unlazy_fpu(struct task_struct *tsk)
377 static inline void clear_fpu(struct task_struct *tsk)
384 #endif /* CONFIG_X86_64 */
387 * i387 state interaction
389 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
392 return tsk->thread.xstate->fxsave.cwd;
394 return (unsigned short)tsk->thread.xstate->fsave.cwd;
398 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
401 return tsk->thread.xstate->fxsave.swd;
403 return (unsigned short)tsk->thread.xstate->fsave.swd;
407 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
410 return tsk->thread.xstate->fxsave.mxcsr;
412 return MXCSR_DEFAULT;
416 #endif /* __ASSEMBLY__ */
418 #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
419 #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
421 #endif /* _ASM_X86_I387_H */