2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
13 #include <linux/sched.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/regset.h>
16 #include <linux/hardirq.h>
18 #include <asm/processor.h>
19 #include <asm/sigcontext.h>
21 #include <asm/uaccess.h>
22 #include <asm/xsave.h>
24 extern unsigned int sig_xstate_size;
25 extern void fpu_init(void);
26 extern void mxcsr_feature_mask_init(void);
27 extern int init_fpu(struct task_struct *child);
28 extern asmlinkage void math_state_restore(void);
29 extern void init_thread_xstate(void);
30 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
32 extern user_regset_active_fn fpregs_active, xfpregs_active;
33 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
34 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
36 extern struct _fpx_sw_bytes fx_sw_reserved;
37 #ifdef CONFIG_IA32_EMULATION
38 extern unsigned int sig_xstate_ia32_size;
39 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
42 extern int save_i387_xstate_ia32(void __user *buf);
43 extern int restore_i387_xstate_ia32(void __user *buf);
46 #define X87_FSW_ES (1 << 7) /* Exception Summary */
50 /* Ignore delayed exceptions from user space */
51 static inline void tolerant_fwait(void)
53 asm volatile("1: fwait\n"
55 _ASM_EXTABLE(1b, 2b));
58 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
62 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
64 ".section .fixup,\"ax\"\n"
65 "3: movl $-1,%[err]\n"
70 #if 0 /* See comment in fxsave() below. */
71 : [fx] "r" (fx), "m" (*fx), "0" (0));
73 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
78 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
79 is pending. Clear the x87 state here by setting it to fixed
80 values. The kernel data segment can be sometimes 0 and sometimes
81 new user value. Both should be ok.
82 Use the PDA as safe address because it should be already in L1. */
83 static inline void clear_fpu_state(struct task_struct *tsk)
85 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
86 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
89 * xsave header may indicate the init state of the FP.
91 if ((task_thread_info(tsk)->status & TS_XSAVE) &&
92 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
95 if (unlikely(fx->swd & X87_FSW_ES))
96 asm volatile("fnclex");
97 alternative_input(ASM_NOP8 ASM_NOP2,
98 " emms\n" /* clear stack tags */
99 " fildl %%gs:0", /* load to clear state */
100 X86_FEATURE_FXSAVE_LEAK);
103 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
107 asm volatile("1: rex64/fxsave (%[fx])\n\t"
109 ".section .fixup,\"ax\"\n"
110 "3: movl $-1,%[err]\n"
114 : [err] "=r" (err), "=m" (*fx)
115 #if 0 /* See comment in fxsave() below. */
116 : [fx] "r" (fx), "0" (0));
118 : [fx] "cdaSDb" (fx), "0" (0));
121 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
123 /* No need to clear here because the caller clears USED_MATH */
127 static inline void fxsave(struct task_struct *tsk)
129 /* Using "rex64; fxsave %0" is broken because, if the memory operand
130 uses any extended registers for addressing, a second REX prefix
131 will be generated (to the assembler, rex64 followed by semicolon
132 is a separate instruction), and hence the 64-bitness is lost. */
134 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
135 starting with gas 2.16. */
136 __asm__ __volatile__("fxsaveq %0"
137 : "=m" (tsk->thread.xstate->fxsave));
139 /* Using, as a workaround, the properly prefixed form below isn't
140 accepted by any binutils version so far released, complaining that
141 the same type of prefix is used twice if an extended register is
142 needed for addressing (fix submitted to mainline 2005-11-21). */
143 __asm__ __volatile__("rex64/fxsave %0"
144 : "=m" (tsk->thread.xstate->fxsave));
146 /* This, however, we can work around by forcing the compiler to select
147 an addressing mode that doesn't require extended registers. */
148 __asm__ __volatile__("rex64/fxsave (%1)"
149 : "=m" (tsk->thread.xstate->fxsave)
150 : "cdaSDb" (&tsk->thread.xstate->fxsave));
154 static inline void __save_init_fpu(struct task_struct *tsk)
156 if (task_thread_info(tsk)->status & TS_XSAVE)
161 clear_fpu_state(tsk);
162 task_thread_info(tsk)->status &= ~TS_USEDFPU;
165 #else /* CONFIG_X86_32 */
167 #ifdef CONFIG_MATH_EMULATION
168 extern void finit_task(struct task_struct *tsk);
170 static inline void finit_task(struct task_struct *tsk)
175 static inline void tolerant_fwait(void)
177 asm volatile("fnclex ; fwait");
180 /* perform fxrstor iff the processor has extended states, otherwise frstor */
181 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
184 * The "nop" is needed to make the instructions the same
196 /* We need a safe address that is cheap to find and that is already
197 in L1 during context switch. The best choices are unfortunately
198 different for UP and SMP */
200 #define safe_address (__per_cpu_offset[0])
202 #define safe_address (kstat_cpu(0).cpustat.user)
206 * These must be called with preempt disabled
208 static inline void __save_init_fpu(struct task_struct *tsk)
210 if (task_thread_info(tsk)->status & TS_XSAVE) {
211 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
212 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
217 * xsave header may indicate the init state of the FP.
219 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
222 if (unlikely(fx->swd & X87_FSW_ES))
223 asm volatile("fnclex");
226 * we can do a simple return here or be paranoid :)
231 /* Use more nops than strictly needed in case the compiler
234 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
236 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
238 [fx] "m" (tsk->thread.xstate->fxsave),
239 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
241 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
242 is pending. Clear the x87 state here by setting it to fixed
243 values. safe_address is a random variable that should be in L1 */
245 GENERIC_NOP8 GENERIC_NOP2,
246 "emms\n\t" /* clear stack tags */
247 "fildl %[addr]", /* set F?P to defined value */
248 X86_FEATURE_FXSAVE_LEAK,
249 [addr] "m" (safe_address));
251 task_thread_info(tsk)->status &= ~TS_USEDFPU;
254 #endif /* CONFIG_X86_64 */
256 static inline int restore_fpu_checking(struct task_struct *tsk)
258 if (task_thread_info(tsk)->status & TS_XSAVE)
259 return xrstor_checking(&tsk->thread.xstate->xsave);
261 return fxrstor_checking(&tsk->thread.xstate->fxsave);
265 * Signal frame handlers...
267 extern int save_i387_xstate(void __user *buf);
268 extern int restore_i387_xstate(void __user *buf);
270 static inline void __unlazy_fpu(struct task_struct *tsk)
272 if (task_thread_info(tsk)->status & TS_USEDFPU) {
273 __save_init_fpu(tsk);
276 tsk->fpu_counter = 0;
279 static inline void __clear_fpu(struct task_struct *tsk)
281 if (task_thread_info(tsk)->status & TS_USEDFPU) {
283 task_thread_info(tsk)->status &= ~TS_USEDFPU;
288 static inline void kernel_fpu_begin(void)
290 struct thread_info *me = current_thread_info();
292 if (me->status & TS_USEDFPU)
293 __save_init_fpu(me->task);
298 static inline void kernel_fpu_end(void)
304 static inline bool irq_fpu_usable(void)
306 struct pt_regs *regs;
308 return !in_interrupt() || !(regs = get_irq_regs()) || \
309 user_mode(regs) || (read_cr0() & X86_CR0_TS);
313 * Some instructions like VIA's padlock instructions generate a spurious
314 * DNA fault but don't modify SSE registers. And these instructions
315 * get used from interrupt context as well. To prevent these kernel instructions
316 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
317 * should use them only in the context of irq_ts_save/restore()
319 static inline int irq_ts_save(void)
322 * If in process context and not atomic, we can take a spurious DNA fault.
323 * Otherwise, doing clts() in process context requires disabling preemption
324 * or some heavy lifting like kernel_fpu_begin()
329 if (read_cr0() & X86_CR0_TS) {
337 static inline void irq_ts_restore(int TS_state)
345 static inline void save_init_fpu(struct task_struct *tsk)
347 __save_init_fpu(tsk);
351 #define unlazy_fpu __unlazy_fpu
352 #define clear_fpu __clear_fpu
354 #else /* CONFIG_X86_32 */
357 * These disable preemption on their own and are safe
359 static inline void save_init_fpu(struct task_struct *tsk)
362 __save_init_fpu(tsk);
367 static inline void unlazy_fpu(struct task_struct *tsk)
374 static inline void clear_fpu(struct task_struct *tsk)
381 #endif /* CONFIG_X86_64 */
384 * i387 state interaction
386 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
389 return tsk->thread.xstate->fxsave.cwd;
391 return (unsigned short)tsk->thread.xstate->fsave.cwd;
395 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
398 return tsk->thread.xstate->fxsave.swd;
400 return (unsigned short)tsk->thread.xstate->fsave.swd;
404 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
407 return tsk->thread.xstate->fxsave.mxcsr;
409 return MXCSR_DEFAULT;
413 #endif /* _ASM_X86_I387_H */