2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
21 #include <asm/cpufeature.h>
22 #include <asm/processor.h>
23 #include <asm/sigcontext.h>
25 #include <asm/uaccess.h>
26 #include <asm/xsave.h>
28 extern unsigned int sig_xstate_size;
29 extern void fpu_init(void);
30 extern void mxcsr_feature_mask_init(void);
31 extern int init_fpu(struct task_struct *child);
32 extern asmlinkage void math_state_restore(void);
33 extern void __math_state_restore(void);
34 extern void init_thread_xstate(void);
35 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
37 extern user_regset_active_fn fpregs_active, xfpregs_active;
38 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
40 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
44 * xstateregs_active == fpregs_active. Please refer to the comment
45 * at the definition of fpregs_active.
47 #define xstateregs_active fpregs_active
49 extern struct _fpx_sw_bytes fx_sw_reserved;
50 #ifdef CONFIG_IA32_EMULATION
51 extern unsigned int sig_xstate_ia32_size;
52 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
55 extern int save_i387_xstate_ia32(void __user *buf);
56 extern int restore_i387_xstate_ia32(void __user *buf);
59 #define X87_FSW_ES (1 << 7) /* Exception Summary */
61 static __always_inline __pure bool use_xsave(void)
63 return static_cpu_has(X86_FEATURE_XSAVE);
68 /* Ignore delayed exceptions from user space */
69 static inline void tolerant_fwait(void)
71 asm volatile("1: fwait\n"
73 _ASM_EXTABLE(1b, 2b));
76 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
80 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
82 ".section .fixup,\"ax\"\n"
83 "3: movl $-1,%[err]\n"
88 #if 0 /* See comment in fxsave() below. */
89 : [fx] "r" (fx), "m" (*fx), "0" (0));
91 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
96 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
97 is pending. Clear the x87 state here by setting it to fixed
98 values. The kernel data segment can be sometimes 0 and sometimes
99 new user value. Both should be ok.
100 Use the PDA as safe address because it should be already in L1. */
101 static inline void fpu_clear(struct fpu *fpu)
103 struct xsave_struct *xstate = &fpu->state->xsave;
104 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
107 * xsave header may indicate the init state of the FP.
110 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
113 if (unlikely(fx->swd & X87_FSW_ES))
114 asm volatile("fnclex");
115 alternative_input(ASM_NOP8 ASM_NOP2,
116 " emms\n" /* clear stack tags */
117 " fildl %%gs:0", /* load to clear state */
118 X86_FEATURE_FXSAVE_LEAK);
121 static inline void clear_fpu_state(struct task_struct *tsk)
123 fpu_clear(&tsk->thread.fpu);
126 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
130 asm volatile("1: rex64/fxsave (%[fx])\n\t"
132 ".section .fixup,\"ax\"\n"
133 "3: movl $-1,%[err]\n"
137 : [err] "=r" (err), "=m" (*fx)
138 #if 0 /* See comment in fxsave() below. */
139 : [fx] "r" (fx), "0" (0));
141 : [fx] "cdaSDb" (fx), "0" (0));
144 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
146 /* No need to clear here because the caller clears USED_MATH */
150 static inline void fpu_fxsave(struct fpu *fpu)
152 /* Using "rex64; fxsave %0" is broken because, if the memory operand
153 uses any extended registers for addressing, a second REX prefix
154 will be generated (to the assembler, rex64 followed by semicolon
155 is a separate instruction), and hence the 64-bitness is lost. */
157 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
158 starting with gas 2.16. */
159 __asm__ __volatile__("fxsaveq %0"
160 : "=m" (fpu->state->fxsave));
162 /* Using, as a workaround, the properly prefixed form below isn't
163 accepted by any binutils version so far released, complaining that
164 the same type of prefix is used twice if an extended register is
165 needed for addressing (fix submitted to mainline 2005-11-21). */
166 __asm__ __volatile__("rex64/fxsave %0"
167 : "=m" (fpu->state->fxsave));
169 /* This, however, we can work around by forcing the compiler to select
170 an addressing mode that doesn't require extended registers. */
171 __asm__ __volatile__("rex64/fxsave (%1)"
172 : "=m" (fpu->state->fxsave)
173 : "cdaSDb" (&fpu->state->fxsave));
177 static inline void fpu_save_init(struct fpu *fpu)
187 static inline void __save_init_fpu(struct task_struct *tsk)
189 fpu_save_init(&tsk->thread.fpu);
190 task_thread_info(tsk)->status &= ~TS_USEDFPU;
193 #else /* CONFIG_X86_32 */
195 #ifdef CONFIG_MATH_EMULATION
196 extern void finit_soft_fpu(struct i387_soft_struct *soft);
198 static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
201 static inline void tolerant_fwait(void)
203 asm volatile("fnclex ; fwait");
206 /* perform fxrstor iff the processor has extended states, otherwise frstor */
207 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
210 * The "nop" is needed to make the instructions the same
222 /* We need a safe address that is cheap to find and that is already
223 in L1 during context switch. The best choices are unfortunately
224 different for UP and SMP */
226 #define safe_address (__per_cpu_offset[0])
228 #define safe_address (kstat_cpu(0).cpustat.user)
232 * These must be called with preempt disabled
234 static inline void fpu_save_init(struct fpu *fpu)
237 struct xsave_struct *xstate = &fpu->state->xsave;
238 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
243 * xsave header may indicate the init state of the FP.
245 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
248 if (unlikely(fx->swd & X87_FSW_ES))
249 asm volatile("fnclex");
252 * we can do a simple return here or be paranoid :)
257 /* Use more nops than strictly needed in case the compiler
260 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
262 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
264 [fx] "m" (fpu->state->fxsave),
265 [fsw] "m" (fpu->state->fxsave.swd) : "memory");
267 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
268 is pending. Clear the x87 state here by setting it to fixed
269 values. safe_address is a random variable that should be in L1 */
271 GENERIC_NOP8 GENERIC_NOP2,
272 "emms\n\t" /* clear stack tags */
273 "fildl %[addr]", /* set F?P to defined value */
274 X86_FEATURE_FXSAVE_LEAK,
275 [addr] "m" (safe_address));
280 static inline void __save_init_fpu(struct task_struct *tsk)
282 fpu_save_init(&tsk->thread.fpu);
283 task_thread_info(tsk)->status &= ~TS_USEDFPU;
287 #endif /* CONFIG_X86_64 */
289 static inline int fpu_fxrstor_checking(struct fpu *fpu)
291 return fxrstor_checking(&fpu->state->fxsave);
294 static inline int fpu_restore_checking(struct fpu *fpu)
297 return fpu_xrstor_checking(fpu);
299 return fpu_fxrstor_checking(fpu);
302 static inline int restore_fpu_checking(struct task_struct *tsk)
304 return fpu_restore_checking(&tsk->thread.fpu);
308 * Signal frame handlers...
310 extern int save_i387_xstate(void __user *buf);
311 extern int restore_i387_xstate(void __user *buf);
313 static inline void __unlazy_fpu(struct task_struct *tsk)
315 if (task_thread_info(tsk)->status & TS_USEDFPU) {
316 __save_init_fpu(tsk);
319 tsk->fpu_counter = 0;
322 static inline void __clear_fpu(struct task_struct *tsk)
324 if (task_thread_info(tsk)->status & TS_USEDFPU) {
326 task_thread_info(tsk)->status &= ~TS_USEDFPU;
331 static inline void kernel_fpu_begin(void)
333 struct thread_info *me = current_thread_info();
335 if (me->status & TS_USEDFPU)
336 __save_init_fpu(me->task);
341 static inline void kernel_fpu_end(void)
347 static inline bool irq_fpu_usable(void)
349 struct pt_regs *regs;
351 return !in_interrupt() || !(regs = get_irq_regs()) || \
352 user_mode(regs) || (read_cr0() & X86_CR0_TS);
356 * Some instructions like VIA's padlock instructions generate a spurious
357 * DNA fault but don't modify SSE registers. And these instructions
358 * get used from interrupt context as well. To prevent these kernel instructions
359 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
360 * should use them only in the context of irq_ts_save/restore()
362 static inline int irq_ts_save(void)
365 * If in process context and not atomic, we can take a spurious DNA fault.
366 * Otherwise, doing clts() in process context requires disabling preemption
367 * or some heavy lifting like kernel_fpu_begin()
372 if (read_cr0() & X86_CR0_TS) {
380 static inline void irq_ts_restore(int TS_state)
388 static inline void save_init_fpu(struct task_struct *tsk)
390 __save_init_fpu(tsk);
394 #define unlazy_fpu __unlazy_fpu
395 #define clear_fpu __clear_fpu
397 #else /* CONFIG_X86_32 */
400 * These disable preemption on their own and are safe
402 static inline void save_init_fpu(struct task_struct *tsk)
405 __save_init_fpu(tsk);
410 static inline void unlazy_fpu(struct task_struct *tsk)
417 static inline void clear_fpu(struct task_struct *tsk)
424 #endif /* CONFIG_X86_64 */
427 * i387 state interaction
429 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
432 return tsk->thread.fpu.state->fxsave.cwd;
434 return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
438 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
441 return tsk->thread.fpu.state->fxsave.swd;
443 return (unsigned short)tsk->thread.fpu.state->fsave.swd;
447 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
450 return tsk->thread.fpu.state->fxsave.mxcsr;
452 return MXCSR_DEFAULT;
456 static bool fpu_allocated(struct fpu *fpu)
458 return fpu->state != NULL;
461 static inline int fpu_alloc(struct fpu *fpu)
463 if (fpu_allocated(fpu))
465 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
468 WARN_ON((unsigned long)fpu->state & 15);
472 static inline void fpu_free(struct fpu *fpu)
475 kmem_cache_free(task_xstate_cachep, fpu->state);
480 static inline void fpu_copy(struct fpu *dst, struct fpu *src)
482 memcpy(dst->state, src->state, xstate_size);
485 #endif /* __ASSEMBLY__ */
487 #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
488 #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
490 #endif /* _ASM_X86_I387_H */