5 * KVM x86 specific structures and definitions
9 #include <linux/types.h>
10 #include <linux/ioctl.h>
12 /* Select x86 specific features in <linux/kvm.h> */
13 #define __KVM_HAVE_PIT
14 #define __KVM_HAVE_IOAPIC
15 #define __KVM_HAVE_DEVICE_ASSIGNMENT
16 #define __KVM_HAVE_MSI
17 #define __KVM_HAVE_USER_NMI
18 #define __KVM_HAVE_GUEST_DEBUG
19 #define __KVM_HAVE_MSIX
20 #define __KVM_HAVE_MCE
21 #define __KVM_HAVE_PIT_STATE2
23 /* Architectural interrupt line count. */
24 #define KVM_NR_INTERRUPTS 256
26 struct kvm_memory_alias {
27 __u32 slot; /* this has a different namespace than memory slots */
29 __u64 guest_phys_addr;
31 __u64 target_phys_addr;
34 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
35 struct kvm_pic_state {
36 __u8 last_irr; /* edge detection */
37 __u8 irr; /* interrupt request register */
38 __u8 imr; /* interrupt mask register */
39 __u8 isr; /* interrupt service register */
40 __u8 priority_add; /* highest irq priority */
47 __u8 rotate_on_auto_eoi;
48 __u8 special_fully_nested_mode;
49 __u8 init4; /* true if 4 byte init */
50 __u8 elcr; /* PIIX edge/trigger selection */
54 #define KVM_IOAPIC_NUM_PINS 24
55 struct kvm_ioapic_state {
67 __u8 delivery_status:1;
76 } redirtbl[KVM_IOAPIC_NUM_PINS];
79 #define KVM_IRQCHIP_PIC_MASTER 0
80 #define KVM_IRQCHIP_PIC_SLAVE 1
81 #define KVM_IRQCHIP_IOAPIC 2
83 /* for KVM_GET_REGS and KVM_SET_REGS */
85 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
86 __u64 rax, rbx, rcx, rdx;
87 __u64 rsi, rdi, rsp, rbp;
88 __u64 r8, r9, r10, r11;
89 __u64 r12, r13, r14, r15;
93 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
94 #define KVM_APIC_REG_SIZE 0x400
95 struct kvm_lapic_state {
96 char regs[KVM_APIC_REG_SIZE];
104 __u8 present, dpl, db, s, l, g, avl;
116 /* for KVM_GET_SREGS and KVM_SET_SREGS */
118 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
119 struct kvm_segment cs, ds, es, fs, gs, ss;
120 struct kvm_segment tr, ldt;
121 struct kvm_dtable gdt, idt;
122 __u64 cr0, cr2, cr3, cr4, cr8;
125 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
128 /* for KVM_GET_FPU and KVM_SET_FPU */
133 __u8 ftwx; /* in fxsave format */
143 struct kvm_msr_entry {
149 /* for KVM_GET_MSRS and KVM_SET_MSRS */
151 __u32 nmsrs; /* number of msrs in entries */
154 struct kvm_msr_entry entries[0];
157 /* for KVM_GET_MSR_INDEX_LIST */
158 struct kvm_msr_list {
159 __u32 nmsrs; /* number of msrs in entries */
164 struct kvm_cpuid_entry {
173 /* for KVM_SET_CPUID */
177 struct kvm_cpuid_entry entries[0];
180 struct kvm_cpuid_entry2 {
191 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
192 #define KVM_CPUID_FLAG_STATEFUL_FUNC 2
193 #define KVM_CPUID_FLAG_STATE_READ_NEXT 4
195 /* for KVM_SET_CPUID2 */
199 struct kvm_cpuid_entry2 entries[0];
202 /* for KVM_GET_PIT and KVM_SET_PIT */
203 struct kvm_pit_channel_state {
204 __u32 count; /* can be 65536 */
216 __s64 count_load_time;
219 struct kvm_debug_exit_arch {
227 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
228 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
229 #define KVM_GUESTDBG_INJECT_DB 0x00040000
230 #define KVM_GUESTDBG_INJECT_BP 0x00080000
232 /* for KVM_SET_GUEST_DEBUG */
233 struct kvm_guest_debug_arch {
237 struct kvm_pit_state {
238 struct kvm_pit_channel_state channels[3];
241 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
243 struct kvm_pit_state2 {
244 struct kvm_pit_channel_state channels[3];
249 struct kvm_reinject_control {
253 #endif /* _ASM_X86_KVM_H */