5 * KVM x86 specific structures and definitions
9 #include <linux/types.h>
10 #include <linux/ioctl.h>
12 /* Select x86 specific features in <linux/kvm.h> */
13 #define __KVM_HAVE_PIT
14 #define __KVM_HAVE_IOAPIC
15 #define __KVM_HAVE_DEVICE_ASSIGNMENT
16 #define __KVM_HAVE_MSI
17 #define __KVM_HAVE_USER_NMI
18 #define __KVM_HAVE_GUEST_DEBUG
19 #define __KVM_HAVE_MSIX
20 #define __KVM_HAVE_MCE
21 #define __KVM_HAVE_PIT_STATE2
22 #define __KVM_HAVE_XEN_HVM
23 #define __KVM_HAVE_VCPU_EVENTS
24 #define __KVM_HAVE_DEBUGREGS
26 /* Architectural interrupt line count. */
27 #define KVM_NR_INTERRUPTS 256
29 struct kvm_memory_alias {
30 __u32 slot; /* this has a different namespace than memory slots */
32 __u64 guest_phys_addr;
34 __u64 target_phys_addr;
37 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
38 struct kvm_pic_state {
39 __u8 last_irr; /* edge detection */
40 __u8 irr; /* interrupt request register */
41 __u8 imr; /* interrupt mask register */
42 __u8 isr; /* interrupt service register */
43 __u8 priority_add; /* highest irq priority */
50 __u8 rotate_on_auto_eoi;
51 __u8 special_fully_nested_mode;
52 __u8 init4; /* true if 4 byte init */
53 __u8 elcr; /* PIIX edge/trigger selection */
57 #define KVM_IOAPIC_NUM_PINS 24
58 struct kvm_ioapic_state {
70 __u8 delivery_status:1;
79 } redirtbl[KVM_IOAPIC_NUM_PINS];
82 #define KVM_IRQCHIP_PIC_MASTER 0
83 #define KVM_IRQCHIP_PIC_SLAVE 1
84 #define KVM_IRQCHIP_IOAPIC 2
85 #define KVM_NR_IRQCHIPS 3
87 /* for KVM_GET_REGS and KVM_SET_REGS */
89 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
90 __u64 rax, rbx, rcx, rdx;
91 __u64 rsi, rdi, rsp, rbp;
92 __u64 r8, r9, r10, r11;
93 __u64 r12, r13, r14, r15;
97 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
98 #define KVM_APIC_REG_SIZE 0x400
99 struct kvm_lapic_state {
100 char regs[KVM_APIC_REG_SIZE];
108 __u8 present, dpl, db, s, l, g, avl;
120 /* for KVM_GET_SREGS and KVM_SET_SREGS */
122 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
123 struct kvm_segment cs, ds, es, fs, gs, ss;
124 struct kvm_segment tr, ldt;
125 struct kvm_dtable gdt, idt;
126 __u64 cr0, cr2, cr3, cr4, cr8;
129 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
132 /* for KVM_GET_FPU and KVM_SET_FPU */
137 __u8 ftwx; /* in fxsave format */
147 struct kvm_msr_entry {
153 /* for KVM_GET_MSRS and KVM_SET_MSRS */
155 __u32 nmsrs; /* number of msrs in entries */
158 struct kvm_msr_entry entries[0];
161 /* for KVM_GET_MSR_INDEX_LIST */
162 struct kvm_msr_list {
163 __u32 nmsrs; /* number of msrs in entries */
168 struct kvm_cpuid_entry {
177 /* for KVM_SET_CPUID */
181 struct kvm_cpuid_entry entries[0];
184 struct kvm_cpuid_entry2 {
195 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
196 #define KVM_CPUID_FLAG_STATEFUL_FUNC 2
197 #define KVM_CPUID_FLAG_STATE_READ_NEXT 4
199 /* for KVM_SET_CPUID2 */
203 struct kvm_cpuid_entry2 entries[0];
206 /* for KVM_GET_PIT and KVM_SET_PIT */
207 struct kvm_pit_channel_state {
208 __u32 count; /* can be 65536 */
220 __s64 count_load_time;
223 struct kvm_debug_exit_arch {
231 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
232 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
233 #define KVM_GUESTDBG_INJECT_DB 0x00040000
234 #define KVM_GUESTDBG_INJECT_BP 0x00080000
236 /* for KVM_SET_GUEST_DEBUG */
237 struct kvm_guest_debug_arch {
241 struct kvm_pit_state {
242 struct kvm_pit_channel_state channels[3];
245 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
247 struct kvm_pit_state2 {
248 struct kvm_pit_channel_state channels[3];
253 struct kvm_reinject_control {
258 /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
259 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
260 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
261 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
263 /* Interrupt shadow states */
264 #define KVM_X86_SHADOW_INT_MOV_SS 0x01
265 #define KVM_X86_SHADOW_INT_STI 0x02
267 /* for KVM_GET/SET_VCPU_EVENTS */
268 struct kvm_vcpu_events {
293 /* for KVM_GET/SET_DEBUGREGS */
294 struct kvm_debugregs {
302 #endif /* _ASM_X86_KVM_H */