1 /* OLPC machine specific definitions */
3 #ifndef _ASM_X86_OLPC_H
4 #define _ASM_X86_OLPC_H
8 struct olpc_platform_t {
14 #define OLPC_F_PRESENT 0x01
15 #define OLPC_F_DCON 0x02
19 extern struct olpc_platform_t olpc_platform_info;
22 * OLPC board IDs contain the major build number within the mask 0x0ff0,
23 * and the minor build number withing 0x000f. Pre-builds have a minor
24 * number less than 8, and normal builds start at 8. For example, 0x0B10
25 * is a PreB1, and 0x0C18 is a C1.
28 static inline uint32_t olpc_board(uint8_t id)
30 return (id << 4) | 0x8;
33 static inline uint32_t olpc_board_pre(uint8_t id)
38 static inline int machine_is_olpc(void)
40 return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0;
44 * The DCON is OLPC's Display Controller. It has a number of unique
45 * features that we might want to take advantage of..
47 static inline int olpc_has_dcon(void)
49 return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0;
53 * The "Mass Production" version of OLPC's XO is identified as being model
54 * C2. During the prototype phase, the following models (in chronological
55 * order) were created: A1, B1, B2, B3, B4, C1. The A1 through B2 models
56 * were based on Geode GX CPUs, and models after that were based upon
57 * Geode LX CPUs. There were also some hand-assembled models floating
58 * around, referred to as PreB1, PreB2, etc.
60 static inline int olpc_board_at_least(uint32_t rev)
62 return olpc_platform_info.boardrev >= rev;
67 static inline int machine_is_olpc(void)
72 static inline int olpc_has_dcon(void)
79 extern int pci_olpc_init(void);
81 /* EC related functions */
83 extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
84 unsigned char *outbuf, size_t outlen);
86 extern int olpc_ec_mask_set(uint8_t bits);
87 extern int olpc_ec_mask_unset(uint8_t bits);
91 #define EC_FIRMWARE_REV 0x08
93 /* SCI source values */
95 #define EC_SCI_SRC_EMPTY 0x00
96 #define EC_SCI_SRC_GAME 0x01
97 #define EC_SCI_SRC_BATTERY 0x02
98 #define EC_SCI_SRC_BATSOC 0x04
99 #define EC_SCI_SRC_BATERR 0x08
100 #define EC_SCI_SRC_EBOOK 0x10
101 #define EC_SCI_SRC_WLAN 0x20
102 #define EC_SCI_SRC_ACPWR 0x40
103 #define EC_SCI_SRC_ALL 0x7F
105 /* GPIO assignments */
107 #define OLPC_GPIO_MIC_AC 1
108 #define OLPC_GPIO_DCON_IRQ geode_gpio(7)
109 #define OLPC_GPIO_THRM_ALRM geode_gpio(10)
110 #define OLPC_GPIO_SMB_CLK geode_gpio(14)
111 #define OLPC_GPIO_SMB_DATA geode_gpio(15)
112 #define OLPC_GPIO_WORKAUX geode_gpio(24)
113 #define OLPC_GPIO_LID geode_gpio(26)
114 #define OLPC_GPIO_ECSCI geode_gpio(27)
116 #endif /* _ASM_X86_OLPC_H */