1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75 extern s8 __read_mostly tlb_flushall_shift;
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head.S, so think twice
80 * before touching them. [mj]
84 __u8 x86; /* CPU family */
85 __u8 x86_vendor; /* CPU vendor */
89 char wp_works_ok; /* It doesn't on 386's */
91 /* Problems on some 486Dx4's and old 386's: */
99 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
104 /* CPUID returned core id bits: */
105 __u8 x86_coreid_bits;
106 /* Max extended CPUID function supported: */
107 __u32 extended_cpuid_level;
108 /* Maximum supported CPUID level, -1=no CPUID: */
110 __u32 x86_capability[NCAPINTS];
111 char x86_vendor_id[16];
112 char x86_model_id[64];
113 /* in KB - valid for CPUS which support this call: */
115 int x86_cache_alignment; /* In bytes */
117 unsigned long loops_per_jiffy;
118 /* cpuid returned max cores value: */
122 u16 x86_clflush_size;
123 /* number of cores as seen by the OS: */
125 /* Physical processor id: */
129 /* Compute unit id */
131 /* Index into per_cpu list: */
134 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
136 #define X86_VENDOR_INTEL 0
137 #define X86_VENDOR_CYRIX 1
138 #define X86_VENDOR_AMD 2
139 #define X86_VENDOR_UMC 3
140 #define X86_VENDOR_CENTAUR 5
141 #define X86_VENDOR_TRANSMETA 7
142 #define X86_VENDOR_NSC 8
143 #define X86_VENDOR_NUM 9
145 #define X86_VENDOR_UNKNOWN 0xff
148 * capabilities of CPUs
150 extern struct cpuinfo_x86 boot_cpu_data;
151 extern struct cpuinfo_x86 new_cpu_data;
153 extern struct tss_struct doublefault_tss;
154 extern __u32 cpu_caps_cleared[NCAPINTS];
155 extern __u32 cpu_caps_set[NCAPINTS];
158 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
159 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
161 #define cpu_info boot_cpu_data
162 #define cpu_data(cpu) boot_cpu_data
165 extern const struct seq_operations cpuinfo_op;
167 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
169 extern void cpu_detect(struct cpuinfo_x86 *c);
171 extern void early_cpu_init(void);
172 extern void identify_boot_cpu(void);
173 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
174 extern void print_cpu_info(struct cpuinfo_x86 *);
175 void print_cpu_msr(struct cpuinfo_x86 *);
176 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
177 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
178 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
180 extern void detect_extended_topology(struct cpuinfo_x86 *c);
181 extern void detect_ht(struct cpuinfo_x86 *c);
184 extern int have_cpuid_p(void);
186 static inline int have_cpuid_p(void)
191 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
192 unsigned int *ecx, unsigned int *edx)
194 /* ecx is often an input as well as an output. */
200 : "0" (*eax), "2" (*ecx)
204 static inline void load_cr3(pgd_t *pgdir)
206 write_cr3(__pa(pgdir));
210 /* This is the TSS defined by the hardware. */
212 unsigned short back_link, __blh;
214 unsigned short ss0, __ss0h;
216 /* ss1 caches MSR_IA32_SYSENTER_CS: */
217 unsigned short ss1, __ss1h;
219 unsigned short ss2, __ss2h;
231 unsigned short es, __esh;
232 unsigned short cs, __csh;
233 unsigned short ss, __ssh;
234 unsigned short ds, __dsh;
235 unsigned short fs, __fsh;
236 unsigned short gs, __gsh;
237 unsigned short ldt, __ldth;
238 unsigned short trace;
239 unsigned short io_bitmap_base;
241 } __attribute__((packed));
255 } __attribute__((packed)) ____cacheline_aligned;
261 #define IO_BITMAP_BITS 65536
262 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
263 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
264 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
265 #define INVALID_IO_BITMAP_OFFSET 0x8000
269 * The hardware state:
271 struct x86_hw_tss x86_tss;
274 * The extra 1 is there because the CPU will access an
275 * additional byte beyond the end of the IO permission
276 * bitmap. The extra byte must be all 1 bits, and must
277 * be within the limit.
279 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
282 * .. and then another 0x100 bytes for the emergency kernel stack:
284 unsigned long stack[64];
286 } ____cacheline_aligned;
288 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
291 * Save the original ist values for checking stack pointers during debugging
294 unsigned long ist[7];
297 #define MXCSR_DEFAULT 0x1f80
299 struct i387_fsave_struct {
300 u32 cwd; /* FPU Control Word */
301 u32 swd; /* FPU Status Word */
302 u32 twd; /* FPU Tag Word */
303 u32 fip; /* FPU IP Offset */
304 u32 fcs; /* FPU IP Selector */
305 u32 foo; /* FPU Operand Pointer Offset */
306 u32 fos; /* FPU Operand Pointer Selector */
308 /* 8*10 bytes for each FP-reg = 80 bytes: */
311 /* Software status information [not touched by FSAVE ]: */
315 struct i387_fxsave_struct {
316 u16 cwd; /* Control Word */
317 u16 swd; /* Status Word */
318 u16 twd; /* Tag Word */
319 u16 fop; /* Last Instruction Opcode */
322 u64 rip; /* Instruction Pointer */
323 u64 rdp; /* Data Pointer */
326 u32 fip; /* FPU IP Offset */
327 u32 fcs; /* FPU IP Selector */
328 u32 foo; /* FPU Operand Offset */
329 u32 fos; /* FPU Operand Selector */
332 u32 mxcsr; /* MXCSR Register State */
333 u32 mxcsr_mask; /* MXCSR Mask */
335 /* 8*16 bytes for each FP-reg = 128 bytes: */
338 /* 16*16 bytes for each XMM-reg = 256 bytes: */
348 } __attribute__((aligned(16)));
350 struct i387_soft_struct {
358 /* 8*10 bytes for each FP-reg = 80 bytes: */
366 struct math_emu_info *info;
371 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
375 struct xsave_hdr_struct {
379 } __attribute__((packed));
381 struct xsave_struct {
382 struct i387_fxsave_struct i387;
383 struct xsave_hdr_struct xsave_hdr;
384 struct ymmh_struct ymmh;
385 /* new processor state extensions will go here */
386 } __attribute__ ((packed, aligned (64)));
388 union thread_xstate {
389 struct i387_fsave_struct fsave;
390 struct i387_fxsave_struct fxsave;
391 struct i387_soft_struct soft;
392 struct xsave_struct xsave;
396 unsigned int last_cpu;
397 unsigned int has_fpu;
398 union thread_xstate *state;
402 DECLARE_PER_CPU(struct orig_ist, orig_ist);
404 union irq_stack_union {
405 char irq_stack[IRQ_STACK_SIZE];
407 * GCC hardcodes the stack canary as %gs:40. Since the
408 * irq_stack is the object at %gs:0, we reserve the bottom
409 * 48 bytes of the irq stack for the canary.
413 unsigned long stack_canary;
417 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
418 DECLARE_INIT_PER_CPU(irq_stack_union);
420 DECLARE_PER_CPU(char *, irq_stack_ptr);
421 DECLARE_PER_CPU(unsigned int, irq_count);
422 extern asmlinkage void ignore_sysret(void);
424 #ifdef CONFIG_CC_STACKPROTECTOR
426 * Make sure stack canary segment base is cached-aligned:
427 * "For Intel Atom processors, avoid non zero segment base address
428 * that is not aligned to cache line boundary at all cost."
429 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
431 struct stack_canary {
432 char __pad[20]; /* canary at %gs:20 */
433 unsigned long canary;
435 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
439 extern unsigned int xstate_size;
440 extern void free_thread_xstate(struct task_struct *);
441 extern struct kmem_cache *task_xstate_cachep;
445 struct thread_struct {
446 /* Cached TLS descriptors: */
447 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
451 unsigned long sysenter_cs;
453 unsigned long usersp; /* Copy from PDA */
456 unsigned short fsindex;
457 unsigned short gsindex;
466 /* Save middle states of ptrace breakpoints */
467 struct perf_event *ptrace_bps[HBP_NUM];
468 /* Debug status used for traps, single steps, etc... */
469 unsigned long debugreg6;
470 /* Keep track of the exact dr7 value set by the user */
471 unsigned long ptrace_dr7;
474 unsigned long trap_nr;
475 unsigned long error_code;
476 /* floating point and extended processor state */
479 /* Virtual 86 mode info */
480 struct vm86_struct __user *vm86_info;
481 unsigned long screen_bitmap;
482 unsigned long v86flags;
483 unsigned long v86mask;
484 unsigned long saved_sp0;
485 unsigned int saved_fs;
486 unsigned int saved_gs;
488 /* IO permissions: */
489 unsigned long *io_bitmap_ptr;
491 /* Max allowed port in the bitmap, in bytes: */
492 unsigned io_bitmap_max;
496 * Set IOPL bits in EFLAGS from given mask
498 static inline void native_set_iopl_mask(unsigned mask)
503 asm volatile ("pushfl;"
510 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
515 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
517 tss->x86_tss.sp0 = thread->sp0;
519 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
520 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
521 tss->x86_tss.ss1 = thread->sysenter_cs;
522 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
527 static inline void native_swapgs(void)
530 asm volatile("swapgs" ::: "memory");
534 #ifdef CONFIG_PARAVIRT
535 #include <asm/paravirt.h>
537 #define __cpuid native_cpuid
538 #define paravirt_enabled() 0
540 static inline void load_sp0(struct tss_struct *tss,
541 struct thread_struct *thread)
543 native_load_sp0(tss, thread);
546 #define set_iopl_mask native_set_iopl_mask
547 #endif /* CONFIG_PARAVIRT */
550 * Save the cr4 feature set we're using (ie
551 * Pentium 4MB enable and PPro Global page
552 * enable), so that any CPU's that boot up
553 * after us can get the correct flags.
555 extern unsigned long mmu_cr4_features;
556 extern u32 *trampoline_cr4_features;
558 static inline void set_in_cr4(unsigned long mask)
562 mmu_cr4_features |= mask;
563 if (trampoline_cr4_features)
564 *trampoline_cr4_features = mmu_cr4_features;
570 static inline void clear_in_cr4(unsigned long mask)
574 mmu_cr4_features &= ~mask;
575 if (trampoline_cr4_features)
576 *trampoline_cr4_features = mmu_cr4_features;
587 /* Free all resources held by a thread. */
588 extern void release_thread(struct task_struct *);
590 unsigned long get_wchan(struct task_struct *p);
593 * Generic CPUID function
594 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
595 * resulting in stale register contents being returned.
597 static inline void cpuid(unsigned int op,
598 unsigned int *eax, unsigned int *ebx,
599 unsigned int *ecx, unsigned int *edx)
603 __cpuid(eax, ebx, ecx, edx);
606 /* Some CPUID calls want 'count' to be placed in ecx */
607 static inline void cpuid_count(unsigned int op, int count,
608 unsigned int *eax, unsigned int *ebx,
609 unsigned int *ecx, unsigned int *edx)
613 __cpuid(eax, ebx, ecx, edx);
617 * CPUID functions returning a single datum
619 static inline unsigned int cpuid_eax(unsigned int op)
621 unsigned int eax, ebx, ecx, edx;
623 cpuid(op, &eax, &ebx, &ecx, &edx);
628 static inline unsigned int cpuid_ebx(unsigned int op)
630 unsigned int eax, ebx, ecx, edx;
632 cpuid(op, &eax, &ebx, &ecx, &edx);
637 static inline unsigned int cpuid_ecx(unsigned int op)
639 unsigned int eax, ebx, ecx, edx;
641 cpuid(op, &eax, &ebx, &ecx, &edx);
646 static inline unsigned int cpuid_edx(unsigned int op)
648 unsigned int eax, ebx, ecx, edx;
650 cpuid(op, &eax, &ebx, &ecx, &edx);
655 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
656 static inline void rep_nop(void)
658 asm volatile("rep; nop" ::: "memory");
661 static inline void cpu_relax(void)
666 /* Stop speculative execution and prefetching of modified code. */
667 static inline void sync_core(void)
673 * Do a CPUID if available, otherwise do a jump. The jump
674 * can conveniently enough be the jump around CPUID.
676 asm volatile("cmpl %2,%1\n\t"
681 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
682 : "ebx", "ecx", "edx", "memory");
685 * CPUID is a barrier to speculative execution.
686 * Prefetched instructions are automatically
687 * invalidated when modified.
692 : "ebx", "ecx", "edx", "memory");
696 static inline void __monitor(const void *eax, unsigned long ecx,
699 /* "monitor %eax, %ecx, %edx;" */
700 asm volatile(".byte 0x0f, 0x01, 0xc8;"
701 :: "a" (eax), "c" (ecx), "d"(edx));
704 static inline void __mwait(unsigned long eax, unsigned long ecx)
706 /* "mwait %eax, %ecx;" */
707 asm volatile(".byte 0x0f, 0x01, 0xc9;"
708 :: "a" (eax), "c" (ecx));
711 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
714 /* "mwait %eax, %ecx;" */
715 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
716 :: "a" (eax), "c" (ecx));
719 extern void select_idle_routine(const struct cpuinfo_x86 *c);
720 extern void init_amd_e400_c1e_mask(void);
722 extern unsigned long boot_option_idle_override;
723 extern bool amd_e400_c1e_detected;
725 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
728 extern void enable_sep_cpu(void);
729 extern int sysenter_setup(void);
731 extern void early_trap_init(void);
732 void early_trap_pf_init(void);
734 /* Defined in head.S */
735 extern struct desc_ptr early_gdt_descr;
737 extern void cpu_set_gdt(int);
738 extern void switch_to_new_gdt(int);
739 extern void load_percpu_segment(int);
740 extern void cpu_init(void);
742 static inline unsigned long get_debugctlmsr(void)
744 unsigned long debugctlmsr = 0;
746 #ifndef CONFIG_X86_DEBUGCTLMSR
747 if (boot_cpu_data.x86 < 6)
750 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
755 static inline void update_debugctlmsr(unsigned long debugctlmsr)
757 #ifndef CONFIG_X86_DEBUGCTLMSR
758 if (boot_cpu_data.x86 < 6)
761 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
764 extern void set_task_blockstep(struct task_struct *task, bool on);
767 * from system description table in BIOS. Mostly for MCA use, but
768 * others may find it useful:
770 extern unsigned int machine_id;
771 extern unsigned int machine_submodel_id;
772 extern unsigned int BIOS_revision;
774 /* Boot loader type from the setup header: */
775 extern int bootloader_type;
776 extern int bootloader_version;
778 extern char ignore_fpu_irq;
780 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
781 #define ARCH_HAS_PREFETCHW
782 #define ARCH_HAS_SPINLOCK_PREFETCH
785 # define BASE_PREFETCH ASM_NOP4
786 # define ARCH_HAS_PREFETCH
788 # define BASE_PREFETCH "prefetcht0 (%1)"
792 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
794 * It's not worth to care about 3dnow prefetches for the K6
795 * because they are microcoded there and very slow.
797 static inline void prefetch(const void *x)
799 alternative_input(BASE_PREFETCH,
806 * 3dnow prefetch to get an exclusive cache line.
807 * Useful for spinlocks to avoid one state transition in the
808 * cache coherency protocol:
810 static inline void prefetchw(const void *x)
812 alternative_input(BASE_PREFETCH,
818 static inline void spin_lock_prefetch(const void *x)
825 * User space process size: 3GB (default).
827 #define TASK_SIZE PAGE_OFFSET
828 #define TASK_SIZE_MAX TASK_SIZE
829 #define STACK_TOP TASK_SIZE
830 #define STACK_TOP_MAX STACK_TOP
832 #define INIT_THREAD { \
833 .sp0 = sizeof(init_stack) + (long)&init_stack, \
835 .sysenter_cs = __KERNEL_CS, \
836 .io_bitmap_ptr = NULL, \
840 * Note that the .io_bitmap member must be extra-big. This is because
841 * the CPU will access an additional byte beyond the end of the IO
842 * permission bitmap. The extra byte must be all 1 bits, and must
843 * be within the limit.
847 .sp0 = sizeof(init_stack) + (long)&init_stack, \
848 .ss0 = __KERNEL_DS, \
849 .ss1 = __KERNEL_CS, \
850 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
852 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
855 extern unsigned long thread_saved_pc(struct task_struct *tsk);
857 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
858 #define KSTK_TOP(info) \
860 unsigned long *__ptr = (unsigned long *)(info); \
861 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
865 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
866 * This is necessary to guarantee that the entire "struct pt_regs"
867 * is accessible even if the CPU haven't stored the SS/ESP registers
868 * on the stack (interrupt gate does not save these registers
869 * when switching to the same priv ring).
870 * Therefore beware: accessing the ss/esp fields of the
871 * "struct pt_regs" is possible, but they may contain the
872 * completely wrong values.
874 #define task_pt_regs(task) \
876 struct pt_regs *__regs__; \
877 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
881 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
885 * User space process size. 47bits minus one guard page.
887 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
889 /* This decides where the kernel will search for a free chunk of vm
890 * space during mmap's.
892 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
893 0xc0000000 : 0xFFFFe000)
895 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
896 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
897 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
898 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
900 #define STACK_TOP TASK_SIZE
901 #define STACK_TOP_MAX TASK_SIZE_MAX
903 #define INIT_THREAD { \
904 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
908 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
912 * Return saved PC of a blocked thread.
913 * What is this good for? it will be always the scheduler or ret_from_fork.
915 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
917 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
918 extern unsigned long KSTK_ESP(struct task_struct *task);
921 * User space RSP while inside the SYSCALL fast path
923 DECLARE_PER_CPU(unsigned long, old_rsp);
925 #endif /* CONFIG_X86_64 */
927 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
928 unsigned long new_sp);
931 * This decides where the kernel will search for a free chunk of vm
932 * space during mmap's.
934 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
936 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
938 /* Get/set a process' ability to use the timestamp counter instruction */
939 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
940 #define SET_TSC_CTL(val) set_tsc_mode((val))
942 extern int get_tsc_mode(unsigned long adr);
943 extern int set_tsc_mode(unsigned int val);
945 extern u16 amd_get_nb_id(int cpu);
951 static inline void get_aperfmperf(struct aperfmperf *am)
953 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
955 rdmsrl(MSR_IA32_APERF, am->aperf);
956 rdmsrl(MSR_IA32_MPERF, am->mperf);
959 #define APERFMPERF_SHIFT 10
962 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
963 struct aperfmperf *new)
965 u64 aperf = new->aperf - old->aperf;
966 u64 mperf = new->mperf - old->mperf;
967 unsigned long ratio = aperf;
969 mperf >>= APERFMPERF_SHIFT;
971 ratio = div64_u64(aperf, mperf);
977 * AMD errata checking
979 #ifdef CONFIG_CPU_SUP_AMD
980 extern const int amd_erratum_383[];
981 extern const int amd_erratum_400[];
982 extern bool cpu_has_amd_erratum(const int *);
984 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
985 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
986 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
987 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
988 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
989 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
990 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
993 #define cpu_has_amd_erratum(x) (false)
994 #endif /* CONFIG_CPU_SUP_AMD */
996 extern unsigned long arch_align_stack(unsigned long sp);
997 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
999 void default_idle(void);
1001 bool xen_set_default_idle(void);
1003 #define xen_set_default_idle 0
1006 void stop_this_cpu(void *dummy);
1008 #endif /* _ASM_X86_PROCESSOR_H */