1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
38 static inline void *current_text_addr(void)
42 asm volatile("mov $1f, %0; 1:":"=r" (pc));
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
62 __u8 x86; /* CPU family */
63 __u8 x86_vendor; /* CPU vendor */
67 char wp_works_ok; /* It doesn't on 386's */
69 /* Problems on some 486Dx4's and old 386's: */
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
83 /* CPUID returned core id bits: */
85 /* Max extended CPUID function supported: */
86 __u32 extended_cpuid_level;
87 /* Maximum supported CPUID level, -1=no CPUID: */
89 __u32 x86_capability[NCAPINTS];
90 char x86_vendor_id[16];
91 char x86_model_id[64];
92 /* in KB - valid for CPUS which support this call: */
94 int x86_cache_alignment; /* In bytes */
96 unsigned long loops_per_jiffy;
97 /* cpuid returned max cores value: */
101 u16 x86_clflush_size;
102 /* number of cores as seen by the OS: */
104 /* Physical processor id: */
108 /* Compute unit id */
110 /* Index into per_cpu list: */
113 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
115 #define X86_VENDOR_INTEL 0
116 #define X86_VENDOR_CYRIX 1
117 #define X86_VENDOR_AMD 2
118 #define X86_VENDOR_UMC 3
119 #define X86_VENDOR_CENTAUR 5
120 #define X86_VENDOR_TRANSMETA 7
121 #define X86_VENDOR_NSC 8
122 #define X86_VENDOR_NUM 9
124 #define X86_VENDOR_UNKNOWN 0xff
127 * capabilities of CPUs
129 extern struct cpuinfo_x86 boot_cpu_data;
130 extern struct cpuinfo_x86 new_cpu_data;
132 extern struct tss_struct doublefault_tss;
133 extern __u32 cpu_caps_cleared[NCAPINTS];
134 extern __u32 cpu_caps_set[NCAPINTS];
137 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
138 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
140 #define cpu_info boot_cpu_data
141 #define cpu_data(cpu) boot_cpu_data
144 extern const struct seq_operations cpuinfo_op;
146 static inline int hlt_works(int cpu)
149 return cpu_data(cpu).hlt_works_ok;
155 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
157 extern void cpu_detect(struct cpuinfo_x86 *c);
159 extern struct pt_regs *idle_regs(struct pt_regs *);
161 extern void early_cpu_init(void);
162 extern void identify_boot_cpu(void);
163 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
164 extern void print_cpu_info(struct cpuinfo_x86 *);
165 void print_cpu_msr(struct cpuinfo_x86 *);
166 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
167 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
168 extern unsigned short num_cache_leaves;
170 extern void detect_extended_topology(struct cpuinfo_x86 *c);
171 extern void detect_ht(struct cpuinfo_x86 *c);
173 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
174 unsigned int *ecx, unsigned int *edx)
176 /* ecx is often an input as well as an output. */
182 : "0" (*eax), "2" (*ecx)
186 static inline void load_cr3(pgd_t *pgdir)
188 write_cr3(__pa(pgdir));
192 /* This is the TSS defined by the hardware. */
194 unsigned short back_link, __blh;
196 unsigned short ss0, __ss0h;
198 /* ss1 caches MSR_IA32_SYSENTER_CS: */
199 unsigned short ss1, __ss1h;
201 unsigned short ss2, __ss2h;
213 unsigned short es, __esh;
214 unsigned short cs, __csh;
215 unsigned short ss, __ssh;
216 unsigned short ds, __dsh;
217 unsigned short fs, __fsh;
218 unsigned short gs, __gsh;
219 unsigned short ldt, __ldth;
220 unsigned short trace;
221 unsigned short io_bitmap_base;
223 } __attribute__((packed));
237 } __attribute__((packed)) ____cacheline_aligned;
243 #define IO_BITMAP_BITS 65536
244 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
245 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
246 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
247 #define INVALID_IO_BITMAP_OFFSET 0x8000
251 * The hardware state:
253 struct x86_hw_tss x86_tss;
256 * The extra 1 is there because the CPU will access an
257 * additional byte beyond the end of the IO permission
258 * bitmap. The extra byte must be all 1 bits, and must
259 * be within the limit.
261 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
264 * .. and then another 0x100 bytes for the emergency kernel stack:
266 unsigned long stack[64];
268 } ____cacheline_aligned;
270 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
273 * Save the original ist values for checking stack pointers during debugging
276 unsigned long ist[7];
279 #define MXCSR_DEFAULT 0x1f80
281 struct i387_fsave_struct {
282 u32 cwd; /* FPU Control Word */
283 u32 swd; /* FPU Status Word */
284 u32 twd; /* FPU Tag Word */
285 u32 fip; /* FPU IP Offset */
286 u32 fcs; /* FPU IP Selector */
287 u32 foo; /* FPU Operand Pointer Offset */
288 u32 fos; /* FPU Operand Pointer Selector */
290 /* 8*10 bytes for each FP-reg = 80 bytes: */
293 /* Software status information [not touched by FSAVE ]: */
297 struct i387_fxsave_struct {
298 u16 cwd; /* Control Word */
299 u16 swd; /* Status Word */
300 u16 twd; /* Tag Word */
301 u16 fop; /* Last Instruction Opcode */
304 u64 rip; /* Instruction Pointer */
305 u64 rdp; /* Data Pointer */
308 u32 fip; /* FPU IP Offset */
309 u32 fcs; /* FPU IP Selector */
310 u32 foo; /* FPU Operand Offset */
311 u32 fos; /* FPU Operand Selector */
314 u32 mxcsr; /* MXCSR Register State */
315 u32 mxcsr_mask; /* MXCSR Mask */
317 /* 8*16 bytes for each FP-reg = 128 bytes: */
320 /* 16*16 bytes for each XMM-reg = 256 bytes: */
330 } __attribute__((aligned(16)));
332 struct i387_soft_struct {
340 /* 8*10 bytes for each FP-reg = 80 bytes: */
348 struct math_emu_info *info;
353 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
357 struct xsave_hdr_struct {
361 } __attribute__((packed));
363 struct xsave_struct {
364 struct i387_fxsave_struct i387;
365 struct xsave_hdr_struct xsave_hdr;
366 struct ymmh_struct ymmh;
367 /* new processor state extensions will go here */
368 } __attribute__ ((packed, aligned (64)));
370 union thread_xstate {
371 struct i387_fsave_struct fsave;
372 struct i387_fxsave_struct fxsave;
373 struct i387_soft_struct soft;
374 struct xsave_struct xsave;
378 unsigned int last_cpu;
379 unsigned int has_fpu;
380 union thread_xstate *state;
384 DECLARE_PER_CPU(struct orig_ist, orig_ist);
386 union irq_stack_union {
387 char irq_stack[IRQ_STACK_SIZE];
389 * GCC hardcodes the stack canary as %gs:40. Since the
390 * irq_stack is the object at %gs:0, we reserve the bottom
391 * 48 bytes of the irq stack for the canary.
395 unsigned long stack_canary;
399 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
400 DECLARE_INIT_PER_CPU(irq_stack_union);
402 DECLARE_PER_CPU(char *, irq_stack_ptr);
403 DECLARE_PER_CPU(unsigned int, irq_count);
404 extern unsigned long kernel_eflags;
405 extern asmlinkage void ignore_sysret(void);
407 #ifdef CONFIG_CC_STACKPROTECTOR
409 * Make sure stack canary segment base is cached-aligned:
410 * "For Intel Atom processors, avoid non zero segment base address
411 * that is not aligned to cache line boundary at all cost."
412 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
414 struct stack_canary {
415 char __pad[20]; /* canary at %gs:20 */
416 unsigned long canary;
418 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
422 extern unsigned int xstate_size;
423 extern void free_thread_xstate(struct task_struct *);
424 extern struct kmem_cache *task_xstate_cachep;
428 struct thread_struct {
429 /* Cached TLS descriptors: */
430 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
434 unsigned long sysenter_cs;
436 unsigned long usersp; /* Copy from PDA */
439 unsigned short fsindex;
440 unsigned short gsindex;
449 /* Save middle states of ptrace breakpoints */
450 struct perf_event *ptrace_bps[HBP_NUM];
451 /* Debug status used for traps, single steps, etc... */
452 unsigned long debugreg6;
453 /* Keep track of the exact dr7 value set by the user */
454 unsigned long ptrace_dr7;
457 unsigned long trap_no;
458 unsigned long error_code;
459 /* floating point and extended processor state */
462 /* Virtual 86 mode info */
463 struct vm86_struct __user *vm86_info;
464 unsigned long screen_bitmap;
465 unsigned long v86flags;
466 unsigned long v86mask;
467 unsigned long saved_sp0;
468 unsigned int saved_fs;
469 unsigned int saved_gs;
471 /* IO permissions: */
472 unsigned long *io_bitmap_ptr;
474 /* Max allowed port in the bitmap, in bytes: */
475 unsigned io_bitmap_max;
478 static inline unsigned long native_get_debugreg(int regno)
480 unsigned long val = 0; /* Damn you, gcc! */
484 asm("mov %%db0, %0" :"=r" (val));
487 asm("mov %%db1, %0" :"=r" (val));
490 asm("mov %%db2, %0" :"=r" (val));
493 asm("mov %%db3, %0" :"=r" (val));
496 asm("mov %%db6, %0" :"=r" (val));
499 asm("mov %%db7, %0" :"=r" (val));
507 static inline void native_set_debugreg(int regno, unsigned long value)
511 asm("mov %0, %%db0" ::"r" (value));
514 asm("mov %0, %%db1" ::"r" (value));
517 asm("mov %0, %%db2" ::"r" (value));
520 asm("mov %0, %%db3" ::"r" (value));
523 asm("mov %0, %%db6" ::"r" (value));
526 asm("mov %0, %%db7" ::"r" (value));
534 * Set IOPL bits in EFLAGS from given mask
536 static inline void native_set_iopl_mask(unsigned mask)
541 asm volatile ("pushfl;"
548 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
553 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
555 tss->x86_tss.sp0 = thread->sp0;
557 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
558 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
559 tss->x86_tss.ss1 = thread->sysenter_cs;
560 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
565 static inline void native_swapgs(void)
568 asm volatile("swapgs" ::: "memory");
572 #ifdef CONFIG_PARAVIRT
573 #include <asm/paravirt.h>
575 #define __cpuid native_cpuid
576 #define paravirt_enabled() 0
579 * These special macros can be used to get or set a debugging register
581 #define get_debugreg(var, register) \
582 (var) = native_get_debugreg(register)
583 #define set_debugreg(value, register) \
584 native_set_debugreg(register, value)
586 static inline void load_sp0(struct tss_struct *tss,
587 struct thread_struct *thread)
589 native_load_sp0(tss, thread);
592 #define set_iopl_mask native_set_iopl_mask
593 #endif /* CONFIG_PARAVIRT */
596 * Save the cr4 feature set we're using (ie
597 * Pentium 4MB enable and PPro Global page
598 * enable), so that any CPU's that boot up
599 * after us can get the correct flags.
601 extern unsigned long mmu_cr4_features;
603 static inline void set_in_cr4(unsigned long mask)
607 mmu_cr4_features |= mask;
613 static inline void clear_in_cr4(unsigned long mask)
617 mmu_cr4_features &= ~mask;
629 * create a kernel thread without removing it from tasklists
631 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
633 /* Free all resources held by a thread. */
634 extern void release_thread(struct task_struct *);
636 /* Prepare to copy thread state - unlazy all lazy state */
637 extern void prepare_to_copy(struct task_struct *tsk);
639 unsigned long get_wchan(struct task_struct *p);
642 * Generic CPUID function
643 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
644 * resulting in stale register contents being returned.
646 static inline void cpuid(unsigned int op,
647 unsigned int *eax, unsigned int *ebx,
648 unsigned int *ecx, unsigned int *edx)
652 __cpuid(eax, ebx, ecx, edx);
655 /* Some CPUID calls want 'count' to be placed in ecx */
656 static inline void cpuid_count(unsigned int op, int count,
657 unsigned int *eax, unsigned int *ebx,
658 unsigned int *ecx, unsigned int *edx)
662 __cpuid(eax, ebx, ecx, edx);
666 * CPUID functions returning a single datum
668 static inline unsigned int cpuid_eax(unsigned int op)
670 unsigned int eax, ebx, ecx, edx;
672 cpuid(op, &eax, &ebx, &ecx, &edx);
677 static inline unsigned int cpuid_ebx(unsigned int op)
679 unsigned int eax, ebx, ecx, edx;
681 cpuid(op, &eax, &ebx, &ecx, &edx);
686 static inline unsigned int cpuid_ecx(unsigned int op)
688 unsigned int eax, ebx, ecx, edx;
690 cpuid(op, &eax, &ebx, &ecx, &edx);
695 static inline unsigned int cpuid_edx(unsigned int op)
697 unsigned int eax, ebx, ecx, edx;
699 cpuid(op, &eax, &ebx, &ecx, &edx);
704 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
705 static inline void rep_nop(void)
707 asm volatile("rep; nop" ::: "memory");
710 static inline void cpu_relax(void)
715 /* Stop speculative execution and prefetching of modified code. */
716 static inline void sync_core(void)
720 #if defined(CONFIG_M386) || defined(CONFIG_M486)
721 if (boot_cpu_data.x86 < 5)
722 /* There is no speculative execution.
723 * jmp is a barrier to prefetching. */
724 asm volatile("jmp 1f\n1:\n" ::: "memory");
727 /* cpuid is a barrier to speculative execution.
728 * Prefetched instructions are automatically
729 * invalidated when modified. */
730 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
731 : "ebx", "ecx", "edx", "memory");
734 static inline void __monitor(const void *eax, unsigned long ecx,
737 /* "monitor %eax, %ecx, %edx;" */
738 asm volatile(".byte 0x0f, 0x01, 0xc8;"
739 :: "a" (eax), "c" (ecx), "d"(edx));
742 static inline void __mwait(unsigned long eax, unsigned long ecx)
744 /* "mwait %eax, %ecx;" */
745 asm volatile(".byte 0x0f, 0x01, 0xc9;"
746 :: "a" (eax), "c" (ecx));
749 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
752 /* "mwait %eax, %ecx;" */
753 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
754 :: "a" (eax), "c" (ecx));
757 extern void select_idle_routine(const struct cpuinfo_x86 *c);
758 extern void init_amd_e400_c1e_mask(void);
760 extern unsigned long boot_option_idle_override;
761 extern bool amd_e400_c1e_detected;
763 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
764 IDLE_POLL, IDLE_FORCE_MWAIT};
766 extern void enable_sep_cpu(void);
767 extern int sysenter_setup(void);
769 extern void early_trap_init(void);
771 /* Defined in head.S */
772 extern struct desc_ptr early_gdt_descr;
774 extern void cpu_set_gdt(int);
775 extern void switch_to_new_gdt(int);
776 extern void load_percpu_segment(int);
777 extern void cpu_init(void);
779 static inline unsigned long get_debugctlmsr(void)
781 unsigned long debugctlmsr = 0;
783 #ifndef CONFIG_X86_DEBUGCTLMSR
784 if (boot_cpu_data.x86 < 6)
787 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
792 static inline void update_debugctlmsr(unsigned long debugctlmsr)
794 #ifndef CONFIG_X86_DEBUGCTLMSR
795 if (boot_cpu_data.x86 < 6)
798 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
802 * from system description table in BIOS. Mostly for MCA use, but
803 * others may find it useful:
805 extern unsigned int machine_id;
806 extern unsigned int machine_submodel_id;
807 extern unsigned int BIOS_revision;
809 /* Boot loader type from the setup header: */
810 extern int bootloader_type;
811 extern int bootloader_version;
813 extern char ignore_fpu_irq;
815 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
816 #define ARCH_HAS_PREFETCHW
817 #define ARCH_HAS_SPINLOCK_PREFETCH
820 # define BASE_PREFETCH ASM_NOP4
821 # define ARCH_HAS_PREFETCH
823 # define BASE_PREFETCH "prefetcht0 (%1)"
827 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
829 * It's not worth to care about 3dnow prefetches for the K6
830 * because they are microcoded there and very slow.
832 static inline void prefetch(const void *x)
834 alternative_input(BASE_PREFETCH,
841 * 3dnow prefetch to get an exclusive cache line.
842 * Useful for spinlocks to avoid one state transition in the
843 * cache coherency protocol:
845 static inline void prefetchw(const void *x)
847 alternative_input(BASE_PREFETCH,
853 static inline void spin_lock_prefetch(const void *x)
860 * User space process size: 3GB (default).
862 #define TASK_SIZE PAGE_OFFSET
863 #define TASK_SIZE_MAX TASK_SIZE
864 #define STACK_TOP TASK_SIZE
865 #define STACK_TOP_MAX STACK_TOP
867 #define INIT_THREAD { \
868 .sp0 = sizeof(init_stack) + (long)&init_stack, \
870 .sysenter_cs = __KERNEL_CS, \
871 .io_bitmap_ptr = NULL, \
875 * Note that the .io_bitmap member must be extra-big. This is because
876 * the CPU will access an additional byte beyond the end of the IO
877 * permission bitmap. The extra byte must be all 1 bits, and must
878 * be within the limit.
882 .sp0 = sizeof(init_stack) + (long)&init_stack, \
883 .ss0 = __KERNEL_DS, \
884 .ss1 = __KERNEL_CS, \
885 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
887 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
890 extern unsigned long thread_saved_pc(struct task_struct *tsk);
892 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
893 #define KSTK_TOP(info) \
895 unsigned long *__ptr = (unsigned long *)(info); \
896 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
900 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
901 * This is necessary to guarantee that the entire "struct pt_regs"
902 * is accessible even if the CPU haven't stored the SS/ESP registers
903 * on the stack (interrupt gate does not save these registers
904 * when switching to the same priv ring).
905 * Therefore beware: accessing the ss/esp fields of the
906 * "struct pt_regs" is possible, but they may contain the
907 * completely wrong values.
909 #define task_pt_regs(task) \
911 struct pt_regs *__regs__; \
912 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
916 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
920 * User space process size. 47bits minus one guard page.
922 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
924 /* This decides where the kernel will search for a free chunk of vm
925 * space during mmap's.
927 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
928 0xc0000000 : 0xFFFFe000)
930 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
931 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
932 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
933 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
935 #define STACK_TOP TASK_SIZE
936 #define STACK_TOP_MAX TASK_SIZE_MAX
938 #define INIT_THREAD { \
939 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
943 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
947 * Return saved PC of a blocked thread.
948 * What is this good for? it will be always the scheduler or ret_from_fork.
950 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
952 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
953 extern unsigned long KSTK_ESP(struct task_struct *task);
954 #endif /* CONFIG_X86_64 */
956 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
957 unsigned long new_sp);
960 * This decides where the kernel will search for a free chunk of vm
961 * space during mmap's.
963 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
965 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
967 /* Get/set a process' ability to use the timestamp counter instruction */
968 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
969 #define SET_TSC_CTL(val) set_tsc_mode((val))
971 extern int get_tsc_mode(unsigned long adr);
972 extern int set_tsc_mode(unsigned int val);
974 extern int amd_get_nb_id(int cpu);
980 static inline void get_aperfmperf(struct aperfmperf *am)
982 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
984 rdmsrl(MSR_IA32_APERF, am->aperf);
985 rdmsrl(MSR_IA32_MPERF, am->mperf);
988 #define APERFMPERF_SHIFT 10
991 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
992 struct aperfmperf *new)
994 u64 aperf = new->aperf - old->aperf;
995 u64 mperf = new->mperf - old->mperf;
996 unsigned long ratio = aperf;
998 mperf >>= APERFMPERF_SHIFT;
1000 ratio = div64_u64(aperf, mperf);
1006 * AMD errata checking
1008 #ifdef CONFIG_CPU_SUP_AMD
1009 extern const int amd_erratum_383[];
1010 extern const int amd_erratum_400[];
1011 extern bool cpu_has_amd_erratum(const int *);
1013 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1014 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1015 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1016 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1017 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1018 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1019 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1022 #define cpu_has_amd_erratum(x) (false)
1023 #endif /* CONFIG_CPU_SUP_AMD */
1025 #endif /* _ASM_X86_PROCESSOR_H */