1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
26 #include <linux/personality.h>
27 #include <linux/cpumask.h>
28 #include <linux/cache.h>
29 #include <linux/threads.h>
30 #include <linux/math64.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
57 * These alignment constraints are for performance in the vSMP case,
58 * but in the task_struct case we must also meet hardware imposed
59 * alignment requirements of the FPU state:
61 #ifdef CONFIG_X86_VSMP
62 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
63 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
65 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
66 # define ARCH_MIN_MMSTRUCT_ALIGN 0
74 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
75 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
76 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
77 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
78 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
79 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
80 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
83 * CPU type and hardware bug flags. Kept separately for each CPU.
84 * Members of this structure are referenced in head.S, so think twice
85 * before touching them. [mj]
89 __u8 x86; /* CPU family */
90 __u8 x86_vendor; /* CPU vendor */
94 char wp_works_ok; /* It doesn't on 386's */
96 /* Problems on some 486Dx4's and old 386's: */
101 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
106 /* CPUID returned core id bits: */
107 __u8 x86_coreid_bits;
108 /* Max extended CPUID function supported: */
109 __u32 extended_cpuid_level;
110 /* Maximum supported CPUID level, -1=no CPUID: */
112 __u32 x86_capability[NCAPINTS + NBUGINTS];
113 char x86_vendor_id[16];
114 char x86_model_id[64];
115 /* in KB - valid for CPUS which support this call: */
117 int x86_cache_alignment; /* In bytes */
118 /* Cache QoS architectural values: */
119 int x86_cache_max_rmid; /* max index */
120 int x86_cache_occ_scale; /* scale to bytes */
122 unsigned long loops_per_jiffy;
123 /* cpuid returned max cores value: */
127 u16 x86_clflush_size;
128 /* number of cores as seen by the OS: */
130 /* Physical processor id: */
134 /* Compute unit id */
136 /* Index into per_cpu list: */
141 #define X86_VENDOR_INTEL 0
142 #define X86_VENDOR_CYRIX 1
143 #define X86_VENDOR_AMD 2
144 #define X86_VENDOR_UMC 3
145 #define X86_VENDOR_CENTAUR 5
146 #define X86_VENDOR_TRANSMETA 7
147 #define X86_VENDOR_NSC 8
148 #define X86_VENDOR_NUM 9
150 #define X86_VENDOR_UNKNOWN 0xff
153 * capabilities of CPUs
155 extern struct cpuinfo_x86 boot_cpu_data;
156 extern struct cpuinfo_x86 new_cpu_data;
158 extern struct tss_struct doublefault_tss;
159 extern __u32 cpu_caps_cleared[NCAPINTS];
160 extern __u32 cpu_caps_set[NCAPINTS];
163 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
164 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
166 #define cpu_info boot_cpu_data
167 #define cpu_data(cpu) boot_cpu_data
170 extern const struct seq_operations cpuinfo_op;
172 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
174 extern void cpu_detect(struct cpuinfo_x86 *c);
176 extern void early_cpu_init(void);
177 extern void identify_boot_cpu(void);
178 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
179 extern void print_cpu_info(struct cpuinfo_x86 *);
180 void print_cpu_msr(struct cpuinfo_x86 *);
181 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
182 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
183 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
185 extern void detect_extended_topology(struct cpuinfo_x86 *c);
186 extern void detect_ht(struct cpuinfo_x86 *c);
189 extern int have_cpuid_p(void);
191 static inline int have_cpuid_p(void)
196 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
197 unsigned int *ecx, unsigned int *edx)
199 /* ecx is often an input as well as an output. */
205 : "0" (*eax), "2" (*ecx)
209 static inline void load_cr3(pgd_t *pgdir)
211 write_cr3(__pa(pgdir));
215 /* This is the TSS defined by the hardware. */
217 unsigned short back_link, __blh;
219 unsigned short ss0, __ss0h;
223 * We don't use ring 1, so ss1 is a convenient scratch space in
224 * the same cacheline as sp0. We use ss1 to cache the value in
225 * MSR_IA32_SYSENTER_CS. When we context switch
226 * MSR_IA32_SYSENTER_CS, we first check if the new value being
227 * written matches ss1, and, if it's not, then we wrmsr the new
228 * value and update ss1.
230 * The only reason we context switch MSR_IA32_SYSENTER_CS is
231 * that we set it to zero in vm86 tasks to avoid corrupting the
232 * stack if we were to go through the sysenter path from vm86
235 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
237 unsigned short __ss1h;
239 unsigned short ss2, __ss2h;
251 unsigned short es, __esh;
252 unsigned short cs, __csh;
253 unsigned short ss, __ssh;
254 unsigned short ds, __dsh;
255 unsigned short fs, __fsh;
256 unsigned short gs, __gsh;
257 unsigned short ldt, __ldth;
258 unsigned short trace;
259 unsigned short io_bitmap_base;
261 } __attribute__((packed));
275 } __attribute__((packed)) ____cacheline_aligned;
281 #define IO_BITMAP_BITS 65536
282 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
283 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
284 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
285 #define INVALID_IO_BITMAP_OFFSET 0x8000
289 * The hardware state:
291 struct x86_hw_tss x86_tss;
294 * The extra 1 is there because the CPU will access an
295 * additional byte beyond the end of the IO permission
296 * bitmap. The extra byte must be all 1 bits, and must
297 * be within the limit.
299 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
302 * Space for the temporary SYSENTER stack:
304 unsigned long SYSENTER_stack[64];
306 } ____cacheline_aligned;
308 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
311 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
315 * Save the original ist values for checking stack pointers during debugging
318 unsigned long ist[7];
322 DECLARE_PER_CPU(struct orig_ist, orig_ist);
324 union irq_stack_union {
325 char irq_stack[IRQ_STACK_SIZE];
327 * GCC hardcodes the stack canary as %gs:40. Since the
328 * irq_stack is the object at %gs:0, we reserve the bottom
329 * 48 bytes of the irq stack for the canary.
333 unsigned long stack_canary;
337 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
338 DECLARE_INIT_PER_CPU(irq_stack_union);
340 DECLARE_PER_CPU(char *, irq_stack_ptr);
341 DECLARE_PER_CPU(unsigned int, irq_count);
342 extern asmlinkage void ignore_sysret(void);
344 #ifdef CONFIG_CC_STACKPROTECTOR
346 * Make sure stack canary segment base is cached-aligned:
347 * "For Intel Atom processors, avoid non zero segment base address
348 * that is not aligned to cache line boundary at all cost."
349 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
351 struct stack_canary {
352 char __pad[20]; /* canary at %gs:20 */
353 unsigned long canary;
355 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
358 * per-CPU IRQ handling stacks
361 u32 stack[THREAD_SIZE/sizeof(u32)];
362 } __aligned(THREAD_SIZE);
364 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
365 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
368 extern unsigned int xstate_size;
372 struct thread_struct {
373 /* Cached TLS descriptors: */
374 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
378 unsigned long sysenter_cs;
382 unsigned short fsindex;
383 unsigned short gsindex;
393 /* Save middle states of ptrace breakpoints */
394 struct perf_event *ptrace_bps[HBP_NUM];
395 /* Debug status used for traps, single steps, etc... */
396 unsigned long debugreg6;
397 /* Keep track of the exact dr7 value set by the user */
398 unsigned long ptrace_dr7;
401 unsigned long trap_nr;
402 unsigned long error_code;
404 /* Virtual 86 mode info */
405 struct vm86_struct __user *vm86_info;
406 unsigned long screen_bitmap;
407 unsigned long v86flags;
408 unsigned long v86mask;
409 unsigned long saved_sp0;
410 unsigned int saved_fs;
411 unsigned int saved_gs;
413 /* IO permissions: */
414 unsigned long *io_bitmap_ptr;
416 /* Max allowed port in the bitmap, in bytes: */
417 unsigned io_bitmap_max;
419 /* Floating point and extended processor state */
422 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
428 * Set IOPL bits in EFLAGS from given mask
430 static inline void native_set_iopl_mask(unsigned mask)
435 asm volatile ("pushfl;"
442 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
447 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
449 tss->x86_tss.sp0 = thread->sp0;
451 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
452 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
453 tss->x86_tss.ss1 = thread->sysenter_cs;
454 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
459 static inline void native_swapgs(void)
462 asm volatile("swapgs" ::: "memory");
466 static inline unsigned long current_top_of_stack(void)
469 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
471 /* sp0 on x86_32 is special in and around vm86 mode. */
472 return this_cpu_read_stable(cpu_current_top_of_stack);
476 #ifdef CONFIG_PARAVIRT
477 #include <asm/paravirt.h>
479 #define __cpuid native_cpuid
480 #define paravirt_enabled() 0
482 static inline void load_sp0(struct tss_struct *tss,
483 struct thread_struct *thread)
485 native_load_sp0(tss, thread);
488 #define set_iopl_mask native_set_iopl_mask
489 #endif /* CONFIG_PARAVIRT */
496 /* Free all resources held by a thread. */
497 extern void release_thread(struct task_struct *);
499 unsigned long get_wchan(struct task_struct *p);
502 * Generic CPUID function
503 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
504 * resulting in stale register contents being returned.
506 static inline void cpuid(unsigned int op,
507 unsigned int *eax, unsigned int *ebx,
508 unsigned int *ecx, unsigned int *edx)
512 __cpuid(eax, ebx, ecx, edx);
515 /* Some CPUID calls want 'count' to be placed in ecx */
516 static inline void cpuid_count(unsigned int op, int count,
517 unsigned int *eax, unsigned int *ebx,
518 unsigned int *ecx, unsigned int *edx)
522 __cpuid(eax, ebx, ecx, edx);
526 * CPUID functions returning a single datum
528 static inline unsigned int cpuid_eax(unsigned int op)
530 unsigned int eax, ebx, ecx, edx;
532 cpuid(op, &eax, &ebx, &ecx, &edx);
537 static inline unsigned int cpuid_ebx(unsigned int op)
539 unsigned int eax, ebx, ecx, edx;
541 cpuid(op, &eax, &ebx, &ecx, &edx);
546 static inline unsigned int cpuid_ecx(unsigned int op)
548 unsigned int eax, ebx, ecx, edx;
550 cpuid(op, &eax, &ebx, &ecx, &edx);
555 static inline unsigned int cpuid_edx(unsigned int op)
557 unsigned int eax, ebx, ecx, edx;
559 cpuid(op, &eax, &ebx, &ecx, &edx);
564 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
565 static inline void rep_nop(void)
567 asm volatile("rep; nop" ::: "memory");
570 static inline void cpu_relax(void)
575 #define cpu_relax_lowlatency() cpu_relax()
577 /* Stop speculative execution and prefetching of modified code. */
578 static inline void sync_core(void)
584 * Do a CPUID if available, otherwise do a jump. The jump
585 * can conveniently enough be the jump around CPUID.
587 asm volatile("cmpl %2,%1\n\t"
592 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
593 : "ebx", "ecx", "edx", "memory");
596 * CPUID is a barrier to speculative execution.
597 * Prefetched instructions are automatically
598 * invalidated when modified.
603 : "ebx", "ecx", "edx", "memory");
607 extern void select_idle_routine(const struct cpuinfo_x86 *c);
608 extern void init_amd_e400_c1e_mask(void);
610 extern unsigned long boot_option_idle_override;
611 extern bool amd_e400_c1e_detected;
613 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
616 extern void enable_sep_cpu(void);
617 extern int sysenter_setup(void);
619 extern void early_trap_init(void);
620 void early_trap_pf_init(void);
622 /* Defined in head.S */
623 extern struct desc_ptr early_gdt_descr;
625 extern void cpu_set_gdt(int);
626 extern void switch_to_new_gdt(int);
627 extern void load_percpu_segment(int);
628 extern void cpu_init(void);
630 static inline unsigned long get_debugctlmsr(void)
632 unsigned long debugctlmsr = 0;
634 #ifndef CONFIG_X86_DEBUGCTLMSR
635 if (boot_cpu_data.x86 < 6)
638 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
643 static inline void update_debugctlmsr(unsigned long debugctlmsr)
645 #ifndef CONFIG_X86_DEBUGCTLMSR
646 if (boot_cpu_data.x86 < 6)
649 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
652 extern void set_task_blockstep(struct task_struct *task, bool on);
655 * from system description table in BIOS. Mostly for MCA use, but
656 * others may find it useful:
658 extern unsigned int machine_id;
659 extern unsigned int machine_submodel_id;
660 extern unsigned int BIOS_revision;
662 /* Boot loader type from the setup header: */
663 extern int bootloader_type;
664 extern int bootloader_version;
666 extern char ignore_fpu_irq;
668 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
669 #define ARCH_HAS_PREFETCHW
670 #define ARCH_HAS_SPINLOCK_PREFETCH
673 # define BASE_PREFETCH ""
674 # define ARCH_HAS_PREFETCH
676 # define BASE_PREFETCH "prefetcht0 %P1"
680 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
682 * It's not worth to care about 3dnow prefetches for the K6
683 * because they are microcoded there and very slow.
685 static inline void prefetch(const void *x)
687 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
689 "m" (*(const char *)x));
693 * 3dnow prefetch to get an exclusive cache line.
694 * Useful for spinlocks to avoid one state transition in the
695 * cache coherency protocol:
697 static inline void prefetchw(const void *x)
699 alternative_input(BASE_PREFETCH, "prefetchw %P1",
700 X86_FEATURE_3DNOWPREFETCH,
701 "m" (*(const char *)x));
704 static inline void spin_lock_prefetch(const void *x)
709 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
710 TOP_OF_KERNEL_STACK_PADDING)
714 * User space process size: 3GB (default).
716 #define TASK_SIZE PAGE_OFFSET
717 #define TASK_SIZE_MAX TASK_SIZE
718 #define STACK_TOP TASK_SIZE
719 #define STACK_TOP_MAX STACK_TOP
721 #define INIT_THREAD { \
722 .sp0 = TOP_OF_INIT_STACK, \
724 .sysenter_cs = __KERNEL_CS, \
725 .io_bitmap_ptr = NULL, \
728 extern unsigned long thread_saved_pc(struct task_struct *tsk);
731 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
732 * This is necessary to guarantee that the entire "struct pt_regs"
733 * is accessible even if the CPU haven't stored the SS/ESP registers
734 * on the stack (interrupt gate does not save these registers
735 * when switching to the same priv ring).
736 * Therefore beware: accessing the ss/esp fields of the
737 * "struct pt_regs" is possible, but they may contain the
738 * completely wrong values.
740 #define task_pt_regs(task) \
742 unsigned long __ptr = (unsigned long)task_stack_page(task); \
743 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
744 ((struct pt_regs *)__ptr) - 1; \
747 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
751 * User space process size. 47bits minus one guard page. The guard
752 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
753 * the highest possible canonical userspace address, then that
754 * syscall will enter the kernel with a non-canonical return
755 * address, and SYSRET will explode dangerously. We avoid this
756 * particular problem by preventing anything from being mapped
757 * at the maximum canonical address.
759 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
761 /* This decides where the kernel will search for a free chunk of vm
762 * space during mmap's.
764 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
765 0xc0000000 : 0xFFFFe000)
767 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
768 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
769 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
770 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
772 #define STACK_TOP TASK_SIZE
773 #define STACK_TOP_MAX TASK_SIZE_MAX
775 #define INIT_THREAD { \
776 .sp0 = TOP_OF_INIT_STACK \
780 * Return saved PC of a blocked thread.
781 * What is this good for? it will be always the scheduler or ret_from_fork.
783 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
785 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
786 extern unsigned long KSTK_ESP(struct task_struct *task);
788 #endif /* CONFIG_X86_64 */
790 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
791 unsigned long new_sp);
794 * This decides where the kernel will search for a free chunk of vm
795 * space during mmap's.
797 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
799 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
801 /* Get/set a process' ability to use the timestamp counter instruction */
802 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
803 #define SET_TSC_CTL(val) set_tsc_mode((val))
805 extern int get_tsc_mode(unsigned long adr);
806 extern int set_tsc_mode(unsigned int val);
808 /* Register/unregister a process' MPX related resource */
809 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
810 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
812 #ifdef CONFIG_X86_INTEL_MPX
813 extern int mpx_enable_management(void);
814 extern int mpx_disable_management(void);
816 static inline int mpx_enable_management(void)
820 static inline int mpx_disable_management(void)
824 #endif /* CONFIG_X86_INTEL_MPX */
826 extern u16 amd_get_nb_id(int cpu);
827 extern u32 amd_get_nodes_per_socket(void);
829 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
831 uint32_t base, eax, signature[3];
833 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
834 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
836 if (!memcmp(sig, signature, 12) &&
837 (leaves == 0 || ((eax - base) >= leaves)))
844 extern unsigned long arch_align_stack(unsigned long sp);
845 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
847 void default_idle(void);
849 bool xen_set_default_idle(void);
851 #define xen_set_default_idle 0
854 void stop_this_cpu(void *dummy);
855 void df_debug(struct pt_regs *regs, long error_code);
856 #endif /* _ASM_X86_PROCESSOR_H */