arch/x86/include/asm/spinlock.h

   1 #ifndef _ASM_X86_SPINLOCK_H
   2 #define _ASM_X86_SPINLOCK_H
   3
   4 #include <linux/jump_label.h>
   5 #include <linux/atomic.h>
   6 #include <asm/page.h>
   7 #include <asm/processor.h>
   8 #include <linux/compiler.h>
   9 #include <asm/paravirt.h>
  10 #include <asm/bitops.h>
  11
  12 /*
  13  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  14  *
  15  * Simple spin lock operations.  There are two variants, one clears IRQ's
  16  * on the local processor, one does not.
  17  *
  18  * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
  19  *
  20  * (the type definitions are in asm/spinlock_types.h)
  21  */
  22
  23 #ifdef CONFIG_X86_32
  24 # define LOCK_PTR_REG "a"
  25 #else
  26 # define LOCK_PTR_REG "D"
  27 #endif
  28
  29 #if defined(CONFIG_X86_32) && \
  30         (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
  31 /*
  32  * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
  33  * (PPro errata 66, 92)
  34  */
  35 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
  36 #else
  37 # define UNLOCK_LOCK_PREFIX
  38 #endif
  39
  40 /* How long a lock should spin before we consider blocking */
  41 #define SPIN_THRESHOLD  (1 << 15)
  42
  43 extern struct static_key paravirt_ticketlocks_enabled;
  44 static __always_inline bool static_key_false(struct static_key *key);
  45
  46 #ifdef CONFIG_PARAVIRT_SPINLOCKS
  47
  48 static inline void __ticket_enter_slowpath(arch_spinlock_t *lock)
  49 {
  50         set_bit(0, (volatile unsigned long *)&lock->tickets.tail);
  51 }
  52
  53 #else  /* !CONFIG_PARAVIRT_SPINLOCKS */
  54 static __always_inline void __ticket_lock_spinning(arch_spinlock_t *lock,
  55                                                         __ticket_t ticket)
  56 {
  57 }
  58 static inline void __ticket_unlock_kick(arch_spinlock_t *lock,
  59                                                         __ticket_t ticket)
  60 {
  61 }
  62
  63 #endif /* CONFIG_PARAVIRT_SPINLOCKS */
  64
  65 /*
  66  * Ticket locks are conceptually two parts, one indicating the current head of
  67  * the queue, and the other indicating the current tail. The lock is acquired
  68  * by atomically noting the tail and incrementing it by one (thus adding
  69  * ourself to the queue and noting our position), then waiting until the head
  70  * becomes equal to the the initial value of the tail.
  71  *
  72  * We use an xadd covering *both* parts of the lock, to increment the tail and
  73  * also load the position of the head, which takes care of memory ordering
  74  * issues and should be optimal for the uncontended case. Note the tail must be
  75  * in the high part, because a wide xadd increment of the low part would carry
  76  * up and contaminate the high part.
  77  */
  78 static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
  79 {
  80         register struct __raw_tickets inc = { .tail = TICKET_LOCK_INC };
  81
  82         inc = xadd(&lock->tickets, inc);
  83         if (likely(inc.head == inc.tail))
  84                 goto out;
  85
  86         inc.tail &= ~TICKET_SLOWPATH_FLAG;
  87         for (;;) {
  88                 unsigned count = SPIN_THRESHOLD;
  89
  90                 do {
  91                         if (ACCESS_ONCE(lock->tickets.head) == inc.tail)
  92                                 goto out;
  93                         cpu_relax();
  94                 } while (--count);
  95                 __ticket_lock_spinning(lock, inc.tail);
  96         }
  97 out:    barrier();      /* make sure nothing creeps before the lock is taken */
  98 }
  99
 100 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
 101 {
 102         arch_spinlock_t old, new;
 103
 104         old.tickets = ACCESS_ONCE(lock->tickets);
 105         if (old.tickets.head != (old.tickets.tail & ~TICKET_SLOWPATH_FLAG))
 106                 return 0;
 107
 108         new.head_tail = old.head_tail + (TICKET_LOCK_INC << TICKET_SHIFT);
 109
 110         /* cmpxchg is a full barrier, so nothing can move before it */
 111         return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail;
 112 }
 113
 114 static inline void __ticket_unlock_slowpath(arch_spinlock_t *lock,
 115                                             arch_spinlock_t old)
 116 {
 117         arch_spinlock_t new;
 118
 119         BUILD_BUG_ON(((__ticket_t)NR_CPUS) != NR_CPUS);
 120
 121         /* Perform the unlock on the "before" copy */
 122         old.tickets.head += TICKET_LOCK_INC;
 123
 124         /* Clear the slowpath flag */
 125         new.head_tail = old.head_tail & ~(TICKET_SLOWPATH_FLAG << TICKET_SHIFT);
 126
 127         /*
 128          * If the lock is uncontended, clear the flag - use cmpxchg in
 129          * case it changes behind our back though.
 130          */
 131         if (new.tickets.head != new.tickets.tail ||
 132             cmpxchg(&lock->head_tail, old.head_tail,
 133                                         new.head_tail) != old.head_tail) {
 134                 /*
 135                  * Lock still has someone queued for it, so wake up an
 136                  * appropriate waiter.
 137                  */
 138                 __ticket_unlock_kick(lock, old.tickets.head);
 139         }
 140 }
 141
 142 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
 143 {
 144         if (TICKET_SLOWPATH_FLAG &&
 145             static_key_false(&paravirt_ticketlocks_enabled)) {
 146                 arch_spinlock_t prev;
 147
 148                 prev = *lock;
 149                 add_smp(&lock->tickets.head, TICKET_LOCK_INC);
 150
 151                 /* add_smp() is a full mb() */
 152
 153                 if (unlikely(lock->tickets.tail & TICKET_SLOWPATH_FLAG))
 154                         __ticket_unlock_slowpath(lock, prev);
 155         } else
 156                 __add(&lock->tickets.head, TICKET_LOCK_INC, UNLOCK_LOCK_PREFIX);
 157 }
 158
 159 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 160 {
 161         struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
 162
 163         return tmp.tail != tmp.head;
 164 }
 165
 166 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 167 {
 168         struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
 169
 170         return (__ticket_t)(tmp.tail - tmp.head) > TICKET_LOCK_INC;
 171 }
 172 #define arch_spin_is_contended  arch_spin_is_contended
 173
 174 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
 175                                                   unsigned long flags)
 176 {
 177         arch_spin_lock(lock);
 178 }
 179
 180 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 181 {
 182         while (arch_spin_is_locked(lock))
 183                 cpu_relax();
 184 }
 185
 186 /*
 187  * Read-write spinlocks, allowing multiple readers
 188  * but only one writer.
 189  *
 190  * NOTE! it is quite common to have readers in interrupts
 191  * but no interrupt writers. For those circumstances we
 192  * can "mix" irq-safe locks - any writer needs to get a
 193  * irq-safe write-lock, but readers can get non-irqsafe
 194  * read-locks.
 195  *
 196  * On x86, we implement read-write locks as a 32-bit counter
 197  * with the high bit (sign) being the "contended" bit.
 198  */
 199
 200 /**
 201  * read_can_lock - would read_trylock() succeed?
 202  * @lock: the rwlock in question.
 203  */
 204 static inline int arch_read_can_lock(arch_rwlock_t *lock)
 205 {
 206         return lock->lock > 0;
 207 }
 208
 209 /**
 210  * write_can_lock - would write_trylock() succeed?
 211  * @lock: the rwlock in question.
 212  */
 213 static inline int arch_write_can_lock(arch_rwlock_t *lock)
 214 {
 215         return lock->write == WRITE_LOCK_CMP;
 216 }
 217
 218 static inline void arch_read_lock(arch_rwlock_t *rw)
 219 {
 220         asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
 221                      "jns 1f\n"
 222                      "call __read_lock_failed\n\t"
 223                      "1:\n"
 224                      ::LOCK_PTR_REG (rw) : "memory");
 225 }
 226
 227 static inline void arch_write_lock(arch_rwlock_t *rw)
 228 {
 229         asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
 230                      "jz 1f\n"
 231                      "call __write_lock_failed\n\t"
 232                      "1:\n"
 233                      ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
 234                      : "memory");
 235 }
 236
 237 static inline int arch_read_trylock(arch_rwlock_t *lock)
 238 {
 239         READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
 240
 241         if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
 242                 return 1;
 243         READ_LOCK_ATOMIC(inc)(count);
 244         return 0;
 245 }
 246
 247 static inline int arch_write_trylock(arch_rwlock_t *lock)
 248 {
 249         atomic_t *count = (atomic_t *)&lock->write;
 250
 251         if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
 252                 return 1;
 253         atomic_add(WRITE_LOCK_CMP, count);
 254         return 0;
 255 }
 256
 257 static inline void arch_read_unlock(arch_rwlock_t *rw)
 258 {
 259         asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
 260                      :"+m" (rw->lock) : : "memory");
 261 }
 262
 263 static inline void arch_write_unlock(arch_rwlock_t *rw)
 264 {
 265         asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
 266                      : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
 267 }
 268
 269 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 270 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 271
 272 #undef READ_LOCK_SIZE
 273 #undef READ_LOCK_ATOMIC
 274 #undef WRITE_LOCK_ADD
 275 #undef WRITE_LOCK_SUB
 276 #undef WRITE_LOCK_CMP
 277
 278 #define arch_spin_relax(lock)   cpu_relax()
 279 #define arch_read_relax(lock)   cpu_relax()
 280 #define arch_write_relax(lock)  cpu_relax()
 281
 282 /* The {read|write|spin}_lock() on x86 are full memory barriers. */
 283 static inline void smp_mb__after_lock(void) { }
 284 #define ARCH_HAS_SMP_MB_AFTER_LOCK
 285
 286 #endif /* _ASM_X86_SPINLOCK_H */