2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
15 #include <linux/numa.h>
16 #include <linux/percpu.h>
17 #include <linux/timer.h>
19 #include <asm/types.h>
20 #include <asm/percpu.h>
21 #include <asm/uv/uv_mmrs.h>
22 #include <asm/irq_vectors.h>
23 #include <asm/io_apic.h>
27 * Addressing Terminology
29 * M - The low M bits of a physical address represent the offset
30 * into the blade local memory. RAM memory on a blade is physically
31 * contiguous (although various IO spaces may punch holes in
34 * N - Number of bits in the node portion of a socket physical
37 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
38 * routers always have low bit of 1, C/MBricks have low bit
39 * equal to 0. Most addressing macros that target UV hub chips
40 * right shift the NASID by 1 to exclude the always-zero bit.
41 * NASIDs contain up to 15 bits.
43 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
46 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
47 * of the nasid for socket usage.
50 * NumaLink Global Physical Address Format:
51 * +--------------------------------+---------------------+
52 * |00..000| GNODE | NodeOffset |
53 * +--------------------------------+---------------------+
54 * |<-------53 - M bits --->|<--------M bits ----->
56 * M - number of node offset bits (35 .. 40)
59 * Memory/UV-HUB Processor Socket Address Format:
60 * +----------------+---------------+---------------------+
61 * |00..000000000000| PNODE | NodeOffset |
62 * +----------------+---------------+---------------------+
63 * <--- N bits --->|<--------M bits ----->
65 * M - number of node offset bits (35 .. 40)
66 * N - number of PNODE bits (0 .. 10)
68 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
69 * The actual values are configuration dependent and are set at
70 * boot time. M & N values are set by the hardware/BIOS at boot.
74 * NOTE!!!!!! This is the current format of the APICID. However, code
75 * should assume that this will change in the future. Use functions
76 * in this file for all APICID bit manipulations and conversion.
84 * l = socket number on board
87 * s = bits that are in the SOCKET_ID CSR
89 * Note: Processor only supports 12 bits in the APICID register. The ACPI
90 * tables hold all 16 bits. Software needs to be aware of this.
92 * Unless otherwise specified, all references to APICID refer to
93 * the FULL value contained in ACPI tables, not the subset in the
94 * processor APICID register.
99 * Maximum number of bricks in all partitions and in all coherency domains.
100 * This is the total number of bricks accessible in the numalink fabric. It
101 * includes all C & M bricks. Routers are NOT included.
103 * This value is also the value of the maximum number of non-router NASIDs
104 * in the numalink fabric.
106 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
108 #define UV_MAX_NUMALINK_BLADES 16384
111 * Maximum number of C/Mbricks within a software SSI (hardware may support
114 #define UV_MAX_SSI_BLADES 256
117 * The largest possible NASID of a C or M brick (+ 2)
119 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
122 struct timer_list timer;
123 unsigned long offset;
125 unsigned long idle_on;
126 unsigned long idle_off;
128 unsigned char enabled;
132 * The following defines attributes of the HUB chip. These attributes are
133 * frequently referenced and are kept in the per-cpu data areas of each cpu.
134 * They are kept together in a struct to minimize cache misses.
136 struct uv_hub_info_s {
137 unsigned long global_mmr_base;
138 unsigned long gpa_mask;
139 unsigned int gnode_extra;
140 unsigned long gnode_upper;
141 unsigned long lowmem_remap_top;
142 unsigned long lowmem_remap_base;
143 unsigned short pnode;
144 unsigned short pnode_mask;
145 unsigned short coherency_domain_number;
146 unsigned short numa_blade_id;
147 unsigned char blade_processor_id;
150 struct uv_scir_s scir;
153 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
154 #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
155 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
158 * Local & Global MMR space macros.
159 * Note: macros are intended to be used ONLY by inline functions
160 * in this file - not by other kernel code.
161 * n - NASID (full 15-bit global nasid)
162 * g - GNODE (full 15-bit global nasid, right shifted 1)
163 * p - PNODE (local part of nsids, right shifted 1)
165 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
166 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
167 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
169 #define UV_LOCAL_MMR_BASE 0xf4000000UL
170 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL
171 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
172 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
173 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
175 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
176 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26
178 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
180 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
181 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
183 #define UV_APIC_PNODE_SHIFT 6
185 /* Local Bus from cpu's perspective */
186 #define LOCAL_BUS_BASE 0x1c00000
187 #define LOCAL_BUS_SIZE (4 * 1024 * 1024)
190 * System Controller Interface Reg
192 * Note there are NO leds on a UV system. This register is only
193 * used by the system controller to monitor system-wide operation.
194 * There are 64 regs per node. With Nahelem cpus (2 cores per node,
195 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
198 * The window is located at top of ACPI MMR space
200 #define SCIR_WINDOW_COUNT 64
201 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
205 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
206 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */
207 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
209 /* Loop through all installed blades */
210 #define for_each_possible_blade(bid) \
211 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
214 * Macros for converting between kernel virtual addresses, socket local physical
215 * addresses, and UV global physical addresses.
216 * Note: use the standard __pa() & __va() macros for converting
217 * between socket virtual and socket physical addresses.
220 /* socket phys RAM --> UV global physical address */
221 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
223 if (paddr < uv_hub_info->lowmem_remap_top)
224 paddr |= uv_hub_info->lowmem_remap_base;
225 return paddr | uv_hub_info->gnode_upper;
229 /* socket virtual --> UV global physical address */
230 static inline unsigned long uv_gpa(void *v)
232 return uv_soc_phys_ram_to_gpa(__pa(v));
235 /* UV global physical address --> socket phys RAM */
236 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
238 unsigned long paddr = gpa & uv_hub_info->gpa_mask;
239 unsigned long remap_base = uv_hub_info->lowmem_remap_base;
240 unsigned long remap_top = uv_hub_info->lowmem_remap_top;
242 if (paddr >= remap_base && paddr < remap_base + remap_top)
249 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
251 return gpa >> uv_hub_info->m_val;
255 static inline int uv_gpa_to_pnode(unsigned long gpa)
257 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
259 return uv_gpa_to_gnode(gpa) & n_mask;
262 /* pnode, offset --> socket virtual */
263 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
265 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
270 * Extract a PNODE from an APICID (full apicid, not processor subset)
272 static inline int uv_apicid_to_pnode(int apicid)
274 return (apicid >> UV_APIC_PNODE_SHIFT);
278 * Access global MMRs using the low memory MMR32 space. This region supports
279 * faster MMR access but not all MMRs are accessible in this space.
281 static inline unsigned long *uv_global_mmr32_address(int pnode,
282 unsigned long offset)
284 return __va(UV_GLOBAL_MMR32_BASE |
285 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
288 static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
291 writeq(val, uv_global_mmr32_address(pnode, offset));
294 static inline unsigned long uv_read_global_mmr32(int pnode,
295 unsigned long offset)
297 return readq(uv_global_mmr32_address(pnode, offset));
301 * Access Global MMR space using the MMR space located at the top of physical
304 static inline unsigned long *uv_global_mmr64_address(int pnode,
305 unsigned long offset)
307 return __va(UV_GLOBAL_MMR64_BASE |
308 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
311 static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
314 writeq(val, uv_global_mmr64_address(pnode, offset));
317 static inline unsigned long uv_read_global_mmr64(int pnode,
318 unsigned long offset)
320 return readq(uv_global_mmr64_address(pnode, offset));
324 * Access hub local MMRs. Faster than using global space but only local MMRs
327 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
329 return __va(UV_LOCAL_MMR_BASE | offset);
332 static inline unsigned long uv_read_local_mmr(unsigned long offset)
334 return readq(uv_local_mmr_address(offset));
337 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
339 writeq(val, uv_local_mmr_address(offset));
342 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
344 return readb(uv_local_mmr_address(offset));
347 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
349 writeb(val, uv_local_mmr_address(offset));
353 * Structures and definitions for converting between cpu, node, pnode, and blade
356 struct uv_blade_info {
357 unsigned short nr_possible_cpus;
358 unsigned short nr_online_cpus;
359 unsigned short pnode;
362 extern struct uv_blade_info *uv_blade_info;
363 extern short *uv_node_to_blade;
364 extern short *uv_cpu_to_blade;
365 extern short uv_possible_blades;
367 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
368 static inline int uv_blade_processor_id(void)
370 return uv_hub_info->blade_processor_id;
373 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
374 static inline int uv_numa_blade_id(void)
376 return uv_hub_info->numa_blade_id;
379 /* Convert a cpu number to the the UV blade number */
380 static inline int uv_cpu_to_blade_id(int cpu)
382 return uv_cpu_to_blade[cpu];
385 /* Convert linux node number to the UV blade number */
386 static inline int uv_node_to_blade_id(int nid)
388 return uv_node_to_blade[nid];
391 /* Convert a blade id to the PNODE of the blade */
392 static inline int uv_blade_to_pnode(int bid)
394 return uv_blade_info[bid].pnode;
397 /* Nid of memory node on blade. -1 if no blade-local memory */
398 static inline int uv_blade_to_memory_nid(int bid)
400 return uv_blade_info[bid].memory_nid;
403 /* Determine the number of possible cpus on a blade */
404 static inline int uv_blade_nr_possible_cpus(int bid)
406 return uv_blade_info[bid].nr_possible_cpus;
409 /* Determine the number of online cpus on a blade */
410 static inline int uv_blade_nr_online_cpus(int bid)
412 return uv_blade_info[bid].nr_online_cpus;
415 /* Convert a cpu id to the PNODE of the blade containing the cpu */
416 static inline int uv_cpu_to_pnode(int cpu)
418 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
421 /* Convert a linux node number to the PNODE of the blade */
422 static inline int uv_node_to_pnode(int nid)
424 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
427 /* Maximum possible number of blades */
428 static inline int uv_num_possible_blades(void)
430 return uv_possible_blades;
433 /* Update SCIR state */
434 static inline void uv_set_scir_bits(unsigned char value)
436 if (uv_hub_info->scir.state != value) {
437 uv_hub_info->scir.state = value;
438 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
442 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
444 if (uv_cpu_hub_info(cpu)->scir.state != value) {
445 uv_cpu_hub_info(cpu)->scir.state = value;
446 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
450 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
453 unsigned long dmode = dest_Fixed;
455 if (vector == NMI_VECTOR)
458 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
459 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
460 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
461 (vector << UVH_IPI_INT_VECTOR_SHFT);
462 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
465 #endif /* CONFIG_X86_64 */
466 #endif /* _ASM_X86_UV_UV_HUB_H */