arch/x86/include/asm/uv/uv_mmrs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV MMR definitions
   7  *
   8  * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #ifndef _ASM_X86_UV_UV_MMRS_H
  12 #define _ASM_X86_UV_UV_MMRS_H
  13
  14 /*
  15  * This file contains MMR definitions for all UV hubs types.
  16  *
  17  * To minimize coding differences between hub types, the symbols are
  18  * grouped by architecture types.
  19  *
  20  * UVH  - definitions common to all UV hub types.
  21  * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3).
  22  * UV1H - definitions specific to UV type 1 hub.
  23  * UV2H - definitions specific to UV type 2 hub.
  24  * UV3H - definitions specific to UV type 3 hub.
  25  *
  26  * So in general, MMR addresses and structures are identical on all hubs types.
  27  * These MMRs are identified as:
  28  *      #define UVH_xxx         <address>
  29  *      union uvh_xxx {
  30  *              unsigned long       v;
  31  *              struct uvh_int_cmpd_s {
  32  *              } s;
  33  *      };
  34  *
  35  * If the MMR exists on all hub types but have different addresses:
  36  *      #define UV1Hxxx a
  37  *      #define UV2Hxxx b
  38  *      #define UV3Hxxx c
  39  *      #define UVHxxx  (is_uv1_hub() ? UV1Hxxx :
  40  *                      (is_uv2_hub() ? UV2Hxxx :
  41  *                                      UV3Hxxx))
  42  *
  43  * If the MMR exists on all hub types > 1 but have different addresses:
  44  *      #define UV2Hxxx b
  45  *      #define UV3Hxxx c
  46  *      #define UVXHxxx (is_uv2_hub() ? UV2Hxxx :
  47  *                                      UV3Hxxx))
  48  *
  49  *      union uvh_xxx {
  50  *              unsigned long       v;
  51  *              struct uvh_xxx_s {       # Common fields only
  52  *              } s;
  53  *              struct uv1h_xxx_s {      # Full UV1 definition (*)
  54  *              } s1;
  55  *              struct uv2h_xxx_s {      # Full UV2 definition (*)
  56  *              } s2;
  57  *              struct uv3h_xxx_s {      # Full UV3 definition (*)
  58  *              } s3;
  59  *      };
  60  *              (* - if present and different than the common struct)
  61  *
  62  * Only essential differences are enumerated. For example, if the address is
  63  * the same for all UV's, only a single #define is generated. Likewise,
  64  * if the contents is the same for all hubs, only the "s" structure is
  65  * generated.
  66  *
  67  * If the MMR exists on ONLY 1 type of hub, no generic definition is
  68  * generated:
  69  *      #define UVnH_xxx        <uvn address>
  70  *      union uvnh_xxx {
  71  *              unsigned long       v;
  72  *              struct uvh_int_cmpd_s {
  73  *              } sn;
  74  *      };
  75  *
  76  * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH)
  77  */
  78
  79 #define UV_MMR_ENABLE           (1UL << 63)
  80
  81 #define UV1_HUB_PART_NUMBER     0x88a5
  82 #define UV2_HUB_PART_NUMBER     0x8eb8
  83 #define UV2_HUB_PART_NUMBER_X   0x1111
  84 #define UV3_HUB_PART_NUMBER     0x9578
  85 #define UV3_HUB_PART_NUMBER_X   0x4321
  86
  87 /* Compat: Indicate which UV Hubs are supported. */
  88 #define UV2_HUB_IS_SUPPORTED    1
  89 #define UV3_HUB_IS_SUPPORTED    1
  90
  91 /* ========================================================================= */
  92 /*                          UVH_BAU_DATA_BROADCAST                           */
  93 /* ========================================================================= */
  94 #define UVH_BAU_DATA_BROADCAST 0x61688UL
  95 #define UVH_BAU_DATA_BROADCAST_32 0x440
  96
  97 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT              0
  98 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK              0x0000000000000001UL
  99
 100 union uvh_bau_data_broadcast_u {
 101         unsigned long   v;
 102         struct uvh_bau_data_broadcast_s {
 103                 unsigned long   enable:1;                       /* RW */
 104                 unsigned long   rsvd_1_63:63;
 105         } s;
 106 };
 107
 108 /* ========================================================================= */
 109 /*                           UVH_BAU_DATA_CONFIG                             */
 110 /* ========================================================================= */
 111 #define UVH_BAU_DATA_CONFIG 0x61680UL
 112 #define UVH_BAU_DATA_CONFIG_32 0x438
 113
 114 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT                 0
 115 #define UVH_BAU_DATA_CONFIG_DM_SHFT                     8
 116 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT               11
 117 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT                 12
 118 #define UVH_BAU_DATA_CONFIG_P_SHFT                      13
 119 #define UVH_BAU_DATA_CONFIG_T_SHFT                      15
 120 #define UVH_BAU_DATA_CONFIG_M_SHFT                      16
 121 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT                32
 122 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK                 0x00000000000000ffUL
 123 #define UVH_BAU_DATA_CONFIG_DM_MASK                     0x0000000000000700UL
 124 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK               0x0000000000000800UL
 125 #define UVH_BAU_DATA_CONFIG_STATUS_MASK                 0x0000000000001000UL
 126 #define UVH_BAU_DATA_CONFIG_P_MASK                      0x0000000000002000UL
 127 #define UVH_BAU_DATA_CONFIG_T_MASK                      0x0000000000008000UL
 128 #define UVH_BAU_DATA_CONFIG_M_MASK                      0x0000000000010000UL
 129 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
 130
 131 union uvh_bau_data_config_u {
 132         unsigned long   v;
 133         struct uvh_bau_data_config_s {
 134                 unsigned long   vector_:8;                      /* RW */
 135                 unsigned long   dm:3;                           /* RW */
 136                 unsigned long   destmode:1;                     /* RW */
 137                 unsigned long   status:1;                       /* RO */
 138                 unsigned long   p:1;                            /* RO */
 139                 unsigned long   rsvd_14:1;
 140                 unsigned long   t:1;                            /* RO */
 141                 unsigned long   m:1;                            /* RW */
 142                 unsigned long   rsvd_17_31:15;
 143                 unsigned long   apic_id:32;                     /* RW */
 144         } s;
 145 };
 146
 147 /* ========================================================================= */
 148 /*                           UVH_EVENT_OCCURRED0                             */
 149 /* ========================================================================= */
 150 #define UVH_EVENT_OCCURRED0 0x70000UL
 151 #define UVH_EVENT_OCCURRED0_32 0x5e8
 152
 153 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT               0
 154 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT              11
 155 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK               0x0000000000000001UL
 156 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK              0x0000000000000800UL
 157
 158 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT             1
 159 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT             2
 160 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT              3
 161 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT              4
 162 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT              5
 163 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT              6
 164 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT             7
 165 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT            8
 166 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT            9
 167 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT             10
 168 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT             12
 169 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT             13
 170 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT             14
 171 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            15
 172 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            16
 173 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT             17
 174 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT             18
 175 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT             19
 176 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT             20
 177 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT            21
 178 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   22
 179 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          23
 180 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          24
 181 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          25
 182 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          26
 183 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          27
 184 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          28
 185 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          29
 186 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          30
 187 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          31
 188 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          32
 189 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         33
 190 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         34
 191 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         35
 192 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         36
 193 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         37
 194 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         38
 195 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            39
 196 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            40
 197 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            41
 198 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            42
 199 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT               43
 200 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        44
 201 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT               45
 202 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            46
 203 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            47
 204 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            48
 205 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            49
 206 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT           50
 207 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT                  51
 208 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT                  52
 209 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT                  53
 210 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT                  54
 211 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT              55
 212 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT  56
 213 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000002UL
 214 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000004UL
 215 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK              0x0000000000000008UL
 216 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000010UL
 217 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK              0x0000000000000020UL
 218 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK              0x0000000000000040UL
 219 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000080UL
 220 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000000100UL
 221 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000000200UL
 222 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK             0x0000000000000400UL
 223 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK             0x0000000000001000UL
 224 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK             0x0000000000002000UL
 225 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000004000UL
 226 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000000008000UL
 227 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000000010000UL
 228 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK             0x0000000000020000UL
 229 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000040000UL
 230 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK             0x0000000000080000UL
 231 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK             0x0000000000100000UL
 232 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK            0x0000000000200000UL
 233 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000000400000UL
 234 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000000800000UL
 235 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000001000000UL
 236 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000002000000UL
 237 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000004000000UL
 238 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000000008000000UL
 239 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000000010000000UL
 240 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000000020000000UL
 241 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000000040000000UL
 242 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000000080000000UL
 243 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000000100000000UL
 244 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000000200000000UL
 245 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000000400000000UL
 246 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000000800000000UL
 247 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000001000000000UL
 248 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000002000000000UL
 249 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000004000000000UL
 250 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0000008000000000UL
 251 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0000010000000000UL
 252 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0000020000000000UL
 253 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0000040000000000UL
 254 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK               0x0000080000000000UL
 255 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0000100000000000UL
 256 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK               0x0000200000000000UL
 257 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0000400000000000UL
 258 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0000800000000000UL
 259 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0001000000000000UL
 260 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0002000000000000UL
 261 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0004000000000000UL
 262 #define UV1H_EVENT_OCCURRED0_RTC0_MASK                  0x0008000000000000UL
 263 #define UV1H_EVENT_OCCURRED0_RTC1_MASK                  0x0010000000000000UL
 264 #define UV1H_EVENT_OCCURRED0_RTC2_MASK                  0x0020000000000000UL
 265 #define UV1H_EVENT_OCCURRED0_RTC3_MASK                  0x0040000000000000UL
 266 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK              0x0080000000000000UL
 267 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK  0x0100000000000000UL
 268
 269 #define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT              1
 270 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT              2
 271 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT             3
 272 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT             4
 273 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT             5
 274 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT             6
 275 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT             7
 276 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT             8
 277 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT             9
 278 #define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
 279 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT            12
 280 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT            13
 281 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT            14
 282 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT            15
 283 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT             16
 284 #define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
 285 #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
 286 #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
 287 #define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
 288 #define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
 289 #define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
 290 #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
 291 #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
 292 #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
 293 #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
 294 #define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
 295 #define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
 296 #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
 297 #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
 298 #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
 299 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
 300 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
 301 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
 302 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
 303 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
 304 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
 305 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
 306 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
 307 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
 308 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
 309 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
 310 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
 311 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
 312 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
 313 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
 314 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
 315 #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
 316 #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
 317 #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
 318 #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
 319 #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
 320 #define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT               53
 321 #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
 322 #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
 323 #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
 324 #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
 325 #define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
 326 #define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
 327 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000004UL
 328 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK             0x0000000000000008UL
 329 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK             0x0000000000000010UL
 330 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000020UL
 331 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000040UL
 332 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK             0x0000000000000080UL
 333 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK             0x0000000000000100UL
 334 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000200UL
 335 #define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
 336 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK            0x0000000000001000UL
 337 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK            0x0000000000002000UL
 338 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000004000UL
 339 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000008000UL
 340 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK             0x0000000000010000UL
 341 #define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
 342 #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
 343 #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
 344 #define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
 345 #define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
 346 #define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
 347 #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
 348 #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
 349 #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
 350 #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
 351 #define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
 352 #define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
 353 #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
 354 #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
 355 #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
 356 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
 357 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
 358 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
 359 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
 360 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
 361 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
 362 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
 363 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
 364 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
 365 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
 366 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
 367 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
 368 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
 369 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
 370 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
 371 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
 372 #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
 373 #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
 374 #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
 375 #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
 376 #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
 377 #define UVXH_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
 378 #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
 379 #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
 380 #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
 381 #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
 382 #define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
 383
 384 union uvh_event_occurred0_u {
 385         unsigned long   v;
 386         struct uvh_event_occurred0_s {
 387                 unsigned long   lb_hcerr:1;                     /* RW, W1C */
 388                 unsigned long   rsvd_1_10:10;
 389                 unsigned long   rh_aoerr0:1;                    /* RW, W1C */
 390                 unsigned long   rsvd_12_63:52;
 391         } s;
 392         struct uvxh_event_occurred0_s {
 393                 unsigned long   lb_hcerr:1;                     /* RW */
 394                 unsigned long   qp_hcerr:1;                     /* RW */
 395                 unsigned long   rh_hcerr:1;                     /* RW */
 396                 unsigned long   lh0_hcerr:1;                    /* RW */
 397                 unsigned long   lh1_hcerr:1;                    /* RW */
 398                 unsigned long   gr0_hcerr:1;                    /* RW */
 399                 unsigned long   gr1_hcerr:1;                    /* RW */
 400                 unsigned long   ni0_hcerr:1;                    /* RW */
 401                 unsigned long   ni1_hcerr:1;                    /* RW */
 402                 unsigned long   lb_aoerr0:1;                    /* RW */
 403                 unsigned long   qp_aoerr0:1;                    /* RW */
 404                 unsigned long   rh_aoerr0:1;                    /* RW */
 405                 unsigned long   lh0_aoerr0:1;                   /* RW */
 406                 unsigned long   lh1_aoerr0:1;                   /* RW */
 407                 unsigned long   gr0_aoerr0:1;                   /* RW */
 408                 unsigned long   gr1_aoerr0:1;                   /* RW */
 409                 unsigned long   xb_aoerr0:1;                    /* RW */
 410                 unsigned long   rt_aoerr0:1;                    /* RW */
 411                 unsigned long   ni0_aoerr0:1;                   /* RW */
 412                 unsigned long   ni1_aoerr0:1;                   /* RW */
 413                 unsigned long   lb_aoerr1:1;                    /* RW */
 414                 unsigned long   qp_aoerr1:1;                    /* RW */
 415                 unsigned long   rh_aoerr1:1;                    /* RW */
 416                 unsigned long   lh0_aoerr1:1;                   /* RW */
 417                 unsigned long   lh1_aoerr1:1;                   /* RW */
 418                 unsigned long   gr0_aoerr1:1;                   /* RW */
 419                 unsigned long   gr1_aoerr1:1;                   /* RW */
 420                 unsigned long   xb_aoerr1:1;                    /* RW */
 421                 unsigned long   rt_aoerr1:1;                    /* RW */
 422                 unsigned long   ni0_aoerr1:1;                   /* RW */
 423                 unsigned long   ni1_aoerr1:1;                   /* RW */
 424                 unsigned long   system_shutdown_int:1;          /* RW */
 425                 unsigned long   lb_irq_int_0:1;                 /* RW */
 426                 unsigned long   lb_irq_int_1:1;                 /* RW */
 427                 unsigned long   lb_irq_int_2:1;                 /* RW */
 428                 unsigned long   lb_irq_int_3:1;                 /* RW */
 429                 unsigned long   lb_irq_int_4:1;                 /* RW */
 430                 unsigned long   lb_irq_int_5:1;                 /* RW */
 431                 unsigned long   lb_irq_int_6:1;                 /* RW */
 432                 unsigned long   lb_irq_int_7:1;                 /* RW */
 433                 unsigned long   lb_irq_int_8:1;                 /* RW */
 434                 unsigned long   lb_irq_int_9:1;                 /* RW */
 435                 unsigned long   lb_irq_int_10:1;                /* RW */
 436                 unsigned long   lb_irq_int_11:1;                /* RW */
 437                 unsigned long   lb_irq_int_12:1;                /* RW */
 438                 unsigned long   lb_irq_int_13:1;                /* RW */
 439                 unsigned long   lb_irq_int_14:1;                /* RW */
 440                 unsigned long   lb_irq_int_15:1;                /* RW */
 441                 unsigned long   l1_nmi_int:1;                   /* RW */
 442                 unsigned long   stop_clock:1;                   /* RW */
 443                 unsigned long   asic_to_l1:1;                   /* RW */
 444                 unsigned long   l1_to_asic:1;                   /* RW */
 445                 unsigned long   la_seq_trigger:1;               /* RW */
 446                 unsigned long   ipi_int:1;                      /* RW */
 447                 unsigned long   extio_int0:1;                   /* RW */
 448                 unsigned long   extio_int1:1;                   /* RW */
 449                 unsigned long   extio_int2:1;                   /* RW */
 450                 unsigned long   extio_int3:1;                   /* RW */
 451                 unsigned long   profile_int:1;                  /* RW */
 452                 unsigned long   rsvd_59_63:5;
 453         } sx;
 454 };
 455
 456 /* ========================================================================= */
 457 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
 458 /* ========================================================================= */
 459 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
 460 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
 461
 462
 463 /* ========================================================================= */
 464 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
 465 /* ========================================================================= */
 466 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
 467
 468 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT             0
 469 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT                 8
 470 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT           11
 471 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT             12
 472 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT                  13
 473 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT                  15
 474 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT                  16
 475 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT            32
 476 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
 477 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
 478 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
 479 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
 480 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
 481 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
 482 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
 483 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 484
 485 union uvh_gr0_tlb_int0_config_u {
 486         unsigned long   v;
 487         struct uvh_gr0_tlb_int0_config_s {
 488                 unsigned long   vector_:8;                      /* RW */
 489                 unsigned long   dm:3;                           /* RW */
 490                 unsigned long   destmode:1;                     /* RW */
 491                 unsigned long   status:1;                       /* RO */
 492                 unsigned long   p:1;                            /* RO */
 493                 unsigned long   rsvd_14:1;
 494                 unsigned long   t:1;                            /* RO */
 495                 unsigned long   m:1;                            /* RW */
 496                 unsigned long   rsvd_17_31:15;
 497                 unsigned long   apic_id:32;                     /* RW */
 498         } s;
 499 };
 500
 501 /* ========================================================================= */
 502 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
 503 /* ========================================================================= */
 504 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
 505
 506 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT             0
 507 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT                 8
 508 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT           11
 509 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT             12
 510 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT                  13
 511 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT                  15
 512 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT                  16
 513 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT            32
 514 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
 515 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
 516 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
 517 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
 518 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
 519 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
 520 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
 521 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 522
 523 union uvh_gr0_tlb_int1_config_u {
 524         unsigned long   v;
 525         struct uvh_gr0_tlb_int1_config_s {
 526                 unsigned long   vector_:8;                      /* RW */
 527                 unsigned long   dm:3;                           /* RW */
 528                 unsigned long   destmode:1;                     /* RW */
 529                 unsigned long   status:1;                       /* RO */
 530                 unsigned long   p:1;                            /* RO */
 531                 unsigned long   rsvd_14:1;
 532                 unsigned long   t:1;                            /* RO */
 533                 unsigned long   m:1;                            /* RW */
 534                 unsigned long   rsvd_17_31:15;
 535                 unsigned long   apic_id:32;                     /* RW */
 536         } s;
 537 };
 538
 539 /* ========================================================================= */
 540 /*                         UVH_GR0_TLB_MMR_CONTROL                           */
 541 /* ========================================================================= */
 542 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
 543 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
 544 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
 545 #define UVH_GR0_TLB_MMR_CONTROL                                         \
 546                 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :              \
 547                 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :              \
 548                                 UV3H_GR0_TLB_MMR_CONTROL))
 549
 550 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT              0
 551 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
 552 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
 553 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
 554 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
 555 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT           31
 556 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
 557 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
 558 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
 559 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
 560 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
 561 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
 562
 563 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 564 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 565 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 566 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 567 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 568 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 569 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
 570 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
 571 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
 572 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
 573 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
 574 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
 575 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 576 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 577 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 578 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 579 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 580 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
 581 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
 582 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
 583 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
 584 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
 585
 586 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 587 #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 588 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 589 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 590 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 591 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 592 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
 593 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
 594 #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 595 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 596 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 597 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 598 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 599 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 600
 601 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 602 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 603 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 604 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 605 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 606 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 607 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
 608 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
 609 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
 610 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
 611 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 612 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 613 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 614 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 615 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 616 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 617 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
 618 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
 619
 620 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
 621 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
 622 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
 623 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
 624 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
 625 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
 626 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
 627 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
 628 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
 629 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
 630 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
 631 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
 632 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
 633 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
 634 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
 635 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
 636
 637 union uvh_gr0_tlb_mmr_control_u {
 638         unsigned long   v;
 639         struct uvh_gr0_tlb_mmr_control_s {
 640                 unsigned long   index:12;                       /* RW */
 641                 unsigned long   mem_sel:2;                      /* RW */
 642                 unsigned long   rsvd_14_15:2;
 643                 unsigned long   auto_valid_en:1;                /* RW */
 644                 unsigned long   rsvd_17_19:3;
 645                 unsigned long   mmr_hash_index_en:1;            /* RW */
 646                 unsigned long   rsvd_21_29:9;
 647                 unsigned long   mmr_write:1;                    /* WP */
 648                 unsigned long   mmr_read:1;                     /* WP */
 649                 unsigned long   rsvd_32_48:17;
 650                 unsigned long   rsvd_49_51:3;
 651                 unsigned long   rsvd_52_63:12;
 652         } s;
 653         struct uv1h_gr0_tlb_mmr_control_s {
 654                 unsigned long   index:12;                       /* RW */
 655                 unsigned long   mem_sel:2;                      /* RW */
 656                 unsigned long   rsvd_14_15:2;
 657                 unsigned long   auto_valid_en:1;                /* RW */
 658                 unsigned long   rsvd_17_19:3;
 659                 unsigned long   mmr_hash_index_en:1;            /* RW */
 660                 unsigned long   rsvd_21_29:9;
 661                 unsigned long   mmr_write:1;                    /* WP */
 662                 unsigned long   mmr_read:1;                     /* WP */
 663                 unsigned long   rsvd_32_47:16;
 664                 unsigned long   mmr_inj_con:1;                  /* RW */
 665                 unsigned long   rsvd_49_51:3;
 666                 unsigned long   mmr_inj_tlbram:1;               /* RW */
 667                 unsigned long   rsvd_53:1;
 668                 unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
 669                 unsigned long   rsvd_55:1;
 670                 unsigned long   mmr_inj_tlbrreg:1;              /* RW */
 671                 unsigned long   rsvd_57_59:3;
 672                 unsigned long   mmr_inj_tlblruv:1;              /* RW */
 673                 unsigned long   rsvd_61_63:3;
 674         } s1;
 675         struct uvxh_gr0_tlb_mmr_control_s {
 676                 unsigned long   index:12;                       /* RW */
 677                 unsigned long   mem_sel:2;                      /* RW */
 678                 unsigned long   rsvd_14_15:2;
 679                 unsigned long   auto_valid_en:1;                /* RW */
 680                 unsigned long   rsvd_17_19:3;
 681                 unsigned long   mmr_hash_index_en:1;            /* RW */
 682                 unsigned long   rsvd_21_29:9;
 683                 unsigned long   mmr_write:1;                    /* WP */
 684                 unsigned long   mmr_read:1;                     /* WP */
 685                 unsigned long   mmr_op_done:1;                  /* RW */
 686                 unsigned long   rsvd_33_47:15;
 687                 unsigned long   rsvd_48:1;
 688                 unsigned long   rsvd_49_51:3;
 689                 unsigned long   rsvd_52:1;
 690                 unsigned long   rsvd_53_63:11;
 691         } sx;
 692         struct uv2h_gr0_tlb_mmr_control_s {
 693                 unsigned long   index:12;                       /* RW */
 694                 unsigned long   mem_sel:2;                      /* RW */
 695                 unsigned long   rsvd_14_15:2;
 696                 unsigned long   auto_valid_en:1;                /* RW */
 697                 unsigned long   rsvd_17_19:3;
 698                 unsigned long   mmr_hash_index_en:1;            /* RW */
 699                 unsigned long   rsvd_21_29:9;
 700                 unsigned long   mmr_write:1;                    /* WP */
 701                 unsigned long   mmr_read:1;                     /* WP */
 702                 unsigned long   mmr_op_done:1;                  /* RW */
 703                 unsigned long   rsvd_33_47:15;
 704                 unsigned long   mmr_inj_con:1;                  /* RW */
 705                 unsigned long   rsvd_49_51:3;
 706                 unsigned long   mmr_inj_tlbram:1;               /* RW */
 707                 unsigned long   rsvd_53_63:11;
 708         } s2;
 709         struct uv3h_gr0_tlb_mmr_control_s {
 710                 unsigned long   index:12;                       /* RW */
 711                 unsigned long   mem_sel:2;                      /* RW */
 712                 unsigned long   rsvd_14_15:2;
 713                 unsigned long   auto_valid_en:1;                /* RW */
 714                 unsigned long   rsvd_17_19:3;
 715                 unsigned long   mmr_hash_index_en:1;            /* RW */
 716                 unsigned long   ecc_sel:1;                      /* RW */
 717                 unsigned long   rsvd_22_29:8;
 718                 unsigned long   mmr_write:1;                    /* WP */
 719                 unsigned long   mmr_read:1;                     /* WP */
 720                 unsigned long   mmr_op_done:1;                  /* RW */
 721                 unsigned long   rsvd_33_47:15;
 722                 unsigned long   undef_48:1;                     /* Undefined */
 723                 unsigned long   rsvd_49_51:3;
 724                 unsigned long   undef_52:1;                     /* Undefined */
 725                 unsigned long   rsvd_53_63:11;
 726         } s3;
 727 };
 728
 729 /* ========================================================================= */
 730 /*                       UVH_GR0_TLB_MMR_READ_DATA_HI                        */
 731 /* ========================================================================= */
 732 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
 733 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
 734 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
 735 #define UVH_GR0_TLB_MMR_READ_DATA_HI                                    \
 736                 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :         \
 737                 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :         \
 738                                 UV3H_GR0_TLB_MMR_READ_DATA_HI))
 739
 740 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
 741 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
 742 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
 743 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
 744 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
 745 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
 746 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
 747 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
 748
 749 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 750 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
 751 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
 752 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
 753 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
 754 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
 755 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
 756 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 757
 758 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 759 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
 760 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
 761 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
 762 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
 763 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
 764 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
 765 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 766
 767 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 768 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
 769 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
 770 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
 771 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
 772 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
 773 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
 774 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 775
 776 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
 777 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
 778 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
 779 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
 780 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       45
 781 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
 782 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
 783 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
 784 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
 785 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
 786 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
 787 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
 788
 789 union uvh_gr0_tlb_mmr_read_data_hi_u {
 790         unsigned long   v;
 791         struct uvh_gr0_tlb_mmr_read_data_hi_s {
 792                 unsigned long   pfn:41;                         /* RO */
 793                 unsigned long   gaa:2;                          /* RO */
 794                 unsigned long   dirty:1;                        /* RO */
 795                 unsigned long   larger:1;                       /* RO */
 796                 unsigned long   rsvd_45_63:19;
 797         } s;
 798         struct uv1h_gr0_tlb_mmr_read_data_hi_s {
 799                 unsigned long   pfn:41;                         /* RO */
 800                 unsigned long   gaa:2;                          /* RO */
 801                 unsigned long   dirty:1;                        /* RO */
 802                 unsigned long   larger:1;                       /* RO */
 803                 unsigned long   rsvd_45_63:19;
 804         } s1;
 805         struct uvxh_gr0_tlb_mmr_read_data_hi_s {
 806                 unsigned long   pfn:41;                         /* RO */
 807                 unsigned long   gaa:2;                          /* RO */
 808                 unsigned long   dirty:1;                        /* RO */
 809                 unsigned long   larger:1;                       /* RO */
 810                 unsigned long   rsvd_45_63:19;
 811         } sx;
 812         struct uv2h_gr0_tlb_mmr_read_data_hi_s {
 813                 unsigned long   pfn:41;                         /* RO */
 814                 unsigned long   gaa:2;                          /* RO */
 815                 unsigned long   dirty:1;                        /* RO */
 816                 unsigned long   larger:1;                       /* RO */
 817                 unsigned long   rsvd_45_63:19;
 818         } s2;
 819         struct uv3h_gr0_tlb_mmr_read_data_hi_s {
 820                 unsigned long   pfn:41;                         /* RO */
 821                 unsigned long   gaa:2;                          /* RO */
 822                 unsigned long   dirty:1;                        /* RO */
 823                 unsigned long   larger:1;                       /* RO */
 824                 unsigned long   aa_ext:1;                       /* RO */
 825                 unsigned long   undef_46_54:9;                  /* Undefined */
 826                 unsigned long   way_ecc:9;                      /* RO */
 827         } s3;
 828 };
 829
 830 /* ========================================================================= */
 831 /*                       UVH_GR0_TLB_MMR_READ_DATA_LO                        */
 832 /* ========================================================================= */
 833 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
 834 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
 835 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
 836 #define UVH_GR0_TLB_MMR_READ_DATA_LO                                    \
 837                 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :         \
 838                 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :         \
 839                                 UV3H_GR0_TLB_MMR_READ_DATA_LO))
 840
 841 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
 842 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
 843 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
 844 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
 845 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
 846 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
 847
 848 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
 849 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
 850 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
 851 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
 852 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
 853 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
 854
 855 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
 856 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
 857 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
 858 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
 859 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
 860 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
 861
 862 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
 863 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
 864 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
 865 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
 866 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
 867 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
 868
 869 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
 870 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
 871 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
 872 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
 873 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
 874 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
 875
 876 union uvh_gr0_tlb_mmr_read_data_lo_u {
 877         unsigned long   v;
 878         struct uvh_gr0_tlb_mmr_read_data_lo_s {
 879                 unsigned long   vpn:39;                         /* RO */
 880                 unsigned long   asid:24;                        /* RO */
 881                 unsigned long   valid:1;                        /* RO */
 882         } s;
 883         struct uv1h_gr0_tlb_mmr_read_data_lo_s {
 884                 unsigned long   vpn:39;                         /* RO */
 885                 unsigned long   asid:24;                        /* RO */
 886                 unsigned long   valid:1;                        /* RO */
 887         } s1;
 888         struct uvxh_gr0_tlb_mmr_read_data_lo_s {
 889                 unsigned long   vpn:39;                         /* RO */
 890                 unsigned long   asid:24;                        /* RO */
 891                 unsigned long   valid:1;                        /* RO */
 892         } sx;
 893         struct uv2h_gr0_tlb_mmr_read_data_lo_s {
 894                 unsigned long   vpn:39;                         /* RO */
 895                 unsigned long   asid:24;                        /* RO */
 896                 unsigned long   valid:1;                        /* RO */
 897         } s2;
 898         struct uv3h_gr0_tlb_mmr_read_data_lo_s {
 899                 unsigned long   vpn:39;                         /* RO */
 900                 unsigned long   asid:24;                        /* RO */
 901                 unsigned long   valid:1;                        /* RO */
 902         } s3;
 903 };
 904
 905 /* ========================================================================= */
 906 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
 907 /* ========================================================================= */
 908 #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
 909
 910 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT             0
 911 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT                 8
 912 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT           11
 913 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT             12
 914 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT                  13
 915 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT                  15
 916 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT                  16
 917 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT            32
 918 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
 919 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
 920 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
 921 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
 922 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
 923 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
 924 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
 925 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 926
 927 union uvh_gr1_tlb_int0_config_u {
 928         unsigned long   v;
 929         struct uvh_gr1_tlb_int0_config_s {
 930                 unsigned long   vector_:8;                      /* RW */
 931                 unsigned long   dm:3;                           /* RW */
 932                 unsigned long   destmode:1;                     /* RW */
 933                 unsigned long   status:1;                       /* RO */
 934                 unsigned long   p:1;                            /* RO */
 935                 unsigned long   rsvd_14:1;
 936                 unsigned long   t:1;                            /* RO */
 937                 unsigned long   m:1;                            /* RW */
 938                 unsigned long   rsvd_17_31:15;
 939                 unsigned long   apic_id:32;                     /* RW */
 940         } s;
 941 };
 942
 943 /* ========================================================================= */
 944 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
 945 /* ========================================================================= */
 946 #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
 947
 948 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT             0
 949 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT                 8
 950 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT           11
 951 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT             12
 952 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT                  13
 953 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT                  15
 954 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT                  16
 955 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT            32
 956 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
 957 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
 958 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
 959 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
 960 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
 961 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
 962 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
 963 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 964
 965 union uvh_gr1_tlb_int1_config_u {
 966         unsigned long   v;
 967         struct uvh_gr1_tlb_int1_config_s {
 968                 unsigned long   vector_:8;                      /* RW */
 969                 unsigned long   dm:3;                           /* RW */
 970                 unsigned long   destmode:1;                     /* RW */
 971                 unsigned long   status:1;                       /* RO */
 972                 unsigned long   p:1;                            /* RO */
 973                 unsigned long   rsvd_14:1;
 974                 unsigned long   t:1;                            /* RO */
 975                 unsigned long   m:1;                            /* RW */
 976                 unsigned long   rsvd_17_31:15;
 977                 unsigned long   apic_id:32;                     /* RW */
 978         } s;
 979 };
 980
 981 /* ========================================================================= */
 982 /*                         UVH_GR1_TLB_MMR_CONTROL                           */
 983 /* ========================================================================= */
 984 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
 985 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
 986 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
 987 #define UVH_GR1_TLB_MMR_CONTROL                                         \
 988                 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :              \
 989                 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :              \
 990                                 UV3H_GR1_TLB_MMR_CONTROL))
 991
 992 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT              0
 993 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
 994 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
 995 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
 996 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
 997 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT           31
 998 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
 999 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
1000 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
1001 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
1002 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
1003 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
1004
1005 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1006 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1007 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1008 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1009 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1010 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1011 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
1012 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
1013 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
1014 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
1015 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
1016 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1017 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1018 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1019 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1020 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1021 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1022 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
1023 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
1024 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
1025 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
1026 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
1027
1028 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1029 #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1030 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1031 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1032 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1033 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1034 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1035 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1036 #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1037 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1038 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1039 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1040 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1041 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1042
1043 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1044 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1045 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1046 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1047 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1048 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1049 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1050 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
1051 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
1052 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1053 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1054 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1055 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1056 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1057 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1058 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1059 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
1060 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
1061
1062 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
1063 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
1064 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
1065 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1066 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT           21
1067 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
1068 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
1069 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
1070 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
1071 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
1072 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
1073 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1074 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK           0x0000000000200000UL
1075 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
1076 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
1077 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
1078
1079 union uvh_gr1_tlb_mmr_control_u {
1080         unsigned long   v;
1081         struct uvh_gr1_tlb_mmr_control_s {
1082                 unsigned long   index:12;                       /* RW */
1083                 unsigned long   mem_sel:2;                      /* RW */
1084                 unsigned long   rsvd_14_15:2;
1085                 unsigned long   auto_valid_en:1;                /* RW */
1086                 unsigned long   rsvd_17_19:3;
1087                 unsigned long   mmr_hash_index_en:1;            /* RW */
1088                 unsigned long   rsvd_21_29:9;
1089                 unsigned long   mmr_write:1;                    /* WP */
1090                 unsigned long   mmr_read:1;                     /* WP */
1091                 unsigned long   rsvd_32_48:17;
1092                 unsigned long   rsvd_49_51:3;
1093                 unsigned long   rsvd_52_63:12;
1094         } s;
1095         struct uv1h_gr1_tlb_mmr_control_s {
1096                 unsigned long   index:12;                       /* RW */
1097                 unsigned long   mem_sel:2;                      /* RW */
1098                 unsigned long   rsvd_14_15:2;
1099                 unsigned long   auto_valid_en:1;                /* RW */
1100                 unsigned long   rsvd_17_19:3;
1101                 unsigned long   mmr_hash_index_en:1;            /* RW */
1102                 unsigned long   rsvd_21_29:9;
1103                 unsigned long   mmr_write:1;                    /* WP */
1104                 unsigned long   mmr_read:1;                     /* WP */
1105                 unsigned long   rsvd_32_47:16;
1106                 unsigned long   mmr_inj_con:1;                  /* RW */
1107                 unsigned long   rsvd_49_51:3;
1108                 unsigned long   mmr_inj_tlbram:1;               /* RW */
1109                 unsigned long   rsvd_53:1;
1110                 unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
1111                 unsigned long   rsvd_55:1;
1112                 unsigned long   mmr_inj_tlbrreg:1;              /* RW */
1113                 unsigned long   rsvd_57_59:3;
1114                 unsigned long   mmr_inj_tlblruv:1;              /* RW */
1115                 unsigned long   rsvd_61_63:3;
1116         } s1;
1117         struct uvxh_gr1_tlb_mmr_control_s {
1118                 unsigned long   index:12;                       /* RW */
1119                 unsigned long   mem_sel:2;                      /* RW */
1120                 unsigned long   rsvd_14_15:2;
1121                 unsigned long   auto_valid_en:1;                /* RW */
1122                 unsigned long   rsvd_17_19:3;
1123                 unsigned long   mmr_hash_index_en:1;            /* RW */
1124                 unsigned long   rsvd_21_29:9;
1125                 unsigned long   mmr_write:1;                    /* WP */
1126                 unsigned long   mmr_read:1;                     /* WP */
1127                 unsigned long   mmr_op_done:1;                  /* RW */
1128                 unsigned long   rsvd_33_47:15;
1129                 unsigned long   rsvd_48:1;
1130                 unsigned long   rsvd_49_51:3;
1131                 unsigned long   rsvd_52:1;
1132                 unsigned long   rsvd_53_63:11;
1133         } sx;
1134         struct uv2h_gr1_tlb_mmr_control_s {
1135                 unsigned long   index:12;                       /* RW */
1136                 unsigned long   mem_sel:2;                      /* RW */
1137                 unsigned long   rsvd_14_15:2;
1138                 unsigned long   auto_valid_en:1;                /* RW */
1139                 unsigned long   rsvd_17_19:3;
1140                 unsigned long   mmr_hash_index_en:1;            /* RW */
1141                 unsigned long   rsvd_21_29:9;
1142                 unsigned long   mmr_write:1;                    /* WP */
1143                 unsigned long   mmr_read:1;                     /* WP */
1144                 unsigned long   mmr_op_done:1;                  /* RW */
1145                 unsigned long   rsvd_33_47:15;
1146                 unsigned long   mmr_inj_con:1;                  /* RW */
1147                 unsigned long   rsvd_49_51:3;
1148                 unsigned long   mmr_inj_tlbram:1;               /* RW */
1149                 unsigned long   rsvd_53_63:11;
1150         } s2;
1151         struct uv3h_gr1_tlb_mmr_control_s {
1152                 unsigned long   index:12;                       /* RW */
1153                 unsigned long   mem_sel:2;                      /* RW */
1154                 unsigned long   rsvd_14_15:2;
1155                 unsigned long   auto_valid_en:1;                /* RW */
1156                 unsigned long   rsvd_17_19:3;
1157                 unsigned long   mmr_hash_index_en:1;            /* RW */
1158                 unsigned long   ecc_sel:1;                      /* RW */
1159                 unsigned long   rsvd_22_29:8;
1160                 unsigned long   mmr_write:1;                    /* WP */
1161                 unsigned long   mmr_read:1;                     /* WP */
1162                 unsigned long   mmr_op_done:1;                  /* RW */
1163                 unsigned long   rsvd_33_47:15;
1164                 unsigned long   undef_48:1;                     /* Undefined */
1165                 unsigned long   rsvd_49_51:3;
1166                 unsigned long   undef_52:1;                     /* Undefined */
1167                 unsigned long   rsvd_53_63:11;
1168         } s3;
1169 };
1170
1171 /* ========================================================================= */
1172 /*                       UVH_GR1_TLB_MMR_READ_DATA_HI                        */
1173 /* ========================================================================= */
1174 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
1175 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1176 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1177 #define UVH_GR1_TLB_MMR_READ_DATA_HI                                    \
1178                 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :         \
1179                 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :         \
1180                                 UV3H_GR1_TLB_MMR_READ_DATA_HI))
1181
1182 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
1183 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
1184 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
1185 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
1186 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
1187 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
1188 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
1189 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
1190
1191 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1192 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1193 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1194 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1195 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1196 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1197 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1198 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1199
1200 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1201 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1202 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1203 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1204 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1205 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1206 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1207 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1208
1209 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1210 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1211 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1212 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1213 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1214 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1215 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1216 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1217
1218 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT          0
1219 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT          41
1220 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT        43
1221 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT       44
1222 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT       45
1223 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT      55
1224 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK          0x000001ffffffffffUL
1225 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK          0x0000060000000000UL
1226 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK        0x0000080000000000UL
1227 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK       0x0000100000000000UL
1228 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK       0x0000200000000000UL
1229 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK      0xff80000000000000UL
1230
1231 union uvh_gr1_tlb_mmr_read_data_hi_u {
1232         unsigned long   v;
1233         struct uvh_gr1_tlb_mmr_read_data_hi_s {
1234                 unsigned long   pfn:41;                         /* RO */
1235                 unsigned long   gaa:2;                          /* RO */
1236                 unsigned long   dirty:1;                        /* RO */
1237                 unsigned long   larger:1;                       /* RO */
1238                 unsigned long   rsvd_45_63:19;
1239         } s;
1240         struct uv1h_gr1_tlb_mmr_read_data_hi_s {
1241                 unsigned long   pfn:41;                         /* RO */
1242                 unsigned long   gaa:2;                          /* RO */
1243                 unsigned long   dirty:1;                        /* RO */
1244                 unsigned long   larger:1;                       /* RO */
1245                 unsigned long   rsvd_45_63:19;
1246         } s1;
1247         struct uvxh_gr1_tlb_mmr_read_data_hi_s {
1248                 unsigned long   pfn:41;                         /* RO */
1249                 unsigned long   gaa:2;                          /* RO */
1250                 unsigned long   dirty:1;                        /* RO */
1251                 unsigned long   larger:1;                       /* RO */
1252                 unsigned long   rsvd_45_63:19;
1253         } sx;
1254         struct uv2h_gr1_tlb_mmr_read_data_hi_s {
1255                 unsigned long   pfn:41;                         /* RO */
1256                 unsigned long   gaa:2;                          /* RO */
1257                 unsigned long   dirty:1;                        /* RO */
1258                 unsigned long   larger:1;                       /* RO */
1259                 unsigned long   rsvd_45_63:19;
1260         } s2;
1261         struct uv3h_gr1_tlb_mmr_read_data_hi_s {
1262                 unsigned long   pfn:41;                         /* RO */
1263                 unsigned long   gaa:2;                          /* RO */
1264                 unsigned long   dirty:1;                        /* RO */
1265                 unsigned long   larger:1;                       /* RO */
1266                 unsigned long   aa_ext:1;                       /* RO */
1267                 unsigned long   undef_46_54:9;                  /* Undefined */
1268                 unsigned long   way_ecc:9;                      /* RO */
1269         } s3;
1270 };
1271
1272 /* ========================================================================= */
1273 /*                       UVH_GR1_TLB_MMR_READ_DATA_LO                        */
1274 /* ========================================================================= */
1275 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
1276 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1277 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1278 #define UVH_GR1_TLB_MMR_READ_DATA_LO                                    \
1279                 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :         \
1280                 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :         \
1281                                 UV3H_GR1_TLB_MMR_READ_DATA_LO))
1282
1283 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
1284 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
1285 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
1286 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
1287 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
1288 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
1289
1290 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1291 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1292 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1293 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1294 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1295 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1296
1297 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1298 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1299 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1300 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1301 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1302 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1303
1304 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1305 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1306 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1307 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1308 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1309 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1310
1311 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT          0
1312 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT         39
1313 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT        63
1314 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK          0x0000007fffffffffUL
1315 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK         0x7fffff8000000000UL
1316 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK        0x8000000000000000UL
1317
1318 union uvh_gr1_tlb_mmr_read_data_lo_u {
1319         unsigned long   v;
1320         struct uvh_gr1_tlb_mmr_read_data_lo_s {
1321                 unsigned long   vpn:39;                         /* RO */
1322                 unsigned long   asid:24;                        /* RO */
1323                 unsigned long   valid:1;                        /* RO */
1324         } s;
1325         struct uv1h_gr1_tlb_mmr_read_data_lo_s {
1326                 unsigned long   vpn:39;                         /* RO */
1327                 unsigned long   asid:24;                        /* RO */
1328                 unsigned long   valid:1;                        /* RO */
1329         } s1;
1330         struct uvxh_gr1_tlb_mmr_read_data_lo_s {
1331                 unsigned long   vpn:39;                         /* RO */
1332                 unsigned long   asid:24;                        /* RO */
1333                 unsigned long   valid:1;                        /* RO */
1334         } sx;
1335         struct uv2h_gr1_tlb_mmr_read_data_lo_s {
1336                 unsigned long   vpn:39;                         /* RO */
1337                 unsigned long   asid:24;                        /* RO */
1338                 unsigned long   valid:1;                        /* RO */
1339         } s2;
1340         struct uv3h_gr1_tlb_mmr_read_data_lo_s {
1341                 unsigned long   vpn:39;                         /* RO */
1342                 unsigned long   asid:24;                        /* RO */
1343                 unsigned long   valid:1;                        /* RO */
1344         } s3;
1345 };
1346
1347 /* ========================================================================= */
1348 /*                               UVH_INT_CMPB                                */
1349 /* ========================================================================= */
1350 #define UVH_INT_CMPB 0x22080UL
1351
1352 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT                0
1353 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK                0x00ffffffffffffffUL
1354
1355 union uvh_int_cmpb_u {
1356         unsigned long   v;
1357         struct uvh_int_cmpb_s {
1358                 unsigned long   real_time_cmpb:56;              /* RW */
1359                 unsigned long   rsvd_56_63:8;
1360         } s;
1361 };
1362
1363 /* ========================================================================= */
1364 /*                               UVH_INT_CMPC                                */
1365 /* ========================================================================= */
1366 #define UVH_INT_CMPC 0x22100UL
1367
1368 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT               0
1369 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK               0x00ffffffffffffffUL
1370
1371 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT              0
1372 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK              0x00ffffffffffffffUL
1373
1374 union uvh_int_cmpc_u {
1375         unsigned long   v;
1376         struct uvh_int_cmpc_s {
1377                 unsigned long   real_time_cmpc:56;              /* RW */
1378                 unsigned long   rsvd_56_63:8;
1379         } s;
1380 };
1381
1382 /* ========================================================================= */
1383 /*                               UVH_INT_CMPD                                */
1384 /* ========================================================================= */
1385 #define UVH_INT_CMPD 0x22180UL
1386
1387 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT               0
1388 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK               0x00ffffffffffffffUL
1389
1390 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT              0
1391 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK              0x00ffffffffffffffUL
1392
1393 union uvh_int_cmpd_u {
1394         unsigned long   v;
1395         struct uvh_int_cmpd_s {
1396                 unsigned long   real_time_cmpd:56;              /* RW */
1397                 unsigned long   rsvd_56_63:8;
1398         } s;
1399 };
1400
1401 /* ========================================================================= */
1402 /*                               UVH_IPI_INT                                 */
1403 /* ========================================================================= */
1404 #define UVH_IPI_INT 0x60500UL
1405 #define UVH_IPI_INT_32 0x348
1406
1407 #define UVH_IPI_INT_VECTOR_SHFT                         0
1408 #define UVH_IPI_INT_DELIVERY_MODE_SHFT                  8
1409 #define UVH_IPI_INT_DESTMODE_SHFT                       11
1410 #define UVH_IPI_INT_APIC_ID_SHFT                        16
1411 #define UVH_IPI_INT_SEND_SHFT                           63
1412 #define UVH_IPI_INT_VECTOR_MASK                         0x00000000000000ffUL
1413 #define UVH_IPI_INT_DELIVERY_MODE_MASK                  0x0000000000000700UL
1414 #define UVH_IPI_INT_DESTMODE_MASK                       0x0000000000000800UL
1415 #define UVH_IPI_INT_APIC_ID_MASK                        0x0000ffffffff0000UL
1416 #define UVH_IPI_INT_SEND_MASK                           0x8000000000000000UL
1417
1418 union uvh_ipi_int_u {
1419         unsigned long   v;
1420         struct uvh_ipi_int_s {
1421                 unsigned long   vector_:8;                      /* RW */
1422                 unsigned long   delivery_mode:3;                /* RW */
1423                 unsigned long   destmode:1;                     /* RW */
1424                 unsigned long   rsvd_12_15:4;
1425                 unsigned long   apic_id:32;                     /* RW */
1426                 unsigned long   rsvd_48_62:15;
1427                 unsigned long   send:1;                         /* WP */
1428         } s;
1429 };
1430
1431 /* ========================================================================= */
1432 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
1433 /* ========================================================================= */
1434 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1435 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
1436
1437 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1438 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1439 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1440 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1441
1442 union uvh_lb_bau_intd_payload_queue_first_u {
1443         unsigned long   v;
1444         struct uvh_lb_bau_intd_payload_queue_first_s {
1445                 unsigned long   rsvd_0_3:4;
1446                 unsigned long   address:39;                     /* RW */
1447                 unsigned long   rsvd_43_48:6;
1448                 unsigned long   node_id:14;                     /* RW */
1449                 unsigned long   rsvd_63:1;
1450         } s;
1451 };
1452
1453 /* ========================================================================= */
1454 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
1455 /* ========================================================================= */
1456 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1457 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
1458
1459 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1460 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1461
1462 union uvh_lb_bau_intd_payload_queue_last_u {
1463         unsigned long   v;
1464         struct uvh_lb_bau_intd_payload_queue_last_s {
1465                 unsigned long   rsvd_0_3:4;
1466                 unsigned long   address:39;                     /* RW */
1467                 unsigned long   rsvd_43_63:21;
1468         } s;
1469 };
1470
1471 /* ========================================================================= */
1472 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
1473 /* ========================================================================= */
1474 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1475 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
1476
1477 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1478 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1479
1480 union uvh_lb_bau_intd_payload_queue_tail_u {
1481         unsigned long   v;
1482         struct uvh_lb_bau_intd_payload_queue_tail_s {
1483                 unsigned long   rsvd_0_3:4;
1484                 unsigned long   address:39;                     /* RW */
1485                 unsigned long   rsvd_43_63:21;
1486         } s;
1487 };
1488
1489 /* ========================================================================= */
1490 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
1491 /* ========================================================================= */
1492 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
1493 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
1494
1495 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
1496 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
1497 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
1498 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
1499 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
1500 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
1501 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
1502 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
1503 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
1504 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
1505 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
1506 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
1507 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
1508 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
1509 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
1510 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
1511 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
1512 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
1513 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
1514 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
1515 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
1516 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
1517 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
1518 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
1519 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
1520 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
1521 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
1522 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
1523 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
1524 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
1525 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
1526 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
1527
1528 union uvh_lb_bau_intd_software_acknowledge_u {
1529         unsigned long   v;
1530         struct uvh_lb_bau_intd_software_acknowledge_s {
1531                 unsigned long   pending_0:1;                    /* RW, W1C */
1532                 unsigned long   pending_1:1;                    /* RW, W1C */
1533                 unsigned long   pending_2:1;                    /* RW, W1C */
1534                 unsigned long   pending_3:1;                    /* RW, W1C */
1535                 unsigned long   pending_4:1;                    /* RW, W1C */
1536                 unsigned long   pending_5:1;                    /* RW, W1C */
1537                 unsigned long   pending_6:1;                    /* RW, W1C */
1538                 unsigned long   pending_7:1;                    /* RW, W1C */
1539                 unsigned long   timeout_0:1;                    /* RW, W1C */
1540                 unsigned long   timeout_1:1;                    /* RW, W1C */
1541                 unsigned long   timeout_2:1;                    /* RW, W1C */
1542                 unsigned long   timeout_3:1;                    /* RW, W1C */
1543                 unsigned long   timeout_4:1;                    /* RW, W1C */
1544                 unsigned long   timeout_5:1;                    /* RW, W1C */
1545                 unsigned long   timeout_6:1;                    /* RW, W1C */
1546                 unsigned long   timeout_7:1;                    /* RW, W1C */
1547                 unsigned long   rsvd_16_63:48;
1548         } s;
1549 };
1550
1551 /* ========================================================================= */
1552 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
1553 /* ========================================================================= */
1554 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
1555 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
1556
1557
1558 /* ========================================================================= */
1559 /*                         UVH_LB_BAU_MISC_CONTROL                           */
1560 /* ========================================================================= */
1561 #define UVH_LB_BAU_MISC_CONTROL 0x320170UL
1562 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL
1563 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL
1564 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL
1565 #define UVH_LB_BAU_MISC_CONTROL_32 0xa10
1566 #define UV1H_LB_BAU_MISC_CONTROL_32 0x320170UL
1567 #define UV2H_LB_BAU_MISC_CONTROL_32 0x320170UL
1568 #define UV3H_LB_BAU_MISC_CONTROL_32 0x320170UL
1569
1570 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT    0
1571 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT          8
1572 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT    9
1573 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT     10
1574 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1575 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1576 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1577 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1578 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1579 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1580 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1581 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1582 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1583 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1584 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1585 #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT                48
1586 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK    0x00000000000000ffUL
1587 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK          0x0000000000000100UL
1588 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK    0x0000000000000200UL
1589 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK     0x0000000000000400UL
1590 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1591 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1592 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1593 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1594 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1595 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1596 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1597 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1598 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1599 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1600 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1601 #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK                0xffff000000000000UL
1602
1603 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
1604 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
1605 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
1606 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
1607 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1608 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1609 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1610 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1611 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1612 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1613 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1614 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1615 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1616 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1617 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1618 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
1619 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
1620 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
1621 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
1622 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
1623 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1624 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1625 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1626 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1627 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1628 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1629 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1630 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1631 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1632 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1633 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1634 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
1635
1636 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
1637 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
1638 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
1639 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
1640 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1641 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1642 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1643 #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1644 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1645 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1646 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1647 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1648 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1649 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1650 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1651 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
1652 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
1653 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
1654 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
1655 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
1656 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
1657 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
1658 #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT               48
1659 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
1660 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
1661 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
1662 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
1663 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1664 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1665 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1666 #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1667 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1668 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1669 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1670 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1671 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1672 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1673 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1674 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
1675 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
1676 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
1677 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
1678 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
1679 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
1680 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
1681 #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
1682
1683 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
1684 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
1685 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
1686 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
1687 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1688 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1689 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1690 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1691 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1692 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1693 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1694 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1695 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1696 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1697 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1698 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
1699 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
1700 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
1701 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
1702 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
1703 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
1704 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
1705 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
1706 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
1707 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
1708 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
1709 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
1710 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1711 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1712 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1713 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1714 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1715 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1716 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1717 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1718 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1719 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1720 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1721 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
1722 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
1723 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
1724 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
1725 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
1726 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
1727 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
1728 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
1729
1730 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
1731 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
1732 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
1733 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
1734 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1735 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1736 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1737 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1738 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1739 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1740 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1741 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1742 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1743 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1744 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1745 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
1746 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
1747 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
1748 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
1749 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
1750 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
1751 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
1752 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
1753 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37
1754 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
1755 #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
1756 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
1757 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
1758 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
1759 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
1760 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1761 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1762 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1763 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1764 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1765 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1766 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1767 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1768 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1769 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1770 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1771 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
1772 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
1773 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
1774 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
1775 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
1776 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
1777 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
1778 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
1779 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL
1780 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
1781 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
1782
1783 union uvh_lb_bau_misc_control_u {
1784         unsigned long   v;
1785         struct uvh_lb_bau_misc_control_s {
1786                 unsigned long   rejection_delay:8;              /* RW */
1787                 unsigned long   apic_mode:1;                    /* RW */
1788                 unsigned long   force_broadcast:1;              /* RW */
1789                 unsigned long   force_lock_nop:1;               /* RW */
1790                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
1791                 unsigned long   descriptor_fetch_mode:1;        /* RW */
1792                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
1793                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
1794                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
1795                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
1796                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
1797                 unsigned long   suppress_dest_registration:1;   /* RW */
1798                 unsigned long   programmed_initial_priority:3;  /* RW */
1799                 unsigned long   use_incoming_priority:1;        /* RW */
1800                 unsigned long   enable_programmed_initial_priority:1;/* RW */
1801                 unsigned long   rsvd_29_47:19;
1802                 unsigned long   fun:16;                         /* RW */
1803         } s;
1804         struct uv1h_lb_bau_misc_control_s {
1805                 unsigned long   rejection_delay:8;              /* RW */
1806                 unsigned long   apic_mode:1;                    /* RW */
1807                 unsigned long   force_broadcast:1;              /* RW */
1808                 unsigned long   force_lock_nop:1;               /* RW */
1809                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
1810                 unsigned long   descriptor_fetch_mode:1;        /* RW */
1811                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
1812                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
1813                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
1814                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
1815                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
1816                 unsigned long   suppress_dest_registration:1;   /* RW */
1817                 unsigned long   programmed_initial_priority:3;  /* RW */
1818                 unsigned long   use_incoming_priority:1;        /* RW */
1819                 unsigned long   enable_programmed_initial_priority:1;/* RW */
1820                 unsigned long   rsvd_29_47:19;
1821                 unsigned long   fun:16;                         /* RW */
1822         } s1;
1823         struct uvxh_lb_bau_misc_control_s {
1824                 unsigned long   rejection_delay:8;              /* RW */
1825                 unsigned long   apic_mode:1;                    /* RW */
1826                 unsigned long   force_broadcast:1;              /* RW */
1827                 unsigned long   force_lock_nop:1;               /* RW */
1828                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
1829                 unsigned long   descriptor_fetch_mode:1;        /* RW */
1830                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
1831                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
1832                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
1833                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
1834                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
1835                 unsigned long   suppress_dest_registration:1;   /* RW */
1836                 unsigned long   programmed_initial_priority:3;  /* RW */
1837                 unsigned long   use_incoming_priority:1;        /* RW */
1838                 unsigned long   enable_programmed_initial_priority:1;/* RW */
1839                 unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
1840                 unsigned long   apic_mode_status:1;             /* RO */
1841                 unsigned long   suppress_interrupts_to_self:1;  /* RW */
1842                 unsigned long   enable_lock_based_system_flush:1;/* RW */
1843                 unsigned long   enable_extended_sb_status:1;    /* RW */
1844                 unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
1845                 unsigned long   use_legacy_descriptor_formats:1;/* RW */
1846                 unsigned long   rsvd_36_47:12;
1847                 unsigned long   fun:16;                         /* RW */
1848         } sx;
1849         struct uv2h_lb_bau_misc_control_s {
1850                 unsigned long   rejection_delay:8;              /* RW */
1851                 unsigned long   apic_mode:1;                    /* RW */
1852                 unsigned long   force_broadcast:1;              /* RW */
1853                 unsigned long   force_lock_nop:1;               /* RW */
1854                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
1855                 unsigned long   descriptor_fetch_mode:1;        /* RW */
1856                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
1857                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
1858                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
1859                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
1860                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
1861                 unsigned long   suppress_dest_registration:1;   /* RW */
1862                 unsigned long   programmed_initial_priority:3;  /* RW */
1863                 unsigned long   use_incoming_priority:1;        /* RW */
1864                 unsigned long   enable_programmed_initial_priority:1;/* RW */
1865                 unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
1866                 unsigned long   apic_mode_status:1;             /* RO */
1867                 unsigned long   suppress_interrupts_to_self:1;  /* RW */
1868                 unsigned long   enable_lock_based_system_flush:1;/* RW */
1869                 unsigned long   enable_extended_sb_status:1;    /* RW */
1870                 unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
1871                 unsigned long   use_legacy_descriptor_formats:1;/* RW */
1872                 unsigned long   rsvd_36_47:12;
1873                 unsigned long   fun:16;                         /* RW */
1874         } s2;
1875         struct uv3h_lb_bau_misc_control_s {
1876                 unsigned long   rejection_delay:8;              /* RW */
1877                 unsigned long   apic_mode:1;                    /* RW */
1878                 unsigned long   force_broadcast:1;              /* RW */
1879                 unsigned long   force_lock_nop:1;               /* RW */
1880                 unsigned long   qpi_agent_presence_vector:3;    /* RW */
1881                 unsigned long   descriptor_fetch_mode:1;        /* RW */
1882                 unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
1883                 unsigned long   intd_soft_ack_timeout_period:4; /* RW */
1884                 unsigned long   enable_dual_mapping_mode:1;     /* RW */
1885                 unsigned long   vga_io_port_decode_enable:1;    /* RW */
1886                 unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
1887                 unsigned long   suppress_dest_registration:1;   /* RW */
1888                 unsigned long   programmed_initial_priority:3;  /* RW */
1889                 unsigned long   use_incoming_priority:1;        /* RW */
1890                 unsigned long   enable_programmed_initial_priority:1;/* RW */
1891                 unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
1892                 unsigned long   apic_mode_status:1;             /* RO */
1893                 unsigned long   suppress_interrupts_to_self:1;  /* RW */
1894                 unsigned long   enable_lock_based_system_flush:1;/* RW */
1895                 unsigned long   enable_extended_sb_status:1;    /* RW */
1896                 unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
1897                 unsigned long   use_legacy_descriptor_formats:1;/* RW */
1898                 unsigned long   suppress_quiesce_msgs_to_qpi:1; /* RW */
1899                 unsigned long   enable_intd_prefetch_hint:1;    /* RW */
1900                 unsigned long   thread_kill_timebase:8;         /* RW */
1901                 unsigned long   rsvd_46_47:2;
1902                 unsigned long   fun:16;                         /* RW */
1903         } s3;
1904 };
1905
1906 /* ========================================================================= */
1907 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
1908 /* ========================================================================= */
1909 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
1910 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
1911
1912 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT     0
1913 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT      62
1914 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT      63
1915 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK     0x000000000000003fUL
1916 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK      0x4000000000000000UL
1917 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK      0x8000000000000000UL
1918
1919 union uvh_lb_bau_sb_activation_control_u {
1920         unsigned long   v;
1921         struct uvh_lb_bau_sb_activation_control_s {
1922                 unsigned long   index:6;                        /* RW */
1923                 unsigned long   rsvd_6_61:56;
1924                 unsigned long   push:1;                         /* WP */
1925                 unsigned long   init:1;                         /* WP */
1926         } s;
1927 };
1928
1929 /* ========================================================================= */
1930 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
1931 /* ========================================================================= */
1932 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
1933 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
1934
1935 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT   0
1936 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK   0xffffffffffffffffUL
1937
1938 union uvh_lb_bau_sb_activation_status_0_u {
1939         unsigned long   v;
1940         struct uvh_lb_bau_sb_activation_status_0_s {
1941                 unsigned long   status:64;                      /* RW */
1942         } s;
1943 };
1944
1945 /* ========================================================================= */
1946 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
1947 /* ========================================================================= */
1948 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
1949 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
1950
1951 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT   0
1952 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK   0xffffffffffffffffUL
1953
1954 union uvh_lb_bau_sb_activation_status_1_u {
1955         unsigned long   v;
1956         struct uvh_lb_bau_sb_activation_status_1_s {
1957                 unsigned long   status:64;                      /* RW */
1958         } s;
1959 };
1960
1961 /* ========================================================================= */
1962 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
1963 /* ========================================================================= */
1964 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
1965 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
1966
1967 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
1968 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT      49
1969 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
1970 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK      0x7ffe000000000000UL
1971
1972 union uvh_lb_bau_sb_descriptor_base_u {
1973         unsigned long   v;
1974         struct uvh_lb_bau_sb_descriptor_base_s {
1975                 unsigned long   rsvd_0_11:12;
1976                 unsigned long   page_address:31;                /* RW */
1977                 unsigned long   rsvd_43_48:6;
1978                 unsigned long   node_id:14;                     /* RW */
1979                 unsigned long   rsvd_63:1;
1980         } s;
1981 };
1982
1983 /* ========================================================================= */
1984 /*                               UVH_NODE_ID                                 */
1985 /* ========================================================================= */
1986 #define UVH_NODE_ID 0x0UL
1987 #define UV1H_NODE_ID 0x0UL
1988 #define UV2H_NODE_ID 0x0UL
1989 #define UV3H_NODE_ID 0x0UL
1990
1991 #define UVH_NODE_ID_FORCE1_SHFT                         0
1992 #define UVH_NODE_ID_MANUFACTURER_SHFT                   1
1993 #define UVH_NODE_ID_PART_NUMBER_SHFT                    12
1994 #define UVH_NODE_ID_REVISION_SHFT                       28
1995 #define UVH_NODE_ID_NODE_ID_SHFT                        32
1996 #define UVH_NODE_ID_FORCE1_MASK                         0x0000000000000001UL
1997 #define UVH_NODE_ID_MANUFACTURER_MASK                   0x0000000000000ffeUL
1998 #define UVH_NODE_ID_PART_NUMBER_MASK                    0x000000000ffff000UL
1999 #define UVH_NODE_ID_REVISION_MASK                       0x00000000f0000000UL
2000 #define UVH_NODE_ID_NODE_ID_MASK                        0x00007fff00000000UL
2001
2002 #define UV1H_NODE_ID_FORCE1_SHFT                        0
2003 #define UV1H_NODE_ID_MANUFACTURER_SHFT                  1
2004 #define UV1H_NODE_ID_PART_NUMBER_SHFT                   12
2005 #define UV1H_NODE_ID_REVISION_SHFT                      28
2006 #define UV1H_NODE_ID_NODE_ID_SHFT                       32
2007 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT                 48
2008 #define UV1H_NODE_ID_NI_PORT_SHFT                       56
2009 #define UV1H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2010 #define UV1H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2011 #define UV1H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2012 #define UV1H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2013 #define UV1H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2014 #define UV1H_NODE_ID_NODES_PER_BIT_MASK                 0x007f000000000000UL
2015 #define UV1H_NODE_ID_NI_PORT_MASK                       0x0f00000000000000UL
2016
2017 #define UVXH_NODE_ID_FORCE1_SHFT                        0
2018 #define UVXH_NODE_ID_MANUFACTURER_SHFT                  1
2019 #define UVXH_NODE_ID_PART_NUMBER_SHFT                   12
2020 #define UVXH_NODE_ID_REVISION_SHFT                      28
2021 #define UVXH_NODE_ID_NODE_ID_SHFT                       32
2022 #define UVXH_NODE_ID_NODES_PER_BIT_SHFT                 50
2023 #define UVXH_NODE_ID_NI_PORT_SHFT                       57
2024 #define UVXH_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2025 #define UVXH_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2026 #define UVXH_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2027 #define UVXH_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2028 #define UVXH_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2029 #define UVXH_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
2030 #define UVXH_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
2031
2032 #define UV2H_NODE_ID_FORCE1_SHFT                        0
2033 #define UV2H_NODE_ID_MANUFACTURER_SHFT                  1
2034 #define UV2H_NODE_ID_PART_NUMBER_SHFT                   12
2035 #define UV2H_NODE_ID_REVISION_SHFT                      28
2036 #define UV2H_NODE_ID_NODE_ID_SHFT                       32
2037 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT                 50
2038 #define UV2H_NODE_ID_NI_PORT_SHFT                       57
2039 #define UV2H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2040 #define UV2H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2041 #define UV2H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2042 #define UV2H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2043 #define UV2H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2044 #define UV2H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
2045 #define UV2H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
2046
2047 #define UV3H_NODE_ID_FORCE1_SHFT                        0
2048 #define UV3H_NODE_ID_MANUFACTURER_SHFT                  1
2049 #define UV3H_NODE_ID_PART_NUMBER_SHFT                   12
2050 #define UV3H_NODE_ID_REVISION_SHFT                      28
2051 #define UV3H_NODE_ID_NODE_ID_SHFT                       32
2052 #define UV3H_NODE_ID_ROUTER_SELECT_SHFT                 48
2053 #define UV3H_NODE_ID_RESERVED_2_SHFT                    49
2054 #define UV3H_NODE_ID_NODES_PER_BIT_SHFT                 50
2055 #define UV3H_NODE_ID_NI_PORT_SHFT                       57
2056 #define UV3H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
2057 #define UV3H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
2058 #define UV3H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
2059 #define UV3H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
2060 #define UV3H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
2061 #define UV3H_NODE_ID_ROUTER_SELECT_MASK                 0x0001000000000000UL
2062 #define UV3H_NODE_ID_RESERVED_2_MASK                    0x0002000000000000UL
2063 #define UV3H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
2064 #define UV3H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
2065
2066 union uvh_node_id_u {
2067         unsigned long   v;
2068         struct uvh_node_id_s {
2069                 unsigned long   force1:1;                       /* RO */
2070                 unsigned long   manufacturer:11;                /* RO */
2071                 unsigned long   part_number:16;                 /* RO */
2072                 unsigned long   revision:4;                     /* RO */
2073                 unsigned long   node_id:15;                     /* RW */
2074                 unsigned long   rsvd_47_63:17;
2075         } s;
2076         struct uv1h_node_id_s {
2077                 unsigned long   force1:1;                       /* RO */
2078                 unsigned long   manufacturer:11;                /* RO */
2079                 unsigned long   part_number:16;                 /* RO */
2080                 unsigned long   revision:4;                     /* RO */
2081                 unsigned long   node_id:15;                     /* RW */
2082                 unsigned long   rsvd_47:1;
2083                 unsigned long   nodes_per_bit:7;                /* RW */
2084                 unsigned long   rsvd_55:1;
2085                 unsigned long   ni_port:4;                      /* RO */
2086                 unsigned long   rsvd_60_63:4;
2087         } s1;
2088         struct uvxh_node_id_s {
2089                 unsigned long   force1:1;                       /* RO */
2090                 unsigned long   manufacturer:11;                /* RO */
2091                 unsigned long   part_number:16;                 /* RO */
2092                 unsigned long   revision:4;                     /* RO */
2093                 unsigned long   node_id:15;                     /* RW */
2094                 unsigned long   rsvd_47_49:3;
2095                 unsigned long   nodes_per_bit:7;                /* RO */
2096                 unsigned long   ni_port:5;                      /* RO */
2097                 unsigned long   rsvd_62_63:2;
2098         } sx;
2099         struct uv2h_node_id_s {
2100                 unsigned long   force1:1;                       /* RO */
2101                 unsigned long   manufacturer:11;                /* RO */
2102                 unsigned long   part_number:16;                 /* RO */
2103                 unsigned long   revision:4;                     /* RO */
2104                 unsigned long   node_id:15;                     /* RW */
2105                 unsigned long   rsvd_47_49:3;
2106                 unsigned long   nodes_per_bit:7;                /* RO */
2107                 unsigned long   ni_port:5;                      /* RO */
2108                 unsigned long   rsvd_62_63:2;
2109         } s2;
2110         struct uv3h_node_id_s {
2111                 unsigned long   force1:1;                       /* RO */
2112                 unsigned long   manufacturer:11;                /* RO */
2113                 unsigned long   part_number:16;                 /* RO */
2114                 unsigned long   revision:4;                     /* RO */
2115                 unsigned long   node_id:15;                     /* RW */
2116                 unsigned long   rsvd_47:1;
2117                 unsigned long   router_select:1;                /* RO */
2118                 unsigned long   rsvd_49:1;
2119                 unsigned long   nodes_per_bit:7;                /* RO */
2120                 unsigned long   ni_port:5;                      /* RO */
2121                 unsigned long   rsvd_62_63:2;
2122         } s3;
2123 };
2124
2125 /* ========================================================================= */
2126 /*                          UVH_NODE_PRESENT_TABLE                           */
2127 /* ========================================================================= */
2128 #define UVH_NODE_PRESENT_TABLE 0x1400UL
2129 #define UVH_NODE_PRESENT_TABLE_DEPTH 16
2130
2131 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT               0
2132 #define UVH_NODE_PRESENT_TABLE_NODES_MASK               0xffffffffffffffffUL
2133
2134 union uvh_node_present_table_u {
2135         unsigned long   v;
2136         struct uvh_node_present_table_s {
2137                 unsigned long   nodes:64;                       /* RW */
2138         } s;
2139 };
2140
2141 /* ========================================================================= */
2142 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
2143 /* ========================================================================= */
2144 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
2145
2146 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
2147 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
2148 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
2149 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
2150 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
2151 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
2152
2153 union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
2154         unsigned long   v;
2155         struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
2156                 unsigned long   rsvd_0_23:24;
2157                 unsigned long   base:8;                         /* RW */
2158                 unsigned long   rsvd_32_47:16;
2159                 unsigned long   m_alias:5;                      /* RW */
2160                 unsigned long   rsvd_53_62:10;
2161                 unsigned long   enable:1;                       /* RW */
2162         } s;
2163 };
2164
2165 /* ========================================================================= */
2166 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
2167 /* ========================================================================= */
2168 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
2169
2170 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
2171 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
2172 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
2173 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
2174 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
2175 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
2176
2177 union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
2178         unsigned long   v;
2179         struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
2180                 unsigned long   rsvd_0_23:24;
2181                 unsigned long   base:8;                         /* RW */
2182                 unsigned long   rsvd_32_47:16;
2183                 unsigned long   m_alias:5;                      /* RW */
2184                 unsigned long   rsvd_53_62:10;
2185                 unsigned long   enable:1;                       /* RW */
2186         } s;
2187 };
2188
2189 /* ========================================================================= */
2190 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
2191 /* ========================================================================= */
2192 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
2193
2194 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
2195 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
2196 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
2197 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
2198 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
2199 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
2200
2201 union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
2202         unsigned long   v;
2203         struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
2204                 unsigned long   rsvd_0_23:24;
2205                 unsigned long   base:8;                         /* RW */
2206                 unsigned long   rsvd_32_47:16;
2207                 unsigned long   m_alias:5;                      /* RW */
2208                 unsigned long   rsvd_53_62:10;
2209                 unsigned long   enable:1;                       /* RW */
2210         } s;
2211 };
2212
2213 /* ========================================================================= */
2214 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
2215 /* ========================================================================= */
2216 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
2217
2218 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
2219 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
2220
2221 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
2222         unsigned long   v;
2223         struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
2224                 unsigned long   rsvd_0_23:24;
2225                 unsigned long   dest_base:22;                   /* RW */
2226                 unsigned long   rsvd_46_63:18;
2227         } s;
2228 };
2229
2230 /* ========================================================================= */
2231 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
2232 /* ========================================================================= */
2233 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
2234
2235 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
2236 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
2237
2238 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
2239         unsigned long   v;
2240         struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
2241                 unsigned long   rsvd_0_23:24;
2242                 unsigned long   dest_base:22;                   /* RW */
2243                 unsigned long   rsvd_46_63:18;
2244         } s;
2245 };
2246
2247 /* ========================================================================= */
2248 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
2249 /* ========================================================================= */
2250 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
2251
2252 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
2253 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
2254
2255 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
2256         unsigned long   v;
2257         struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
2258                 unsigned long   rsvd_0_23:24;
2259                 unsigned long   dest_base:22;                   /* RW */
2260                 unsigned long   rsvd_46_63:18;
2261         } s;
2262 };
2263
2264 /* ========================================================================= */
2265 /*                          UVH_RH_GAM_CONFIG_MMR                            */
2266 /* ========================================================================= */
2267 #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
2268 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL
2269 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL
2270 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL
2271
2272 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT                0
2273 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT                6
2274 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK                0x000000000000003fUL
2275 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK                0x00000000000003c0UL
2276
2277 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
2278 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
2279 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT           12
2280 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
2281 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
2282 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK           0x0000000000001000UL
2283
2284 #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
2285 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
2286 #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
2287 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
2288
2289 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
2290 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
2291 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
2292 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
2293
2294 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
2295 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
2296 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
2297 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
2298
2299 union uvh_rh_gam_config_mmr_u {
2300         unsigned long   v;
2301         struct uvh_rh_gam_config_mmr_s {
2302                 unsigned long   m_skt:6;                        /* RW */
2303                 unsigned long   n_skt:4;                        /* RW */
2304                 unsigned long   rsvd_10_63:54;
2305         } s;
2306         struct uv1h_rh_gam_config_mmr_s {
2307                 unsigned long   m_skt:6;                        /* RW */
2308                 unsigned long   n_skt:4;                        /* RW */
2309                 unsigned long   rsvd_10_11:2;
2310                 unsigned long   mmiol_cfg:1;                    /* RW */
2311                 unsigned long   rsvd_13_63:51;
2312         } s1;
2313         struct uvxh_rh_gam_config_mmr_s {
2314                 unsigned long   m_skt:6;                        /* RW */
2315                 unsigned long   n_skt:4;                        /* RW */
2316                 unsigned long   rsvd_10_63:54;
2317         } sx;
2318         struct uv2h_rh_gam_config_mmr_s {
2319                 unsigned long   m_skt:6;                        /* RW */
2320                 unsigned long   n_skt:4;                        /* RW */
2321                 unsigned long   rsvd_10_63:54;
2322         } s2;
2323         struct uv3h_rh_gam_config_mmr_s {
2324                 unsigned long   m_skt:6;                        /* RW */
2325                 unsigned long   n_skt:4;                        /* RW */
2326                 unsigned long   rsvd_10_63:54;
2327         } s3;
2328 };
2329
2330 /* ========================================================================= */
2331 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
2332 /* ========================================================================= */
2333 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
2334 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
2335 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
2336 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
2337
2338 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT     28
2339 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT    52
2340 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT   63
2341 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK     0x00003ffff0000000UL
2342 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK    0x00f0000000000000UL
2343 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK   0x8000000000000000UL
2344
2345 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
2346 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT     48
2347 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
2348 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2349 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
2350 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK     0x0001000000000000UL
2351 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
2352 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2353
2354 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
2355 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
2356 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2357 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
2358 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
2359 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2360
2361 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
2362 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
2363 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2364 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
2365 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
2366 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2367
2368 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
2369 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
2370 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT    62
2371 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2372 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
2373 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
2374 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK    0x4000000000000000UL
2375 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2376
2377 union uvh_rh_gam_gru_overlay_config_mmr_u {
2378         unsigned long   v;
2379         struct uvh_rh_gam_gru_overlay_config_mmr_s {
2380                 unsigned long   rsvd_0_27:28;
2381                 unsigned long   base:18;                        /* RW */
2382                 unsigned long   rsvd_46_51:6;
2383                 unsigned long   n_gru:4;                        /* RW */
2384                 unsigned long   rsvd_56_62:7;
2385                 unsigned long   enable:1;                       /* RW */
2386         } s;
2387         struct uv1h_rh_gam_gru_overlay_config_mmr_s {
2388                 unsigned long   rsvd_0_27:28;
2389                 unsigned long   base:18;                        /* RW */
2390                 unsigned long   rsvd_46_47:2;
2391                 unsigned long   gr4:1;                          /* RW */
2392                 unsigned long   rsvd_49_51:3;
2393                 unsigned long   n_gru:4;                        /* RW */
2394                 unsigned long   rsvd_56_62:7;
2395                 unsigned long   enable:1;                       /* RW */
2396         } s1;
2397         struct uvxh_rh_gam_gru_overlay_config_mmr_s {
2398                 unsigned long   rsvd_0_27:28;
2399                 unsigned long   base:18;                        /* RW */
2400                 unsigned long   rsvd_46_51:6;
2401                 unsigned long   n_gru:4;                        /* RW */
2402                 unsigned long   rsvd_56_62:7;
2403                 unsigned long   enable:1;                       /* RW */
2404         } sx;
2405         struct uv2h_rh_gam_gru_overlay_config_mmr_s {
2406                 unsigned long   rsvd_0_27:28;
2407                 unsigned long   base:18;                        /* RW */
2408                 unsigned long   rsvd_46_51:6;
2409                 unsigned long   n_gru:4;                        /* RW */
2410                 unsigned long   rsvd_56_62:7;
2411                 unsigned long   enable:1;                       /* RW */
2412         } s2;
2413         struct uv3h_rh_gam_gru_overlay_config_mmr_s {
2414                 unsigned long   rsvd_0_27:28;
2415                 unsigned long   base:18;                        /* RW */
2416                 unsigned long   rsvd_46_51:6;
2417                 unsigned long   n_gru:4;                        /* RW */
2418                 unsigned long   rsvd_56_61:6;
2419                 unsigned long   mode:1;                         /* RW */
2420                 unsigned long   enable:1;                       /* RW */
2421         } s3;
2422 };
2423
2424 /* ========================================================================= */
2425 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
2426 /* ========================================================================= */
2427 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
2428 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
2429
2430 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  30
2431 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
2432 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT  52
2433 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
2434 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK  0x00003fffc0000000UL
2435 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK  0x000fc00000000000UL
2436 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
2437 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2438
2439 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  27
2440 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
2441 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT  52
2442 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
2443 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK  0x00003ffff8000000UL
2444 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK  0x000fc00000000000UL
2445 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
2446 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2447
2448 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
2449         unsigned long   v;
2450         struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
2451                 unsigned long   rsvd_0_29:30;
2452                 unsigned long   base:16;                        /* RW */
2453                 unsigned long   m_io:6;                         /* RW */
2454                 unsigned long   n_io:4;                         /* RW */
2455                 unsigned long   rsvd_56_62:7;
2456                 unsigned long   enable:1;                       /* RW */
2457         } s1;
2458         struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
2459                 unsigned long   rsvd_0_26:27;
2460                 unsigned long   base:19;                        /* RW */
2461                 unsigned long   m_io:6;                         /* RW */
2462                 unsigned long   n_io:4;                         /* RW */
2463                 unsigned long   rsvd_56_62:7;
2464                 unsigned long   enable:1;                       /* RW */
2465         } s2;
2466 };
2467
2468 /* ========================================================================= */
2469 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
2470 /* ========================================================================= */
2471 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
2472 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
2473 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
2474 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
2475
2476 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT     26
2477 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT   63
2478 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK     0x00003ffffc000000UL
2479 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK   0x8000000000000000UL
2480
2481 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
2482 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
2483 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2484 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
2485 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
2486 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2487
2488 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
2489 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2490 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
2491 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2492
2493 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
2494 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2495 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
2496 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2497
2498 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
2499 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
2500 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
2501 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
2502
2503 union uvh_rh_gam_mmr_overlay_config_mmr_u {
2504         unsigned long   v;
2505         struct uvh_rh_gam_mmr_overlay_config_mmr_s {
2506                 unsigned long   rsvd_0_25:26;
2507                 unsigned long   base:20;                        /* RW */
2508                 unsigned long   rsvd_46_62:17;
2509                 unsigned long   enable:1;                       /* RW */
2510         } s;
2511         struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
2512                 unsigned long   rsvd_0_25:26;
2513                 unsigned long   base:20;                        /* RW */
2514                 unsigned long   dual_hub:1;                     /* RW */
2515                 unsigned long   rsvd_47_62:16;
2516                 unsigned long   enable:1;                       /* RW */
2517         } s1;
2518         struct uvxh_rh_gam_mmr_overlay_config_mmr_s {
2519                 unsigned long   rsvd_0_25:26;
2520                 unsigned long   base:20;                        /* RW */
2521                 unsigned long   rsvd_46_62:17;
2522                 unsigned long   enable:1;                       /* RW */
2523         } sx;
2524         struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
2525                 unsigned long   rsvd_0_25:26;
2526                 unsigned long   base:20;                        /* RW */
2527                 unsigned long   rsvd_46_62:17;
2528                 unsigned long   enable:1;                       /* RW */
2529         } s2;
2530         struct uv3h_rh_gam_mmr_overlay_config_mmr_s {
2531                 unsigned long   rsvd_0_25:26;
2532                 unsigned long   base:20;                        /* RW */
2533                 unsigned long   rsvd_46_62:17;
2534                 unsigned long   enable:1;                       /* RW */
2535         } s3;
2536 };
2537
2538 /* ========================================================================= */
2539 /*                                 UVH_RTC                                   */
2540 /* ========================================================================= */
2541 #define UVH_RTC 0x340000UL
2542
2543 #define UVH_RTC_REAL_TIME_CLOCK_SHFT                    0
2544 #define UVH_RTC_REAL_TIME_CLOCK_MASK                    0x00ffffffffffffffUL
2545
2546 union uvh_rtc_u {
2547         unsigned long   v;
2548         struct uvh_rtc_s {
2549                 unsigned long   real_time_clock:56;             /* RW */
2550                 unsigned long   rsvd_56_63:8;
2551         } s;
2552 };
2553
2554 /* ========================================================================= */
2555 /*                           UVH_RTC1_INT_CONFIG                             */
2556 /* ========================================================================= */
2557 #define UVH_RTC1_INT_CONFIG 0x615c0UL
2558
2559 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT                 0
2560 #define UVH_RTC1_INT_CONFIG_DM_SHFT                     8
2561 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT               11
2562 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT                 12
2563 #define UVH_RTC1_INT_CONFIG_P_SHFT                      13
2564 #define UVH_RTC1_INT_CONFIG_T_SHFT                      15
2565 #define UVH_RTC1_INT_CONFIG_M_SHFT                      16
2566 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT                32
2567 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK                 0x00000000000000ffUL
2568 #define UVH_RTC1_INT_CONFIG_DM_MASK                     0x0000000000000700UL
2569 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK               0x0000000000000800UL
2570 #define UVH_RTC1_INT_CONFIG_STATUS_MASK                 0x0000000000001000UL
2571 #define UVH_RTC1_INT_CONFIG_P_MASK                      0x0000000000002000UL
2572 #define UVH_RTC1_INT_CONFIG_T_MASK                      0x0000000000008000UL
2573 #define UVH_RTC1_INT_CONFIG_M_MASK                      0x0000000000010000UL
2574 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
2575
2576 union uvh_rtc1_int_config_u {
2577         unsigned long   v;
2578         struct uvh_rtc1_int_config_s {
2579                 unsigned long   vector_:8;                      /* RW */
2580                 unsigned long   dm:3;                           /* RW */
2581                 unsigned long   destmode:1;                     /* RW */
2582                 unsigned long   status:1;                       /* RO */
2583                 unsigned long   p:1;                            /* RO */
2584                 unsigned long   rsvd_14:1;
2585                 unsigned long   t:1;                            /* RO */
2586                 unsigned long   m:1;                            /* RW */
2587                 unsigned long   rsvd_17_31:15;
2588                 unsigned long   apic_id:32;                     /* RW */
2589         } s;
2590 };
2591
2592 /* ========================================================================= */
2593 /*                               UVH_SCRATCH5                                */
2594 /* ========================================================================= */
2595 #define UVH_SCRATCH5 0x2d0200UL
2596 #define UVH_SCRATCH5_32 0x778
2597
2598 #define UVH_SCRATCH5_SCRATCH5_SHFT                      0
2599 #define UVH_SCRATCH5_SCRATCH5_MASK                      0xffffffffffffffffUL
2600
2601 union uvh_scratch5_u {
2602         unsigned long   v;
2603         struct uvh_scratch5_s {
2604                 unsigned long   scratch5:64;                    /* RW, W1CS */
2605         } s;
2606 };
2607
2608 /* ========================================================================= */
2609 /*                          UVXH_EVENT_OCCURRED2                             */
2610 /* ========================================================================= */
2611 #define UVXH_EVENT_OCCURRED2 0x70100UL
2612 #define UVXH_EVENT_OCCURRED2_32 0xb68
2613
2614 #define UVXH_EVENT_OCCURRED2_RTC_0_SHFT                 0
2615 #define UVXH_EVENT_OCCURRED2_RTC_1_SHFT                 1
2616 #define UVXH_EVENT_OCCURRED2_RTC_2_SHFT                 2
2617 #define UVXH_EVENT_OCCURRED2_RTC_3_SHFT                 3
2618 #define UVXH_EVENT_OCCURRED2_RTC_4_SHFT                 4
2619 #define UVXH_EVENT_OCCURRED2_RTC_5_SHFT                 5
2620 #define UVXH_EVENT_OCCURRED2_RTC_6_SHFT                 6
2621 #define UVXH_EVENT_OCCURRED2_RTC_7_SHFT                 7
2622 #define UVXH_EVENT_OCCURRED2_RTC_8_SHFT                 8
2623 #define UVXH_EVENT_OCCURRED2_RTC_9_SHFT                 9
2624 #define UVXH_EVENT_OCCURRED2_RTC_10_SHFT                10
2625 #define UVXH_EVENT_OCCURRED2_RTC_11_SHFT                11
2626 #define UVXH_EVENT_OCCURRED2_RTC_12_SHFT                12
2627 #define UVXH_EVENT_OCCURRED2_RTC_13_SHFT                13
2628 #define UVXH_EVENT_OCCURRED2_RTC_14_SHFT                14
2629 #define UVXH_EVENT_OCCURRED2_RTC_15_SHFT                15
2630 #define UVXH_EVENT_OCCURRED2_RTC_16_SHFT                16
2631 #define UVXH_EVENT_OCCURRED2_RTC_17_SHFT                17
2632 #define UVXH_EVENT_OCCURRED2_RTC_18_SHFT                18
2633 #define UVXH_EVENT_OCCURRED2_RTC_19_SHFT                19
2634 #define UVXH_EVENT_OCCURRED2_RTC_20_SHFT                20
2635 #define UVXH_EVENT_OCCURRED2_RTC_21_SHFT                21
2636 #define UVXH_EVENT_OCCURRED2_RTC_22_SHFT                22
2637 #define UVXH_EVENT_OCCURRED2_RTC_23_SHFT                23
2638 #define UVXH_EVENT_OCCURRED2_RTC_24_SHFT                24
2639 #define UVXH_EVENT_OCCURRED2_RTC_25_SHFT                25
2640 #define UVXH_EVENT_OCCURRED2_RTC_26_SHFT                26
2641 #define UVXH_EVENT_OCCURRED2_RTC_27_SHFT                27
2642 #define UVXH_EVENT_OCCURRED2_RTC_28_SHFT                28
2643 #define UVXH_EVENT_OCCURRED2_RTC_29_SHFT                29
2644 #define UVXH_EVENT_OCCURRED2_RTC_30_SHFT                30
2645 #define UVXH_EVENT_OCCURRED2_RTC_31_SHFT                31
2646 #define UVXH_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000000001UL
2647 #define UVXH_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000000002UL
2648 #define UVXH_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000000004UL
2649 #define UVXH_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000000008UL
2650 #define UVXH_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000000010UL
2651 #define UVXH_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000000020UL
2652 #define UVXH_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000000000040UL
2653 #define UVXH_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000000000080UL
2654 #define UVXH_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000000000100UL
2655 #define UVXH_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000000000200UL
2656 #define UVXH_EVENT_OCCURRED2_RTC_10_MASK                0x0000000000000400UL
2657 #define UVXH_EVENT_OCCURRED2_RTC_11_MASK                0x0000000000000800UL
2658 #define UVXH_EVENT_OCCURRED2_RTC_12_MASK                0x0000000000001000UL
2659 #define UVXH_EVENT_OCCURRED2_RTC_13_MASK                0x0000000000002000UL
2660 #define UVXH_EVENT_OCCURRED2_RTC_14_MASK                0x0000000000004000UL
2661 #define UVXH_EVENT_OCCURRED2_RTC_15_MASK                0x0000000000008000UL
2662 #define UVXH_EVENT_OCCURRED2_RTC_16_MASK                0x0000000000010000UL
2663 #define UVXH_EVENT_OCCURRED2_RTC_17_MASK                0x0000000000020000UL
2664 #define UVXH_EVENT_OCCURRED2_RTC_18_MASK                0x0000000000040000UL
2665 #define UVXH_EVENT_OCCURRED2_RTC_19_MASK                0x0000000000080000UL
2666 #define UVXH_EVENT_OCCURRED2_RTC_20_MASK                0x0000000000100000UL
2667 #define UVXH_EVENT_OCCURRED2_RTC_21_MASK                0x0000000000200000UL
2668 #define UVXH_EVENT_OCCURRED2_RTC_22_MASK                0x0000000000400000UL
2669 #define UVXH_EVENT_OCCURRED2_RTC_23_MASK                0x0000000000800000UL
2670 #define UVXH_EVENT_OCCURRED2_RTC_24_MASK                0x0000000001000000UL
2671 #define UVXH_EVENT_OCCURRED2_RTC_25_MASK                0x0000000002000000UL
2672 #define UVXH_EVENT_OCCURRED2_RTC_26_MASK                0x0000000004000000UL
2673 #define UVXH_EVENT_OCCURRED2_RTC_27_MASK                0x0000000008000000UL
2674 #define UVXH_EVENT_OCCURRED2_RTC_28_MASK                0x0000000010000000UL
2675 #define UVXH_EVENT_OCCURRED2_RTC_29_MASK                0x0000000020000000UL
2676 #define UVXH_EVENT_OCCURRED2_RTC_30_MASK                0x0000000040000000UL
2677 #define UVXH_EVENT_OCCURRED2_RTC_31_MASK                0x0000000080000000UL
2678
2679 union uvxh_event_occurred2_u {
2680         unsigned long   v;
2681         struct uvxh_event_occurred2_s {
2682                 unsigned long   rtc_0:1;                        /* RW */
2683                 unsigned long   rtc_1:1;                        /* RW */
2684                 unsigned long   rtc_2:1;                        /* RW */
2685                 unsigned long   rtc_3:1;                        /* RW */
2686                 unsigned long   rtc_4:1;                        /* RW */
2687                 unsigned long   rtc_5:1;                        /* RW */
2688                 unsigned long   rtc_6:1;                        /* RW */
2689                 unsigned long   rtc_7:1;                        /* RW */
2690                 unsigned long   rtc_8:1;                        /* RW */
2691                 unsigned long   rtc_9:1;                        /* RW */
2692                 unsigned long   rtc_10:1;                       /* RW */
2693                 unsigned long   rtc_11:1;                       /* RW */
2694                 unsigned long   rtc_12:1;                       /* RW */
2695                 unsigned long   rtc_13:1;                       /* RW */
2696                 unsigned long   rtc_14:1;                       /* RW */
2697                 unsigned long   rtc_15:1;                       /* RW */
2698                 unsigned long   rtc_16:1;                       /* RW */
2699                 unsigned long   rtc_17:1;                       /* RW */
2700                 unsigned long   rtc_18:1;                       /* RW */
2701                 unsigned long   rtc_19:1;                       /* RW */
2702                 unsigned long   rtc_20:1;                       /* RW */
2703                 unsigned long   rtc_21:1;                       /* RW */
2704                 unsigned long   rtc_22:1;                       /* RW */
2705                 unsigned long   rtc_23:1;                       /* RW */
2706                 unsigned long   rtc_24:1;                       /* RW */
2707                 unsigned long   rtc_25:1;                       /* RW */
2708                 unsigned long   rtc_26:1;                       /* RW */
2709                 unsigned long   rtc_27:1;                       /* RW */
2710                 unsigned long   rtc_28:1;                       /* RW */
2711                 unsigned long   rtc_29:1;                       /* RW */
2712                 unsigned long   rtc_30:1;                       /* RW */
2713                 unsigned long   rtc_31:1;                       /* RW */
2714                 unsigned long   rsvd_32_63:32;
2715         } sx;
2716 };
2717
2718 /* ========================================================================= */
2719 /*                       UVXH_EVENT_OCCURRED2_ALIAS                          */
2720 /* ========================================================================= */
2721 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
2722 #define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70
2723
2724
2725 /* ========================================================================= */
2726 /*                   UVXH_LB_BAU_SB_ACTIVATION_STATUS_2                      */
2727 /* ========================================================================= */
2728 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
2729 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
2730 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
2731 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
2732 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL
2733 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL
2734
2735 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
2736 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
2737
2738 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
2739 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
2740
2741 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
2742 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
2743
2744 union uvxh_lb_bau_sb_activation_status_2_u {
2745         unsigned long   v;
2746         struct uvxh_lb_bau_sb_activation_status_2_s {
2747                 unsigned long   aux_error:64;                   /* RW */
2748         } sx;
2749         struct uv2h_lb_bau_sb_activation_status_2_s {
2750                 unsigned long   aux_error:64;                   /* RW */
2751         } s2;
2752         struct uv3h_lb_bau_sb_activation_status_2_s {
2753                 unsigned long   aux_error:64;                   /* RW */
2754         } s3;
2755 };
2756
2757 /* ========================================================================= */
2758 /*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
2759 /* ========================================================================= */
2760 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK            0x320130UL
2761 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32         0x9f0
2762
2763 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
2764 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
2765
2766 union uv1h_lb_target_physical_apic_id_mask_u {
2767         unsigned long   v;
2768         struct uv1h_lb_target_physical_apic_id_mask_s {
2769                 unsigned long   bit_enables:32;                 /* RW */
2770                 unsigned long   rsvd_32_63:32;
2771         } s1;
2772 };
2773
2774 /* ========================================================================= */
2775 /*                   UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR                   */
2776 /* ========================================================================= */
2777 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR           0x1603000UL
2778
2779 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26
2780 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46
2781 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
2782 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL
2783 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL
2784 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
2785
2786 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u {
2787         unsigned long   v;
2788         struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s {
2789                 unsigned long   rsvd_0_25:26;
2790                 unsigned long   base:20;                        /* RW */
2791                 unsigned long   m_io:6;                         /* RW */
2792                 unsigned long   n_io:4;
2793                 unsigned long   rsvd_56_62:7;
2794                 unsigned long   enable:1;                       /* RW */
2795         } s3;
2796 };
2797
2798 /* ========================================================================= */
2799 /*                   UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR                   */
2800 /* ========================================================================= */
2801 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR           0x1604000UL
2802
2803 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26
2804 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46
2805 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
2806 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL
2807 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL
2808 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
2809
2810 union uv3h_rh_gam_mmioh_overlay_config1_mmr_u {
2811         unsigned long   v;
2812         struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s {
2813                 unsigned long   rsvd_0_25:26;
2814                 unsigned long   base:20;                        /* RW */
2815                 unsigned long   m_io:6;                         /* RW */
2816                 unsigned long   n_io:4;
2817                 unsigned long   rsvd_56_62:7;
2818                 unsigned long   enable:1;                       /* RW */
2819         } s3;
2820 };
2821
2822 /* ========================================================================= */
2823 /*                  UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR                   */
2824 /* ========================================================================= */
2825 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR          0x1603800UL
2826 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH    128
2827
2828 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
2829 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
2830
2831 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u {
2832         unsigned long   v;
2833         struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s {
2834                 unsigned long   nasid:15;                       /* RW */
2835                 unsigned long   rsvd_15_63:49;
2836         } s3;
2837 };
2838
2839 /* ========================================================================= */
2840 /*                  UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR                   */
2841 /* ========================================================================= */
2842 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR          0x1604800UL
2843 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH    128
2844
2845 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
2846 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
2847
2848 union uv3h_rh_gam_mmioh_redirect_config1_mmr_u {
2849         unsigned long   v;
2850         struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s {
2851                 unsigned long   nasid:15;                       /* RW */
2852                 unsigned long   rsvd_15_63:49;
2853         } s3;
2854 };
2855
2856
2857 #endif /* _ASM_X86_UV_UV_MMRS_H */