2 * vmx.h: VMX Architecture related definitions
3 * Copyright (c) 2004, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 * A few random additions are:
19 * Copyright (C) 2006 Qumranet
20 * Avi Kivity <avi@qumranet.com>
21 * Yaniv Kamay <yaniv@qumranet.com>
28 #include <linux/types.h>
29 #include <uapi/asm/vmx.h>
32 * Definitions of Primary Processor-Based VM-Execution Controls.
34 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
35 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
36 #define CPU_BASED_HLT_EXITING 0x00000080
37 #define CPU_BASED_INVLPG_EXITING 0x00000200
38 #define CPU_BASED_MWAIT_EXITING 0x00000400
39 #define CPU_BASED_RDPMC_EXITING 0x00000800
40 #define CPU_BASED_RDTSC_EXITING 0x00001000
41 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000
42 #define CPU_BASED_CR3_STORE_EXITING 0x00010000
43 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
44 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
45 #define CPU_BASED_TPR_SHADOW 0x00200000
46 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
47 #define CPU_BASED_MOV_DR_EXITING 0x00800000
48 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
49 #define CPU_BASED_USE_IO_BITMAPS 0x02000000
50 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000
51 #define CPU_BASED_MONITOR_EXITING 0x20000000
52 #define CPU_BASED_PAUSE_EXITING 0x40000000
53 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
55 * Definitions of Secondary Processor-Based VM-Execution Controls.
57 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
58 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002
59 #define SECONDARY_EXEC_RDTSCP 0x00000008
60 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020
61 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
62 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
63 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
64 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
67 #define PIN_BASED_EXT_INTR_MASK 0x00000001
68 #define PIN_BASED_NMI_EXITING 0x00000008
69 #define PIN_BASED_VIRTUAL_NMIS 0x00000020
71 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000002
72 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
73 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
74 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
75 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
76 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
77 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
78 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
79 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
81 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000002
82 #define VM_ENTRY_IA32E_MODE 0x00000200
83 #define VM_ENTRY_SMM 0x00000400
84 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
85 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
86 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
87 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
91 VIRTUAL_PROCESSOR_ID = 0x00000000,
92 GUEST_ES_SELECTOR = 0x00000800,
93 GUEST_CS_SELECTOR = 0x00000802,
94 GUEST_SS_SELECTOR = 0x00000804,
95 GUEST_DS_SELECTOR = 0x00000806,
96 GUEST_FS_SELECTOR = 0x00000808,
97 GUEST_GS_SELECTOR = 0x0000080a,
98 GUEST_LDTR_SELECTOR = 0x0000080c,
99 GUEST_TR_SELECTOR = 0x0000080e,
100 HOST_ES_SELECTOR = 0x00000c00,
101 HOST_CS_SELECTOR = 0x00000c02,
102 HOST_SS_SELECTOR = 0x00000c04,
103 HOST_DS_SELECTOR = 0x00000c06,
104 HOST_FS_SELECTOR = 0x00000c08,
105 HOST_GS_SELECTOR = 0x00000c0a,
106 HOST_TR_SELECTOR = 0x00000c0c,
107 IO_BITMAP_A = 0x00002000,
108 IO_BITMAP_A_HIGH = 0x00002001,
109 IO_BITMAP_B = 0x00002002,
110 IO_BITMAP_B_HIGH = 0x00002003,
111 MSR_BITMAP = 0x00002004,
112 MSR_BITMAP_HIGH = 0x00002005,
113 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
114 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
115 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
116 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
117 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
118 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
119 TSC_OFFSET = 0x00002010,
120 TSC_OFFSET_HIGH = 0x00002011,
121 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
122 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
123 APIC_ACCESS_ADDR = 0x00002014,
124 APIC_ACCESS_ADDR_HIGH = 0x00002015,
125 EPT_POINTER = 0x0000201a,
126 EPT_POINTER_HIGH = 0x0000201b,
127 GUEST_PHYSICAL_ADDRESS = 0x00002400,
128 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
129 VMCS_LINK_POINTER = 0x00002800,
130 VMCS_LINK_POINTER_HIGH = 0x00002801,
131 GUEST_IA32_DEBUGCTL = 0x00002802,
132 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
133 GUEST_IA32_PAT = 0x00002804,
134 GUEST_IA32_PAT_HIGH = 0x00002805,
135 GUEST_IA32_EFER = 0x00002806,
136 GUEST_IA32_EFER_HIGH = 0x00002807,
137 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
138 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
139 GUEST_PDPTR0 = 0x0000280a,
140 GUEST_PDPTR0_HIGH = 0x0000280b,
141 GUEST_PDPTR1 = 0x0000280c,
142 GUEST_PDPTR1_HIGH = 0x0000280d,
143 GUEST_PDPTR2 = 0x0000280e,
144 GUEST_PDPTR2_HIGH = 0x0000280f,
145 GUEST_PDPTR3 = 0x00002810,
146 GUEST_PDPTR3_HIGH = 0x00002811,
147 HOST_IA32_PAT = 0x00002c00,
148 HOST_IA32_PAT_HIGH = 0x00002c01,
149 HOST_IA32_EFER = 0x00002c02,
150 HOST_IA32_EFER_HIGH = 0x00002c03,
151 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
152 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
153 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
154 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
155 EXCEPTION_BITMAP = 0x00004004,
156 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
157 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
158 CR3_TARGET_COUNT = 0x0000400a,
159 VM_EXIT_CONTROLS = 0x0000400c,
160 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
161 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
162 VM_ENTRY_CONTROLS = 0x00004012,
163 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
164 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
165 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
166 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
167 TPR_THRESHOLD = 0x0000401c,
168 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
169 PLE_GAP = 0x00004020,
170 PLE_WINDOW = 0x00004022,
171 VM_INSTRUCTION_ERROR = 0x00004400,
172 VM_EXIT_REASON = 0x00004402,
173 VM_EXIT_INTR_INFO = 0x00004404,
174 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
175 IDT_VECTORING_INFO_FIELD = 0x00004408,
176 IDT_VECTORING_ERROR_CODE = 0x0000440a,
177 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
178 VMX_INSTRUCTION_INFO = 0x0000440e,
179 GUEST_ES_LIMIT = 0x00004800,
180 GUEST_CS_LIMIT = 0x00004802,
181 GUEST_SS_LIMIT = 0x00004804,
182 GUEST_DS_LIMIT = 0x00004806,
183 GUEST_FS_LIMIT = 0x00004808,
184 GUEST_GS_LIMIT = 0x0000480a,
185 GUEST_LDTR_LIMIT = 0x0000480c,
186 GUEST_TR_LIMIT = 0x0000480e,
187 GUEST_GDTR_LIMIT = 0x00004810,
188 GUEST_IDTR_LIMIT = 0x00004812,
189 GUEST_ES_AR_BYTES = 0x00004814,
190 GUEST_CS_AR_BYTES = 0x00004816,
191 GUEST_SS_AR_BYTES = 0x00004818,
192 GUEST_DS_AR_BYTES = 0x0000481a,
193 GUEST_FS_AR_BYTES = 0x0000481c,
194 GUEST_GS_AR_BYTES = 0x0000481e,
195 GUEST_LDTR_AR_BYTES = 0x00004820,
196 GUEST_TR_AR_BYTES = 0x00004822,
197 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
198 GUEST_ACTIVITY_STATE = 0X00004826,
199 GUEST_SYSENTER_CS = 0x0000482A,
200 HOST_IA32_SYSENTER_CS = 0x00004c00,
201 CR0_GUEST_HOST_MASK = 0x00006000,
202 CR4_GUEST_HOST_MASK = 0x00006002,
203 CR0_READ_SHADOW = 0x00006004,
204 CR4_READ_SHADOW = 0x00006006,
205 CR3_TARGET_VALUE0 = 0x00006008,
206 CR3_TARGET_VALUE1 = 0x0000600a,
207 CR3_TARGET_VALUE2 = 0x0000600c,
208 CR3_TARGET_VALUE3 = 0x0000600e,
209 EXIT_QUALIFICATION = 0x00006400,
210 GUEST_LINEAR_ADDRESS = 0x0000640a,
211 GUEST_CR0 = 0x00006800,
212 GUEST_CR3 = 0x00006802,
213 GUEST_CR4 = 0x00006804,
214 GUEST_ES_BASE = 0x00006806,
215 GUEST_CS_BASE = 0x00006808,
216 GUEST_SS_BASE = 0x0000680a,
217 GUEST_DS_BASE = 0x0000680c,
218 GUEST_FS_BASE = 0x0000680e,
219 GUEST_GS_BASE = 0x00006810,
220 GUEST_LDTR_BASE = 0x00006812,
221 GUEST_TR_BASE = 0x00006814,
222 GUEST_GDTR_BASE = 0x00006816,
223 GUEST_IDTR_BASE = 0x00006818,
224 GUEST_DR7 = 0x0000681a,
225 GUEST_RSP = 0x0000681c,
226 GUEST_RIP = 0x0000681e,
227 GUEST_RFLAGS = 0x00006820,
228 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
229 GUEST_SYSENTER_ESP = 0x00006824,
230 GUEST_SYSENTER_EIP = 0x00006826,
231 HOST_CR0 = 0x00006c00,
232 HOST_CR3 = 0x00006c02,
233 HOST_CR4 = 0x00006c04,
234 HOST_FS_BASE = 0x00006c06,
235 HOST_GS_BASE = 0x00006c08,
236 HOST_TR_BASE = 0x00006c0a,
237 HOST_GDTR_BASE = 0x00006c0c,
238 HOST_IDTR_BASE = 0x00006c0e,
239 HOST_IA32_SYSENTER_ESP = 0x00006c10,
240 HOST_IA32_SYSENTER_EIP = 0x00006c12,
241 HOST_RSP = 0x00006c14,
242 HOST_RIP = 0x00006c16,
246 * Interruption-information format
248 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
249 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
250 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
251 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
252 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
253 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
255 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
256 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
257 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
258 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
260 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
261 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
262 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
263 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
264 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
266 /* GUEST_INTERRUPTIBILITY_INFO flags. */
267 #define GUEST_INTR_STATE_STI 0x00000001
268 #define GUEST_INTR_STATE_MOV_SS 0x00000002
269 #define GUEST_INTR_STATE_SMI 0x00000004
270 #define GUEST_INTR_STATE_NMI 0x00000008
272 /* GUEST_ACTIVITY_STATE flags */
273 #define GUEST_ACTIVITY_ACTIVE 0
274 #define GUEST_ACTIVITY_HLT 1
275 #define GUEST_ACTIVITY_SHUTDOWN 2
276 #define GUEST_ACTIVITY_WAIT_SIPI 3
279 * Exit Qualifications for MOV for Control Register Access
281 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
282 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
283 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
284 #define LMSW_SOURCE_DATA_SHIFT 16
285 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
286 #define REG_EAX (0 << 8)
287 #define REG_ECX (1 << 8)
288 #define REG_EDX (2 << 8)
289 #define REG_EBX (3 << 8)
290 #define REG_ESP (4 << 8)
291 #define REG_EBP (5 << 8)
292 #define REG_ESI (6 << 8)
293 #define REG_EDI (7 << 8)
294 #define REG_R8 (8 << 8)
295 #define REG_R9 (9 << 8)
296 #define REG_R10 (10 << 8)
297 #define REG_R11 (11 << 8)
298 #define REG_R12 (12 << 8)
299 #define REG_R13 (13 << 8)
300 #define REG_R14 (14 << 8)
301 #define REG_R15 (15 << 8)
304 * Exit Qualifications for MOV for Debug Register Access
306 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
307 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
308 #define TYPE_MOV_TO_DR (0 << 4)
309 #define TYPE_MOV_FROM_DR (1 << 4)
310 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
314 * Exit Qualifications for APIC-Access
316 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
317 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
318 #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
319 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
320 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
321 #define TYPE_LINEAR_APIC_EVENT (3 << 12)
322 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
323 #define TYPE_PHYSICAL_APIC_INST (15 << 12)
326 #define SEGMENT_AR_L_MASK (1 << 13)
328 #define AR_TYPE_ACCESSES_MASK 1
329 #define AR_TYPE_READABLE_MASK (1 << 1)
330 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
331 #define AR_TYPE_CODE_MASK (1 << 3)
332 #define AR_TYPE_MASK 0x0f
333 #define AR_TYPE_BUSY_64_TSS 11
334 #define AR_TYPE_BUSY_32_TSS 11
335 #define AR_TYPE_BUSY_16_TSS 3
336 #define AR_TYPE_LDT 2
338 #define AR_UNUSABLE_MASK (1 << 16)
339 #define AR_S_MASK (1 << 4)
340 #define AR_P_MASK (1 << 7)
341 #define AR_L_MASK (1 << 13)
342 #define AR_DB_MASK (1 << 14)
343 #define AR_G_MASK (1 << 15)
344 #define AR_DPL_SHIFT 5
345 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
347 #define AR_RESERVD_MASK 0xfffe0f00
349 #define TSS_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 0)
350 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 1)
351 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 2)
353 #define VMX_NR_VPIDS (1 << 16)
354 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
355 #define VMX_VPID_EXTENT_ALL_CONTEXT 2
357 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
358 #define VMX_EPT_EXTENT_CONTEXT 1
359 #define VMX_EPT_EXTENT_GLOBAL 2
361 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
362 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
363 #define VMX_EPTP_UC_BIT (1ull << 8)
364 #define VMX_EPTP_WB_BIT (1ull << 14)
365 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
366 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
367 #define VMX_EPT_AD_BIT (1ull << 21)
368 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
369 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
371 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
372 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
374 #define VMX_EPT_DEFAULT_GAW 3
375 #define VMX_EPT_MAX_GAW 0x4
376 #define VMX_EPT_MT_EPTE_SHIFT 3
377 #define VMX_EPT_GAW_EPTP_SHIFT 3
378 #define VMX_EPT_AD_ENABLE_BIT (1ull << 6)
379 #define VMX_EPT_DEFAULT_MT 0x6ull
380 #define VMX_EPT_READABLE_MASK 0x1ull
381 #define VMX_EPT_WRITABLE_MASK 0x2ull
382 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
383 #define VMX_EPT_IPAT_BIT (1ull << 6)
384 #define VMX_EPT_ACCESS_BIT (1ull << 8)
385 #define VMX_EPT_DIRTY_BIT (1ull << 9)
387 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
390 #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
391 #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
392 #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
393 #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
394 #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
395 #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
396 #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
397 #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
398 #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
399 #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
400 #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
402 struct vmx_msr_entry {
409 * Exit Qualifications for entry failure during or after loading guest state
411 #define ENTRY_FAIL_DEFAULT 0
412 #define ENTRY_FAIL_PDPTE 2
413 #define ENTRY_FAIL_NMI 3
414 #define ENTRY_FAIL_VMCS_LINK_PTR 4
417 * VM-instruction error numbers
419 enum vm_instruction_error_number {
420 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
421 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
422 VMXERR_VMCLEAR_VMXON_POINTER = 3,
423 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
424 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
425 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
426 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
427 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
428 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
429 VMXERR_VMPTRLD_VMXON_POINTER = 10,
430 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
431 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
432 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
433 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
434 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
435 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
436 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
437 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
438 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
439 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
440 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
441 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
442 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
443 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
444 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,